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Start of Pipeline - (32 sec in block)
node - (31 sec in block)
node block - (31 sec in block)
stage - (19 sec in block)Git Clone
stage block (Git Clone) - (19 sec in block)
sh - (0.45 sec in self)rm -rf *.xml
sh - (0.46 sec in self)rm -rf Cores-SweRV-EL2
sh - (17 sec in self)git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-SweRV-EL2 Cores-SweRV-EL2
stage - (2.1 sec in block)Verilog Convert
stage block (Verilog Convert) - (1.5 sec in block)
dir - (1 sec in block)Cores-SweRV-EL2
dir block - (0.67 sec in block)
sh - (0.46 sec in self)RV_ROOT=$(pwd) configs/veer.config -set=fpga_optimize=1 -target=default -set=btb_size=128
stage - (1 sec in block)Simulation
stage block (Simulation) - (0.41 sec in block)
getContext - (0.21 sec in self)
stage - (1 sec in block)Utilities
stage block (Utilities) - (0.37 sec in block)
getContext - (0.17 sec in self)
stage - (6.2 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5.2 sec in block)
getContext - (0.28 sec in self)
parallel - (4.5 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4.1 sec in block)
stage - (3.7 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.4 sec in block)
getContext - (0.39 sec in self)
stage - (0.93 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.34 sec in block)
getContext - (0.15 sec in self)
stage - (1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.71 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.17 sec in self)
stage - (1 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.54 sec in block)
junit - (0.27 sec in self)**/*.xml