Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Cores-SweRV-EL2
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf Cores-SweRV-EL2
[Pipeline] sh
+ git clone --recursive https://github.com/chipsalliance/Cores-SweRV-EL2 Cores-SweRV-EL2
Cloning into 'Cores-SweRV-EL2'...
Submodule 'third_party/cocotb' (https://github.com/cocotb/cocotb) registered for path 'third_party/cocotb'
Submodule 'third-party/picolibc' (https://github.com/picolibc/picolibc) registered for path 'third_party/picolibc'
Submodule 'third_party/riscv-dv' (https://github.com/chipsalliance/riscv-dv) registered for path 'third_party/riscv-dv'
Cloning into '/var/lib/jenkins/workspace/Cores-SweRV-EL2/Cores-SweRV-EL2/third_party/cocotb'...
Cloning into '/var/lib/jenkins/workspace/Cores-SweRV-EL2/Cores-SweRV-EL2/third_party/picolibc'...
Cloning into '/var/lib/jenkins/workspace/Cores-SweRV-EL2/Cores-SweRV-EL2/third_party/riscv-dv'...
Submodule path 'third_party/cocotb': checked out '7789fdf57ac1d509631c7f8eeb63cf455562bb96'
Submodule path 'third_party/picolibc': checked out '0694a78fc08b3300c7db79602c46ba0a64428c8e'
Submodule path 'third_party/riscv-dv': checked out '2c319b805fd1a5fa19b9f481362fe71d8d003f60'
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Cores-SweRV-EL2/Cores-SweRV-EL2
[Pipeline] {
[Pipeline] sh
+ iverilog -o simulation.out -g2012 -s el2_veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_mux.v design/dmi/dmi_wrapper.v design/dmi/rvjtag_tap.v design/el2_dma_ctrl.sv design/el2_mem.sv design/el2_pic_ctrl.sv design/el2_pmp.sv design/el2_veer.sv design/el2_veer_wrapper.sv design/dbg/el2_dbg.sv design/dec/el2_dec.sv design/dec/el2_dec_decode_ctl.sv design/dec/el2_dec_gpr_ctl.sv design/dec/el2_dec_ib_ctl.sv design/dec/el2_dec_pmp_ctl.sv design/dec/el2_dec_tlu_ctl.sv design/dec/el2_dec_trigger.sv design/exu/el2_exu.sv design/exu/el2_exu_alu_ctl.sv design/exu/el2_exu_div_ctl.sv design/exu/el2_exu_mul_ctl.sv design/ifu/el2_ifu.sv design/ifu/el2_ifu_aln_ctl.sv design/ifu/el2_ifu_bp_ctl.sv design/ifu/el2_ifu_compress_ctl.sv design/ifu/el2_ifu_ic_mem.sv design/ifu/el2_ifu_iccm_mem.sv design/ifu/el2_ifu_ifc_ctl.sv design/ifu/el2_ifu_mem_ctl.sv design/include/el2_def.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/el2_lib.sv design/lib/el2_mem_if.sv design/lib/mem_lib.sv design/lsu/el2_lsu.sv design/lsu/el2_lsu_addrcheck.sv design/lsu/el2_lsu_bus_buffer.sv design/lsu/el2_lsu_bus_intf.sv design/lsu/el2_lsu_clkdomain.sv design/lsu/el2_lsu_dccm_ctl.sv design/lsu/el2_lsu_dccm_mem.sv design/lsu/el2_lsu_ecc.sv design/lsu/el2_lsu_lsc_ctl.sv design/lsu/el2_lsu_trigger.sv
design/el2_dma_ctrl.sv:28: Include file el2_param.vh not found
design/el2_dma_ctrl.sv:25: syntax error
I give up.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Cores-SweRV-EL2/Cores-SweRV-EL2
[Pipeline] {
[Pipeline] sh
+ rm -rf LICENSE README.md configs design docs release-notes.md testbench third_party tools verification violations.waiver
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 2
Finished: FAILURE