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Start of Pipeline - (4 min 42 sec in block)
node - (4 min 42 sec in block)
node block - (4 min 41 sec in block)
stage - (40 sec in block)Git Clone
stage block (Git Clone) - (40 sec in block)
sh - (0.78 sec in self)rm -rf Cores-SweRV-EL2
sh - (39 sec in self)git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-SweRV-EL2 Cores-SweRV-EL2
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.95 sec in block)
dir - (0.57 sec in block)Cores-SweRV-EL2
dir block - (0.32 sec in block)
echo - (0.1 sec in self)simulation not supported for System Verilog files
stage - (1.6 sec in block)Utilities
stage block (Utilities) - (1.1 sec in block)
dir - (0.81 sec in block)Cores-SweRV-EL2
dir block - (0.58 sec in block)
sh - (0.39 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (3 min 56 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (3 min 55 sec in block)
parallel - (3 min 55 sec in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (6.2 sec in block)colorlight_i9
stage block (colorlight_i9) - (5.9 sec in block)
lock - (5.1 sec in block)colorlight_i9
lock block - (4.5 sec in block)
stage - (2.1 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1.6 sec in block)
dir - (1.1 sec in block)Cores-SweRV-EL2
dir block - (0.79 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.45 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-SweRV-EL2 -b colorlight_i9
stage - (0.96 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.67 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.38 sec in block)
getContext - (0.17 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (3 min 54 sec in block)
stage - (3 min 54 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3 min 53 sec in block)
lock - (3 min 53 sec in block)digilent_arty_a7_100t
lock block - (43 sec in block)
stage - (41 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (40 sec in block)
dir - (40 sec in block)Cores-SweRV-EL2
dir block - (39 sec in block)
echo - (0.32 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (39 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Cores-SweRV-EL2 -b digilent_arty_a7_100t
stage - (0.91 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.36 sec in block)
getContext - (0.16 sec in self)
stage - (0.68 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.17 sec in self)
stage - (0.73 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.51 sec in block)
junit - (0.26 sec in self)**/test-reports/*.xml