Skip to content

Console Output

+ pwd
+ RV_ROOT=/var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2 configs/veer.config -set=fpga_optimize=1 -target=default -set=btb_size=128
veer: Using target default
veer: Set(s) requested : fpga_optimize=1 btb_size=128
veer: Overriding btb_size value 512 with 128

VeeR configuration for target=default

veer: btb_fullya                     = 0
veer: btb_num_bypass                 = 8
veer: btb_toffset_size               = 12
veer: btb_addr_lo                    = 3
veer: btb_index1_lo                  = 3
veer: btb_size                       = 128
veer: btb_use_sram                   = 0
veer: btb_bypass_enable              = 1
veer: data_access_enable1            = 0x0
veer: data_access_mask3              = 0xffffffff
veer: inst_access_mask5              = 0xffffffff
veer: data_access_addr0              = 0x00000000
veer: inst_access_mask4              = 0xffffffff
veer: data_access_enable5            = 0x0
veer: data_access_mask7              = 0xffffffff
veer: inst_access_addr6              = 0x00000000
veer: data_access_addr2              = 0x00000000
veer: inst_access_mask1              = 0xffffffff
veer: inst_access_mask2              = 0xffffffff
veer: data_access_mask6              = 0xffffffff
veer: data_access_enable2            = 0x0
veer: data_access_addr1              = 0x00000000
veer: data_access_enable4            = 0x0
veer: inst_access_enable7            = 0x0
veer: inst_access_addr3              = 0x00000000
veer: inst_access_addr7              = 0x00000000
veer: inst_access_mask0              = 0xffffffff
veer: data_access_addr4              = 0x00000000
veer: inst_access_enable3            = 0x0
veer: data_access_addr5              = 0x00000000
veer: inst_access_enable6            = 0x0
veer: data_access_enable0            = 0x0
veer: data_access_enable7            = 0x0
veer: data_access_addr3              = 0x00000000
veer: inst_access_enable4            = 0x0
veer: inst_access_enable0            = 0x0
veer: data_access_enable3            = 0x0
veer: inst_access_addr5              = 0x00000000
veer: data_access_enable6            = 0x0
veer: data_access_mask0              = 0xffffffff
veer: inst_access_addr4              = 0x00000000
veer: data_access_addr7              = 0x00000000
veer: inst_access_enable2            = 0x0
veer: inst_access_mask6              = 0xffffffff
veer: data_access_mask2              = 0xffffffff
veer: inst_access_addr1              = 0x00000000
veer: inst_access_addr2              = 0x00000000
veer: data_access_addr6              = 0x00000000
veer: data_access_mask1              = 0xffffffff
veer: inst_access_mask3              = 0xffffffff
veer: inst_access_enable1            = 0x0
veer: inst_access_mask7              = 0xffffffff
veer: inst_access_addr0              = 0x00000000
veer: data_access_mask4              = 0xffffffff
veer: inst_access_enable5            = 0x0
veer: data_access_mask5              = 0xffffffff
veer: bht_size                       = 512
veer: bht_addr_lo                    = 3
veer: pic_meitp_offset               = 0x1800
veer: pic_meigwclr_mask              = 0x0
veer: pic_region                     = 0xf
veer: pic_size                       = 32
veer: pic_meie_offset                = 0x2000
veer: pic_meip_offset                = 0x1000
veer: pic_meigwctrl_offset           = 0x4000
veer: pic_mpiccfg_mask               = 0x1
veer: pic_meie_mask                  = 0x1
veer: pic_meipl_offset               = 0x0000
veer: pic_meip_mask                  = 0x0
veer: pic_meidels_offset             = 0x6000
veer: pic_2cycle                     = 1
veer: pic_meitp_mask                 = 0x0
veer: pic_total_int                  = 127
veer: pic_mpiccfg_offset             = 0x3000
veer: pic_meigwclr_offset            = 0x5000
veer: pic_meigwctrl_mask             = 0x3
veer: pic_meidels_mask               = 0x1
veer: pic_mpiccfg_count              = 1
veer: pic_offset                     = 0xc0000
veer: pic_meipl_mask                 = 0xf
veer: icache_num_ways                = 4
veer: icache_bypass_enable           = 1
veer: icache_2banks                  = 1
veer: icache_bank_width              = 8
veer: icache_enable                  = 1
veer: icache_waypack                 = 1
veer: icache_ln_sz                   = 64
veer: icache_ecc                     = 1
veer: icache_tag_bypass_enable       = 1
veer: icache_size                    = 32
veer: icache_banks_way               = 2
veer: icache_tag_num_bypass          = 2
veer: icache_num_bypass              = 4
veer: iccm_size                      = 64
veer: iccm_offset                    = 0xe000000
veer: iccm_region                    = 0xe
veer: iccm_num_banks                 = 4
veer: iccm_enable                    = 1
veer: dccm_num_banks                 = 8
veer: dccm_enable                    = 1
veer: dccm_offset                    = 0x40000
veer: dccm_region                    = 0xf
veer: dccm_size                      = 64
veer: ifu_bus_prty                   = 2
veer: ifu_bus_tag                    = 4
veer: ifu_bus_id                     = 1
veer: lsu_bus_id                     = 1
veer: sb_bus_prty                    = 2
veer: lsu_bus_prty                   = 2
veer: lsu_bus_tag                    = 4
veer: sb_bus_tag                     = 1
veer: dma_bus_tag                    = 1
veer: dma_bus_prty                   = 2
veer: dma_bus_id                     = 1
veer: bus_prty_default               = 3
veer: sb_bus_id                      = 1
veer: ret_stack_size                 = 4
veer: bitmanip_zbe                   = 0
veer: bitmanip_zbp                   = 0
veer: bitmanip_zbc                   = 1
veer: bitmanip_zbs                   = 1
veer: load_to_use_bus_plus1          = 0
veer: timer_legal_en                 = 1
veer: no_secondary_alu               = 0
veer: fast_interrupt_redirect        = 1
veer: bitmanip_zbr                   = 0
veer: dma_buf_depth                  = 5
veer: load_to_use_plus1              = 0
veer: lsu_num_nbload                 = 8
veer: fpga_optimize                  = 1
veer: atomic_enable                  = 1
veer: verilator                      = 
veer: bitmanip_zbb                   = 1
veer: bitmanip_zba                   = 1
veer: lsu_stbuf_depth                = 10
veer: num_threads                    = 1
veer: bitmanip_zbf                   = 0
veer: opensource                     = 0
veer: div_bit                        = 4
veer: div_new                        = 1
veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/eh2_pdef.vh
veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/eh2_param.vh
veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/common_defines.vh
veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/defines.h
veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/pd_defines.vh
veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/whisper.json
veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/perl_configs.pl
veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/link.ld