Console Output
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Baby-Risco-5 -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Makefile executed successfully.
Makefile output:
Building the Design...
/eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/build_digilent_arty_a7_100t.tcl
****** Vivado v2023.2 (64-bit)
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/build_digilent_arty_a7_100t.tcl
# read_verilog -sv /eda/processor_ci/rtl/Baby-Risco-5.sv
read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1319.988 ; gain = 0.023 ; free physical = 5205 ; free virtual = 28716
# read_verilog /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v
# read_verilog /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v
# read_verilog /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v
# read_verilog /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v
# read_verilog /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v
# read_verilog /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v
# read_verilog -sv /eda/processor-ci-controller/modules/uart.sv
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
# read_verilog -sv /eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/axi4_to_wishbone.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/axi4lite_to_wishbone.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv
# read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv
# set_param general.maxThreads 16
# read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
# set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
# synth_design -top "processorci_top" -part "xc7a100tcsg324-1"
Command: synth_design -top processorci_top -part xc7a100tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 2815649
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2031.719 ; gain = 403.660 ; free physical = 4248 ; free virtual = 27758
---------------------------------------------------------------------------------
WARNING: [Synth 8-10929] literal value 'd8 truncated to fit in 3 bits [/eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv:104]
WARNING: [Synth 8-10929] literal value 'd16 truncated to fit in 3 bits [/eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv:105]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16]
INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/Baby-Risco-5.sv:5]
INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
Parameter ID bound to: 1095914585 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 8192 - type: integer
INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/rtl/clk_divider.sv:1]
Parameter COUNTER_BITS bound to: 32 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/rtl/clk_divider.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/rtl/interpreter.sv:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter ID bound to: 1095914585 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/rtl/interpreter.sv:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:66]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:125]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:199]
INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.sv:199]
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/rtl/fifo.sv:1]
Parameter DEPTH bound to: 8 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/rtl/fifo.sv:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/rtl/memory.sv:1]
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 8192 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/rtl/controller.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Core' [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:1]
Parameter BOOT_ADDRESS bound to: 0 - type: integer
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:38]
INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:1]
INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:11]
INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:1]
WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/eda/processor_ci/rtl/Baby-Risco-5.sv:123]
WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 10 connections declared, but only 9 given [/eda/processor_ci/rtl/Baby-Risco-5.sv:123]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/rtl/reset.sv:1]
Parameter CYCLES bound to: 32'sb00000000000000000000000000010100
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/rtl/reset.sv:32]
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/rtl/reset.sv:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/Baby-Risco-5.sv:175]
WARNING: [Synth 8-7071] port 'rst_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/Baby-Risco-5.sv:175]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/Baby-Risco-5.sv:175]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/Baby-Risco-5.sv:5]
WARNING: [Synth 8-3848] Net intr_o in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:25]
WARNING: [Synth 8-3848] Net data_memory_ack in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:119]
WARNING: [Synth 8-3848] Net data_memory_read_data in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:120]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/Baby-Risco-5.sv:25]
WARNING: [Synth 8-7129] Port func7[6] in module ALU_Control is either unconnected or has no load
WARNING: [Synth 8-7129] Port func7[4] in module ALU_Control is either unconnected or has no load
WARNING: [Synth 8-7129] Port func7[3] in module ALU_Control is either unconnected or has no load
WARNING: [Synth 8-7129] Port func7[2] in module ALU_Control is either unconnected or has no load
WARNING: [Synth 8-7129] Port func7[1] in module ALU_Control is either unconnected or has no load
WARNING: [Synth 8-7129] Port func7[0] in module ALU_Control is either unconnected or has no load
WARNING: [Synth 8-7129] Port readRegister1[4] in module Registers is either unconnected or has no load
WARNING: [Synth 8-7129] Port readRegister2[4] in module Registers is either unconnected or has no load
WARNING: [Synth 8-7129] Port halt in module Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[31] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[30] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[29] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[28] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[27] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[26] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[25] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[24] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[23] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[22] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[21] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[20] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[19] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[18] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[17] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[16] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[15] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[14] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[13] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[1] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[0] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port intr_o in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port sck_i in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port cs_i in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port mosi_i in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port miso_o in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port rw_i in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port rst in module processorci_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2129.656 ; gain = 501.598 ; free physical = 4129 ; free virtual = 27640
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2147.469 ; gain = 519.410 ; free physical = 4127 ; free virtual = 27639
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2147.469 ; gain = 519.410 ; free physical = 4127 ; free virtual = 27639
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2147.469 ; gain = 0.000 ; free physical = 4128 ; free virtual = 27639
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2296.219 ; gain = 0.000 ; free physical = 4108 ; free virtual = 27619
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2296.254 ; gain = 0.000 ; free physical = 4111 ; free virtual = 27622
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4107 ; free virtual = 27618
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4107 ; free virtual = 27618
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4107 ; free virtual = 27618
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_read_fifo_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
READ | 001 | 0001
COPY_READ_BUFFER | 010 | 0100
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
COPY_WRITE_BUFFER | 001 | 0100
WRITE | 010 | 0101
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
TX_FIFO_IDLE | 0001 | 00
TX_FIFO_READ_FIFO | 0010 | 01
TX_FIFO_WRITE_TX | 0100 | 10
TX_FIFO_WAIT | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_read_fifo_state_reg' using encoding 'one-hot' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 0000 | 0000
VALIDATE_FETCH | 0001 | 1111
DECODE | 0010 | 0001
MEMADR | 0011 | 0010
MEMREAD | 0100 | 0011
iSTATE | 0101 | 0100
*
MEMWRITE | 0110 | 0101
EXECUTER | 0111 | 0110
EXECUTEI | 1000 | 1000
JAL | 1001 | 1001
BRANCH | 1010 | 1010
JALR | 1011 | 1011
AUIPC | 1100 | 1100
LUI | 1101 | 1101
ALUWB | 1110 | 0111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'Control_Unit'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
INIT | 001 | 00
RESET_COUNTER | 010 | 01
IDLE | 100 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4103 ; free virtual = 27616
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 2
2 Input 32 Bit Adders := 4
3 Input 32 Bit Adders := 1
2 Input 24 Bit Adders := 2
2 Input 10 Bit Adders := 2
2 Input 8 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 4
2 Input 3 Bit Adders := 6
+---XORs :
2 Input 32 Bit XORs := 1
+---Registers :
64 Bit Registers := 2
32 Bit Registers := 34
24 Bit Registers := 4
10 Bit Registers := 2
8 Bit Registers := 11
6 Bit Registers := 1
4 Bit Registers := 2
3 Bit Registers := 2
1 Bit Registers := 25
+---RAMs :
64K Bit (2048 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 1
2 Input 64 Bit Muxes := 1
48 Input 64 Bit Muxes := 2
5 Input 32 Bit Muxes := 2
2 Input 32 Bit Muxes := 9
8 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 2
48 Input 24 Bit Muxes := 1
48 Input 8 Bit Muxes := 2
2 Input 8 Bit Muxes := 4
24 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 2
3 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 7
15 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 2
9 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 4
2 Input 3 Bit Muxes := 5
10 Input 3 Bit Muxes := 1
3 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 13
48 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 4
15 Input 2 Bit Muxes := 3
2 Input 1 Bit Muxes := 62
48 Input 1 Bit Muxes := 22
3 Input 1 Bit Muxes := 5
4 Input 1 Bit Muxes := 3
5 Input 1 Bit Muxes := 11
15 Input 1 Bit Muxes := 10
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port readRegister1[4] in module Registers is either unconnected or has no load
WARNING: [Synth 8-7129] Port readRegister2[4] in module Registers is either unconnected or has no load
WARNING: [Synth 8-7129] Port halt in module Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[31] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[30] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[29] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[28] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[27] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[26] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[25] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[24] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[23] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[22] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[21] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[20] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[19] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[18] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[17] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[16] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[15] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[14] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[13] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[1] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port addr_i[0] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port intr_o in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port sck_i in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port cs_i in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port mosi_i in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port miso_o in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port rw_i in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port rst in module processorci_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4082 ; free virtual = 27602
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1 | LUT |
|Interpreter | memory_mux_selector | 256x1 | LUT |
+------------+---------------------+---------------+----------------+
Distributed RAM: Preliminary Mapping Report (see note below)
+-------------+-------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+-------------+-------------------------+-----------+----------------------+------------------+
|u_Controller | Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|u_Controller | Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|u_Controller | Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 |
+-------------+-------------------------+-----------+----------------------+------------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4074 ; free virtual = 27593
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4081 ; free virtual = 27600
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+-------------+-------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+-------------+-------------------------+-----------+----------------------+------------------+
|u_Controller | Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|u_Controller | Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|u_Controller | Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 |
+-------------+-------------------------+-----------+----------------------+------------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4081 ; free virtual = 27600
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4079 ; free virtual = 27598
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4078 ; free virtual = 27597
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4080 ; free virtual = 27600
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4080 ; free virtual = 27600
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4080 ; free virtual = 27600
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4080 ; free virtual = 27600
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 3|
|2 |CARRY4 | 87|
|3 |LUT1 | 66|
|4 |LUT2 | 209|
|5 |LUT3 | 329|
|6 |LUT4 | 188|
|7 |LUT5 | 393|
|8 |LUT6 | 868|
|9 |MUXF7 | 172|
|10 |MUXF8 | 64|
|11 |RAM256X1S | 256|
|12 |RAM32M | 2|
|13 |RAM32X1D | 4|
|14 |FDCE | 32|
|15 |FDRE | 1334|
|16 |FDSE | 4|
|17 |IBUF | 2|
|18 |OBUF | 1|
|19 |OBUFT | 2|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4080 ; free virtual = 27600
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 34 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2296.254 ; gain = 519.410 ; free physical = 4080 ; free virtual = 27600
Synthesis Optimization Complete : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2296.254 ; gain = 668.195 ; free physical = 4080 ; free virtual = 27600
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2296.254 ; gain = 0.000 ; free physical = 4358 ; free virtual = 27877
INFO: [Netlist 29-17] Analyzing 585 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2360.250 ; gain = 0.000 ; free physical = 4357 ; free virtual = 27876
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 262 instances were transformed.
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 1eed0e6a
INFO: [Common 17-83] Releasing license: Synthesis
69 Infos, 88 Warnings, 2 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:53 ; elapsed = 00:00:51 . Memory (MB): peak = 2360.285 ; gain = 1040.297 ; free physical = 4354 ; free virtual = 27874
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2038.357; main = 1752.189; forked = 428.709
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3246.539; main = 2360.254; forked = 982.332
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2424.281 ; gain = 63.996 ; free physical = 4353 ; free virtual = 27872
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 19a128cef
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2523.094 ; gain = 98.812 ; free physical = 4292 ; free virtual = 27811
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 19a128cef
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2771.000 ; gain = 0.000 ; free physical = 4022 ; free virtual = 27541
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 19a128cef
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2771.000 ; gain = 0.000 ; free physical = 4022 ; free virtual = 27541
Phase 1 Initialization | Checksum: 19a128cef
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2771.000 ; gain = 0.000 ; free physical = 4022 ; free virtual = 27541
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 19a128cef
Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2771.000 ; gain = 0.000 ; free physical = 4022 ; free virtual = 27541
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 19a128cef
Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2771.000 ; gain = 0.000 ; free physical = 4022 ; free virtual = 27541
Phase 2 Timer Update And Timing Data Collection | Checksum: 19a128cef
Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2771.000 ; gain = 0.000 ; free physical = 4022 ; free virtual = 27541
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 31 inverters resulting in an inversion of 93 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 1cc95c4c3
Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2771.000 ; gain = 0.000 ; free physical = 4022 ; free virtual = 27541
Retarget | Checksum: 1cc95c4c3
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 31 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 1e523b320
Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2771.000 ; gain = 0.000 ; free physical = 4022 ; free virtual = 27541
Constant propagation | Checksum: 1e523b320
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 15a917730
Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2771.000 ; gain = 0.000 ; free physical = 4022 ; free virtual = 27541
Sweep | Checksum: 15a917730
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 15a917730
Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2803.016 ; gain = 32.016 ; free physical = 4022 ; free virtual = 27541
BUFG optimization | Checksum: 15a917730
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 15a917730
Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2803.016 ; gain = 32.016 ; free physical = 4022 ; free virtual = 27541
Shift Register Optimization | Checksum: 15a917730
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 15a917730
Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2803.016 ; gain = 32.016 ; free physical = 4022 ; free virtual = 27541
Post Processing Netlist | Checksum: 15a917730
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1d003f8d7
Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2803.016 ; gain = 32.016 ; free physical = 4020 ; free virtual = 27540
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.016 ; gain = 0.000 ; free physical = 4020 ; free virtual = 27540
Phase 9.2 Verifying Netlist Connectivity | Checksum: 1d003f8d7
Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2803.016 ; gain = 32.016 ; free physical = 4020 ; free virtual = 27540
Phase 9 Finalization | Checksum: 1d003f8d7
Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2803.016 ; gain = 32.016 ; free physical = 4020 ; free virtual = 27540
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 31 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 1 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 1d003f8d7
Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2803.016 ; gain = 32.016 ; free physical = 4020 ; free virtual = 27540
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.016 ; gain = 0.000 ; free physical = 4020 ; free virtual = 27540
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1d003f8d7
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2803.016 ; gain = 0.000 ; free physical = 4023 ; free virtual = 27542
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1d003f8d7
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.016 ; gain = 0.000 ; free physical = 4023 ; free virtual = 27542
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.016 ; gain = 0.000 ; free physical = 4023 ; free virtual = 27542
Ending Netlist Obfuscation Task | Checksum: 1d003f8d7
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.016 ; gain = 0.000 ; free physical = 4023 ; free virtual = 27542
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2803.016 ; gain = 442.730 ; free physical = 4023 ; free virtual = 27542
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2835.031 ; gain = 0.000 ; free physical = 4023 ; free virtual = 27542
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: f1ab1db0
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2835.031 ; gain = 0.000 ; free physical = 4022 ; free virtual = 27542
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.031 ; gain = 0.000 ; free physical = 4022 ; free virtual = 27542
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b73a00aa
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2835.031 ; gain = 0.000 ; free physical = 4015 ; free virtual = 27535
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1b5d55095
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4013 ; free virtual = 27533
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1b5d55095
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4013 ; free virtual = 27533
Phase 1 Placer Initialization | Checksum: 1b5d55095
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4013 ; free virtual = 27533
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: d54453b2
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4005 ; free virtual = 27524
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: c212363c
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4003 ; free virtual = 27522
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: c212363c
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4002 ; free virtual = 27521
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 19562a759
Time (s): cpu = 00:00:11 ; elapsed = 00:00:04 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4001 ; free virtual = 27520
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 128 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 55 nets or LUTs. Breaked 0 LUT, combined 55 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.059 ; gain = 0.000 ; free physical = 4001 ; free virtual = 27520
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 55 | 55 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 55 | 55 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: af93b0ca
Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4001 ; free virtual = 27520
Phase 2.4 Global Placement Core | Checksum: ee40d306
Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4001 ; free virtual = 27520
Phase 2 Global Placement | Checksum: ee40d306
Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4001 ; free virtual = 27520
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 15ca81a08
Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4001 ; free virtual = 27520
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 134a8cb4a
Time (s): cpu = 00:00:13 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 3999 ; free virtual = 27518
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 149f57d53
Time (s): cpu = 00:00:13 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 3992 ; free virtual = 27511
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 18995c52b
Time (s): cpu = 00:00:13 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 3990 ; free virtual = 27509
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1eda6bd83
Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 20c185179
Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 24bb888c1
Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Phase 3 Detail Placement | Checksum: 24bb888c1
Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1a8af94b7
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.875 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 2671d1b8a
Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2842.059 ; gain = 0.000 ; free physical = 4008 ; free virtual = 27527
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 2671d1b8a
Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2842.059 ; gain = 0.000 ; free physical = 4008 ; free virtual = 27527
Phase 4.1.1.1 BUFG Insertion | Checksum: 1a8af94b7
Time (s): cpu = 00:00:18 ; elapsed = 00:00:07 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.875. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1defa3f34
Time (s): cpu = 00:00:18 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Time (s): cpu = 00:00:18 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Phase 4.1 Post Commit Optimization | Checksum: 1defa3f34
Time (s): cpu = 00:00:18 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1defa3f34
Time (s): cpu = 00:00:18 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 1x1|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1defa3f34
Time (s): cpu = 00:00:18 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Phase 4.3 Placer Reporting | Checksum: 1defa3f34
Time (s): cpu = 00:00:18 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.059 ; gain = 0.000 ; free physical = 4008 ; free virtual = 27527
Time (s): cpu = 00:00:18 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e9747ec1
Time (s): cpu = 00:00:18 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
Ending Placer Task | Checksum: 1933e7ff0
Time (s): cpu = 00:00:18 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.059 ; gain = 7.027 ; free physical = 4008 ; free virtual = 27527
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.059 ; gain = 39.043 ; free physical = 4008 ; free virtual = 27527
# report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
# report_utilization -file digilent_arty_a7_utilization_place.rpt
# report_io -file digilent_arty_a7_io.rpt
report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2842.059 ; gain = 0.000 ; free physical = 4007 ; free virtual = 27526
# report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2842.059 ; gain = 0.000 ; free physical = 4008 ; free virtual = 27527
# report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: baf28824 ConstDB: 0 ShapeSum: d84bf7cc RouteDB: 0
Post Restoration Checksum: NetGraph: 8bf0093a | NumContArr: 49f116e3 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 25b331557
Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3993 ; free virtual = 27512
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 25b331557
Time (s): cpu = 00:00:33 ; elapsed = 00:00:25 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3993 ; free virtual = 27512
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 25b331557
Time (s): cpu = 00:00:33 ; elapsed = 00:00:25 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3993 ; free virtual = 27512
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 168ba07e8
Time (s): cpu = 00:00:38 ; elapsed = 00:00:27 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3966 ; free virtual = 27486
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 |
Router Utilization Summary
Global Vertical Routing Utilization = 0.00892197 %
Global Horizontal Routing Utilization = 0.00106564 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 2836
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 2799
Number of Partially Routed Nets = 37
Number of Node Overlaps = 24
Phase 2 Router Initialization | Checksum: 1d7035c8e
Time (s): cpu = 00:00:40 ; elapsed = 00:00:27 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3966 ; free virtual = 27486
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 1d7035c8e
Time (s): cpu = 00:00:40 ; elapsed = 00:00:27 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3966 ; free virtual = 27486
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 26144baf8
Time (s): cpu = 00:00:41 ; elapsed = 00:00:28 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3966 ; free virtual = 27486
Phase 3 Initial Routing | Checksum: 26144baf8
Time (s): cpu = 00:00:41 ; elapsed = 00:00:28 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3966 ; free virtual = 27486
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 299
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.401 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1d0f1843f
Time (s): cpu = 00:00:45 ; elapsed = 00:00:29 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3968 ; free virtual = 27488
Phase 4 Rip-up And Reroute | Checksum: 1d0f1843f
Time (s): cpu = 00:00:45 ; elapsed = 00:00:29 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3968 ; free virtual = 27488
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1d0f1843f
Time (s): cpu = 00:00:45 ; elapsed = 00:00:29 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3968 ; free virtual = 27488
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1d0f1843f
Time (s): cpu = 00:00:45 ; elapsed = 00:00:29 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3968 ; free virtual = 27488
Phase 5 Delay and Skew Optimization | Checksum: 1d0f1843f
Time (s): cpu = 00:00:45 ; elapsed = 00:00:29 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3968 ; free virtual = 27488
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 25ce3a89b
Time (s): cpu = 00:00:45 ; elapsed = 00:00:29 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3960 ; free virtual = 27480
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.497 | TNS=0.000 | WHS=0.414 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 25ce3a89b
Time (s): cpu = 00:00:45 ; elapsed = 00:00:29 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3960 ; free virtual = 27480
Phase 6 Post Hold Fix | Checksum: 25ce3a89b
Time (s): cpu = 00:00:45 ; elapsed = 00:00:29 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3960 ; free virtual = 27480
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.660269 %
Global Horizontal Routing Utilization = 0.770958 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 25ce3a89b
Time (s): cpu = 00:00:45 ; elapsed = 00:00:29 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3960 ; free virtual = 27480
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 25ce3a89b
Time (s): cpu = 00:00:45 ; elapsed = 00:00:29 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3959 ; free virtual = 27478
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1f01e819e
Time (s): cpu = 00:00:46 ; elapsed = 00:00:29 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3961 ; free virtual = 27480
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.497 | TNS=0.000 | WHS=0.414 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1f01e819e
Time (s): cpu = 00:00:46 ; elapsed = 00:00:29 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3961 ; free virtual = 27480
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 16641b08e
Time (s): cpu = 00:00:46 ; elapsed = 00:00:30 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3961 ; free virtual = 27480
Ending Routing Task | Checksum: 16641b08e
Time (s): cpu = 00:00:46 ; elapsed = 00:00:30 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3961 ; free virtual = 27480
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:31 . Memory (MB): peak = 2898.086 ; gain = 0.000 ; free physical = 3953 ; free virtual = 27473
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (25073)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (13495)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (25073)
----------------------------
There are 2417 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[0]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[10]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[11]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[12]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[13]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[14]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[15]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[16]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[17]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[18]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[19]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[1]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[20]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[21]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[22]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[23]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[24]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[25]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[26]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[27]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[28]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[29]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[2]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[30]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[31]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[3]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[4]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[5]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[6]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[7]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[8]/Q (HIGH)
There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[9]/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (13495)
----------------------------------------------------
There are 13495 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (1)
-------------------------------
There is 1 port with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
8.522 0.000 0 1 0.430 0.000 0 1 4.500 0.000 0 2
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sck {0.000 50.000} 100.000 10.000
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 8.522 0.000 0 1 0.430 0.000 0 1 4.500 0.000 0 2
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_arty_a7_route_status.rpt
# report_drc -file digilent_arty_a7_drc.rpt
Command: report_drc -file digilent_arty_a7_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/digilent_arty_a7_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_arty_a7_power.rpt
Command: report_power -file digilent_arty_a7_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "digilent_arty_a7_100t.bit"
Command: write_bitstream -force digilent_arty_a7_100t.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_arty_a7_100t.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 3156.137 ; gain = 246.207 ; free physical = 3611 ; free virtual = 27134
# exit
INFO: [Common 17-206] Exiting Vivado at Sun Apr 27 00:31:12 2025...
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