Skipping 428 KB..
Full LogTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTest
Optimizing lut $abc$100137$lut$aiger100136$19028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$100137$lut$aiger100136$19142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19155.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$100137$lut$aiger100136$19192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$100137$lut$aiger100136$19245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$19681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$100137$lut$aiger100136$19781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$19967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$20013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$20056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$20089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$20111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$20158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$20174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$20199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$20218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$20234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$20267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$20283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$20293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$20309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$20325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$20341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$20386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$20386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$20409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$20409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$20430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$20430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$9282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$11460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$10395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$100137$lut$aiger100136$9422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$100137$lut$aiger100136$9430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$100137$lut$aiger100136$9430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$100137$lut$aiger100136$9441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$100137$lut$aiger100136$9445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$100137$lut$aiger100136$9458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$100137$lut$aiger100136$9467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$100137$lut$aiger100136$9498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$9548.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$9603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$9621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$9637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$9663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9710.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$100137$lut$aiger100136$9747.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$10134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$16640.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$9823.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$100137$lut$auto$opt_dff.cc:219:make_patterns_logic$3075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$100137$lut$auto$opt_dff.cc:219:make_patterns_logic$3247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$flatten\Controller.\Interpreter.$procmux$2270_Y.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$18277.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$100137$lut$auto$fsm_map.cc:170:map_fsm$2923[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$100137$lut$aiger100136$9792.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$100137$lut$aiger100136$14117.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100155.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100201.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100223.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100249.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100249.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100271.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100273.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100279.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100299.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100317.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100253.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100209.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100341.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Removed 0 unused cells and 11343 unused wires.
19.45. Executing AUTONAME pass.
Renamed 154994 objects in module processorci_top (108 iterations).
<suppressed ~11930 debug messages>
19.46. Executing HIERARCHY pass (managing design hierarchy).
19.46.1. Analyzing design hierarchy..
Top module: \processorci_top
19.46.2. Analyzing design hierarchy..
Top module: \processorci_top
Removed 0 unused modules.
19.47. Printing statistics.
=== processorci_top ===
Number of wires: 5667
Number of wire bits: 17210
Number of public wires: 5667
Number of public wire bits: 17210
Number of ports: 10
Number of port bits: 10
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 7463
$scopeinfo 11
CCU2C 142
L6MUX21 236
LUT4 4625
PFUMX 845
TRELLIS_DPR16X4 1028
TRELLIS_FF 576
19.48. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Found and reported 0 problems.
19.49. Executing JSON backend.
Warnings: 113 unique messages, 113 total
End of script. Logfile hash: a52f2027a9, CPU: user 16.88s system 0.17s, MEM: 165.94 MB peak
Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
Time spent: 24% 1x abc9_exe (5 sec), 14% 11x techmap (3 sec), ...
/eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \
--lpf /eda/processor-ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \
--speed 6 --lpf-allow-unconstrained --ignore-loops
/eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config --bit colorlight_i9.bit
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia
[Pipeline] {
[Pipeline] echo
FPGA colorlight_i9 bloqueada para flash.
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b colorlight_i9 -l
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/build_colorlight_i9.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
Loading: [===== ] 8.26%
Loading: [========= ] 16.52%
Loading: [============= ] 25.10%
Loading: [================= ] 33.68%
Loading: [====================== ] 42.25%
Loading: [========================== ] 50.83%
Loading: [============================== ] 59.41%
Loading: [================================== ] 67.67%
Loading: [======================================= ] 76.25%
Loading: [=========================================== ] 84.83%
Loading: [=============================================== ] 93.40%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] echo
Testando FPGA colorlight_i9.
[Pipeline] dir
Running in /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia
[Pipeline] {
[Pipeline] sh
+ PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py
Running tests...
----------------------------------------------------------------------
FFFFFFFFFF.FFFF
======================================================================
ERROR [0.106s]: test_addi (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 21, in test_addi
self.assertEqual(int.from_bytes(retorno, "big"), 5)
AssertionError: 0 != 5
======================================================================
ERROR [0.105s]: test_andi (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 28, in test_andi
self.assertEqual(int.from_bytes(retorno, "big"), 1)
AssertionError: 0 != 1
======================================================================
ERROR [0.105s]: test_jalr (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 112, in test_jalr
self.assertEqual(int.from_bytes(retorno, "big"), 7)
AssertionError: 0 != 7
======================================================================
ERROR [0.106s]: test_jalr_2 (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 119, in test_jalr_2
self.assertEqual(int.from_bytes(retorno, "big"), 7)
AssertionError: 0 != 7
======================================================================
ERROR [0.105s]: test_lb (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 105, in test_lb
self.assertEqual(int.from_bytes(retorno, "big"), 0xFF)
AssertionError: 0 != 255
======================================================================
ERROR [0.105s]: test_lh (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 98, in test_lh
self.assertEqual(int.from_bytes(retorno, "big"), 0xFFC0)
AssertionError: 0 != 65472
======================================================================
ERROR [0.105s]: test_lw (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 91, in test_lw
self.assertEqual(int.from_bytes(retorno, "big"), 0x809)
AssertionError: 0 != 2057
======================================================================
ERROR [0.105s]: test_ori (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 35, in test_ori
self.assertEqual(int.from_bytes(retorno, "big"), 7)
AssertionError: 0 != 7
======================================================================
ERROR [0.105s]: test_slli (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 70, in test_slli
self.assertEqual(int.from_bytes(retorno, "big"), 8)
AssertionError: 0 != 8
======================================================================
ERROR [0.105s]: test_slli_2 (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 77, in test_slli_2
self.assertEqual(int.from_bytes(retorno, "big"), 0x10)
AssertionError: 0 != 16
======================================================================
ERROR [0.105s]: test_slti_2 (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 56, in test_slti_2
self.assertEqual(int.from_bytes(retorno, "big"), 1)
AssertionError: 0 != 1
======================================================================
ERROR [0.105s]: test_sltiu (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 63, in test_sltiu
self.assertEqual(int.from_bytes(retorno, "big"), 1)
AssertionError: 0 != 1
======================================================================
ERROR [0.105s]: test_srli (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 84, in test_srli
self.assertEqual(int.from_bytes(retorno, "big"), 2)
AssertionError: 0 != 2
======================================================================
ERROR [0.105s]: test_xori (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_00.py", line 42, in test_xori
self.assertEqual(int.from_bytes(retorno, "big"), 6)
AssertionError: 0 != 6
----------------------------------------------------------------------
Ran 15 tests in 1.577s
FAILED (errors=14)
Generating XML reports...
Running tests...
----------------------------------------------------------------------
FFFF..FFFF
======================================================================
ERROR [0.105s]: test_add (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_01.py", line 21, in test_add
self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10
======================================================================
ERROR [0.106s]: test_and (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_01.py", line 35, in test_and
self.assertEqual(int.from_bytes(retorno, "big"), 1)
AssertionError: 0 != 1
======================================================================
ERROR [0.105s]: test_or (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_01.py", line 42, in test_or
self.assertEqual(int.from_bytes(retorno, "big"), 7)
AssertionError: 0 != 7
======================================================================
ERROR [0.105s]: test_sll (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_01.py", line 70, in test_sll
self.assertEqual(int.from_bytes(retorno, "big"), 8)
AssertionError: 0 != 8
======================================================================
ERROR [0.105s]: test_sra (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_01.py", line 84, in test_sra
self.assertEqual(int.from_bytes(retorno, "big"), 2)
AssertionError: 0 != 2
======================================================================
ERROR [0.105s]: test_srl (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_01.py", line 77, in test_srl
self.assertEqual(int.from_bytes(retorno, "big"), 2)
AssertionError: 0 != 2
======================================================================
ERROR [0.105s]: test_sub (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_01.py", line 28, in test_sub
self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10
======================================================================
ERROR [0.105s]: test_xor (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_01.py", line 49, in test_xor
self.assertEqual(int.from_bytes(retorno, "big"), 6)
AssertionError: 0 != 6
----------------------------------------------------------------------
Ran 10 tests in 1.051s
FAILED (errors=8)
Generating XML reports...
Running tests...
----------------------------------------------------------------------
FFF
======================================================================
ERROR [0.106s]: test_sb (test_02.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_02.py", line 35, in test_sb
self.assertEqual(int.from_bytes(retorno, "big"), 0xFE)
AssertionError: 0 != 254
======================================================================
ERROR [0.105s]: test_sh (test_02.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_02.py", line 28, in test_sh
self.assertEqual(int.from_bytes(retorno, "big"), 0xFFC0)
AssertionError: 0 != 65472
======================================================================
ERROR [0.105s]: test_sw (test_02.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_02.py", line 21, in test_sw
self.assertEqual(int.from_bytes(retorno, "big"), 0x1E)
AssertionError: 0 != 30
----------------------------------------------------------------------
Ran 3 tests in 0.316s
FAILED (errors=3)
Generating XML reports...
Running tests...
----------------------------------------------------------------------
FFFFFFFFFFFF
======================================================================
ERROR [0.105s]: test_beq (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_03.py", line 21, in test_beq
self.assertEqual(int.from_bytes(retorno, "big"), 0x11)
AssertionError: 0 != 17
======================================================================
ERROR [0.106s]: test_beq_2 (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_03.py", line 28, in test_beq_2
self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10
======================================================================
ERROR [0.105s]: test_bge (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_03.py", line 63, in test_bge
self.assertEqual(int.from_bytes(retorno, "big"), 0x11)
AssertionError: 0 != 17
======================================================================
ERROR [0.105s]: test_bge_2 (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_03.py", line 70, in test_bge_2
self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10
======================================================================
ERROR [0.106s]: test_bgeu (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_03.py", line 91, in test_bgeu
self.assertEqual(int.from_bytes(retorno, "big"), 0x11)
AssertionError: 0 != 17
======================================================================
ERROR [0.106s]: test_bgeu_2 (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_03.py", line 98, in test_bgeu_2
self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10
======================================================================
ERROR [0.106s]: test_blt (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_03.py", line 49, in test_blt
self.assertEqual(int.from_bytes(retorno, "big"), 0x11)
AssertionError: 0 != 17
======================================================================
ERROR [0.106s]: test_blt_2 (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_03.py", line 56, in test_blt_2
self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10
======================================================================
ERROR [0.105s]: test_bltu (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_03.py", line 77, in test_bltu
self.assertEqual(int.from_bytes(retorno, "big"), 0x11)
AssertionError: 0 != 17
======================================================================
ERROR [0.106s]: test_bltu_2 (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_03.py", line 84, in test_bltu_2
self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10
======================================================================
ERROR [0.105s]: test_bne (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_03.py", line 35, in test_bne
self.assertEqual(int.from_bytes(retorno, "big"), 0x11)
AssertionError: 0 != 17
======================================================================
ERROR [0.106s]: test_bne_2 (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_03.py", line 42, in test_bne_2
self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10
----------------------------------------------------------------------
Ran 12 tests in 1.268s
FAILED (errors=12)
Generating XML reports...
Running tests...
----------------------------------------------------------------------
FF
======================================================================
ERROR [0.105s]: test_auipc (test_04.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_04.py", line 21, in test_auipc
self.assertEqual(int.from_bytes(retorno, "big"), 0x000DA004)
AssertionError: 0 != 892932
======================================================================
ERROR [0.105s]: test_lui (test_04.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_04.py", line 28, in test_lui
self.assertEqual(int.from_bytes(retorno, "big"), 0x0006D000)
AssertionError: 0 != 446464
----------------------------------------------------------------------
Ran 2 tests in 0.210s
FAILED (errors=2)
Generating XML reports...
Running tests...
----------------------------------------------------------------------
FF
======================================================================
ERROR [0.106s]: test_jal (test_05.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_05.py", line 21, in test_jal
self.assertEqual(int.from_bytes(retorno, "big"), 0xA)
AssertionError: 0 != 10
======================================================================
ERROR [0.106s]: test_jal_2 (test_05.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/eda/processor-ci-communication/tests/test_05.py", line 28, in test_jal_2
self.assertEqual(int.from_bytes(retorno, "big"), 0xF)
AssertionError: 0 != 15
----------------------------------------------------------------------
Ran 2 tests in 0.212s
FAILED (errors=2)
Generating XML reports...
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/build_digilent_nexys4_ddr.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
Building the Design...
/eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/build_digilent_nexys4_ddr.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096"
****** Vivado v2023.2 (64-bit)
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/build_digilent_nexys4_ddr.tcl
# read_verilog /eda/processor-ci/rtl/AUK-V-Aethia.v
read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1304.219 ; gain = 0.023 ; free physical = 2663 ; free virtual = 26368
# read_verilog /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv.v
# read_verilog /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv_alu.v
# read_verilog /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv_csr_regfile.v
# read_verilog /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv_decode.v
# read_verilog /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv_execute.v
# read_verilog /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv_fetch.v
# read_verilog /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv_gpr_regfilie.v
# read_verilog /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv_mem.v
# set ID 0x6a6a6a6a
# set CLOCK_FREQ 50000000
# read_verilog /eda/processor-ci-controller/modules/uart.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
# read_verilog /eda/processor-ci-controller/src/fifo.v
# read_verilog /eda/processor-ci-controller/src/reset.v
# read_verilog /eda/processor-ci-controller/src/clk_divider.v
# read_verilog /eda/processor-ci-controller/src/memory.v
# read_verilog /eda/processor-ci-controller/src/interpreter.v
# read_verilog /eda/processor-ci-controller/src/controller.v
# set ID [lindex $argv 0]
# set CLOCK_FREQ [lindex $argv 1]
# set MEMORY_SIZE [lindex $argv 2]
# read_xdc "/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc"
# set_property PROCESSING_ORDER EARLY [get_files /eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
# synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE
Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 3327087
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2030.941 ; gain = 405.684 ; free physical = 1554 ; free virtual = 25259
---------------------------------------------------------------------------------
CRITICAL WARNING: [Synth 8-9339] data object 'reset_o' is already declared [/eda/processor-ci/rtl/AUK-V-Aethia.v:137]
INFO: [Synth 8-6826] previous declaration of 'reset_o' is from here [/eda/processor-ci/rtl/AUK-V-Aethia.v:29]
CRITICAL WARNING: [Synth 8-11152] second declaration of 'reset_o' is ignored [/eda/processor-ci/rtl/AUK-V-Aethia.v:137]
INFO: [Synth 8-11241] undeclared symbol 'de0_csr_sel', assumed default net type 'wire' [/var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv.v:234]
INFO: [Synth 8-11241] undeclared symbol 'de0_csr_we', assumed default net type 'wire' [/var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv.v:235]
INFO: [Synth 8-11241] undeclared symbol 'de0_csr_rd', assumed default net type 'wire' [/var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv.v:236]
INFO: [Synth 8-11241] undeclared symbol 'ex_dafe_zone', assumed default net type 'wire' [/var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv.v:255]
INFO: [Synth 8-11241] undeclared symbol 'exception_arr', assumed default net type 'wire' [/var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv.v:258]
INFO: [Synth 8-11241] undeclared symbol 'ex0_instr_valid', assumed default net type 'wire' [/var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv.v:320]
INFO: [Synth 8-11241] undeclared symbol 'ex0_wb_data_sel', assumed default net type 'wire' [/var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv.v:360]
INFO: [Synth 8-11241] undeclared symbol 'mcause_tmp', assumed default net type 'wire' [/var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv_csr_regfile.v:66]
INFO: [Synth 8-11241] undeclared symbol 'mtval_tmp', assumed default net type 'wire' [/var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv_csr_regfile.v:68]
WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv_decode.v:246]
WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv_decode.v:247]
INFO: [Synth 8-11241] undeclared symbol 'mem_wr', assumed default net type 'wire' [/var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/rtl/core/aukv_decode.v:342]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16]
WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15]
WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16]
WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17]
WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84]
WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85]
INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor-ci/rtl/AUK-V-Aethia.v:1]
INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
Parameter ID bound to: 0 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 4096 - type: integer
INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1]
Parameter COUNTER_BITS bound to: 32 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1]
INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer
Parameter BUS_WIDTH bound to: 32 - type: integer
Parameter ID bound to: 0 - type: integer
Parameter RESET_CLK_CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1]
Parameter CLK_FREQ bound to: 50000000 - type: integer
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
Parameter BUFFER_SIZE bound to: 8 - type: integer
Parameter WORD_SIZE_BY bound to: 4 - type: integer
INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213]
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1]
Parameter DEPTH bound to: 8 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
Parameter BIT_RATE bound to: 115200 - type: integer
Parameter CLK_HZ bound to: 50000000 - type: integer
Parameter PAYLOAD_BITS bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1]
Parameter MEMORY_FILE bound to: (null) - type: string
Parameter MEMORY_SIZE bound to: 4096 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1]
WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1]
Parameter CYCLES bound to: 20 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor-ci/rtl/AUK-V-Aethia.v:141]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor-ci/rtl/AUK-V-Aethia.v:141]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor-ci/rtl/AUK-V-Aethia.v:141]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor-ci/rtl/AUK-V-Aethia.v:1]
WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/AUK-V-Aethia.v:21]
WARNING: [Synth 8-3848] Net memory_read in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/AUK-V-Aethia.v:30]
WARNING: [Synth 8-3848] Net address in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/AUK-V-Aethia.v:32]
WARNING: [Synth 8-3848] Net memory_write in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/AUK-V-Aethia.v:30]
WARNING: [Synth 8-3848] Net data_address in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/AUK-V-Aethia.v:33]
WARNING: [Synth 8-3848] Net data_write in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/AUK-V-Aethia.v:33]
WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2114.910 ; gain = 489.652 ; free physical = 1453 ; free virtual = 25159
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2129.754 ; gain = 504.496 ; free physical = 1449 ; free virtual = 25155
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2129.754 ; gain = 504.496 ; free physical = 1449 ; free virtual = 25155
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2129.754 ; gain = 0.000 ; free physical = 1449 ; free virtual = 25155
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2282.504 ; gain = 0.000 ; free physical = 1485 ; free virtual = 25129
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2282.539 ; gain = 0.000 ; free physical = 1481 ; free virtual = 25127
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1436 ; free virtual = 25128
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1436 ; free virtual = 25128
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1436 ; free virtual = 25128
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
READ | 001 | 0001
COPY_READ_BUFFER | 010 | 0100
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
IDLE | 000 | 0000
COPY_WRITE_BUFFER | 001 | 0100
WRITE | 010 | 0001
WB | 011 | 0010
FINISH | 100 | 0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE | 0001 | 00
iSTATE0 | 0010 | 01
iSTATE1 | 0100 | 10
iSTATE2 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1425 ; free virtual = 25118
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 2
2 Input 32 Bit Adders := 6
2 Input 24 Bit Adders := 2
2 Input 10 Bit Adders := 2
2 Input 8 Bit Adders := 1
2 Input 6 Bit Adders := 4
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 2
+---Registers :
64 Bit Registers := 2
32 Bit Registers := 13
24 Bit Registers := 5
10 Bit Registers := 2
8 Bit Registers := 11
6 Bit Registers := 1
4 Bit Registers := 2
3 Bit Registers := 2
1 Bit Registers := 28
+---RAMs :
32K Bit (1024 X 32 bit) RAMs := 2
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
4 Input 64 Bit Muxes := 1
2 Input 64 Bit Muxes := 1
48 Input 64 Bit Muxes := 2
2 Input 32 Bit Muxes := 12
5 Input 32 Bit Muxes := 1
48 Input 24 Bit Muxes := 1
48 Input 8 Bit Muxes := 2
2 Input 8 Bit Muxes := 4
24 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 2
2 Input 6 Bit Muxes := 4
3 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 4
5 Input 3 Bit Muxes := 4
2 Input 3 Bit Muxes := 3
2 Input 2 Bit Muxes := 16
48 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 4
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 52
48 Input 1 Bit Muxes := 22
3 Input 1 Bit Muxes := 5
4 Input 1 Bit Muxes := 3
5 Input 1 Bit Muxes := 11
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1376 ; free virtual = 25075
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1 | LUT |
|Interpreter | memory_mux_selector | 256x1 | LUT |
+------------+---------------------+---------------+----------------+
Distributed RAM: Preliminary Mapping Report (see note below)
+----------------+------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------+------------------------------------+-----------+----------------------+------------------+
|processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
|processorci_top | Controller/Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+----------------+------------------------------------+-----------+----------------------+------------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1381 ; free virtual = 25080
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:06 ; elapsed = 00:01:07 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1374 ; free virtual = 25073
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+----------------+------------------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------+------------------------------------+-----------+----------------------+------------------+
|processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|processorci_top | Controller/Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
|processorci_top | Controller/Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 |
+----------------+------------------------------------+-----------+----------------------+------------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:08 ; elapsed = 00:01:09 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1374 ; free virtual = 25073
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1376 ; free virtual = 25075
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1376 ; free virtual = 25075
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1373 ; free virtual = 25072
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1372 ; free virtual = 25071
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:18 ; elapsed = 00:01:18 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1361 ; free virtual = 25060
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:18 ; elapsed = 00:01:18 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1360 ; free virtual = 25059
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 1|
|2 |CARRY4 | 65|
|3 |LUT1 | 34|
|4 |LUT2 | 195|
|5 |LUT3 | 231|
|6 |LUT4 | 95|
|7 |LUT5 | 111|
|8 |LUT6 | 277|
|9 |MUXF7 | 4|
|10 |RAM256X1S | 256|
|11 |RAM32M | 2|
|12 |RAM32X1D | 4|
|13 |FDRE | 606|
|14 |FDSE | 5|
|15 |IBUF | 2|
|16 |OBUF | 1|
|17 |OBUFT | 2|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:18 ; elapsed = 00:01:18 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1359 ; free virtual = 25058
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 33 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:13 ; elapsed = 00:01:14 . Memory (MB): peak = 2282.539 ; gain = 504.496 ; free physical = 1375 ; free virtual = 25074
Synthesis Optimization Complete : Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 2282.539 ; gain = 657.281 ; free physical = 1375 ; free virtual = 25074
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2282.539 ; gain = 0.000 ; free physical = 1671 ; free virtual = 25370
INFO: [Netlist 29-17] Analyzing 331 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.535 ; gain = 0.000 ; free physical = 1671 ; free virtual = 25371
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 262 instances were transformed.
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 2b2ebe0a
INFO: [Common 17-83] Releasing license: Synthesis
59 Infos, 88 Warnings, 2 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:35 ; elapsed = 00:01:31 . Memory (MB): peak = 2346.570 ; gain = 1042.352 ; free physical = 1666 ; free virtual = 25365
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2070.240; main = 1770.170; forked = 443.984
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3308.496; main = 2346.539; forked = 1025.988
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2410.566 ; gain = 63.996 ; free physical = 1670 ; free virtual = 25369
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 102a8adb8
Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2516.379 ; gain = 105.812 ; free physical = 1631 ; free virtual = 25330
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 102a8adb8
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2762.316 ; gain = 0.000 ; free physical = 1363 ; free virtual = 25062
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 102a8adb8
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2762.316 ; gain = 0.000 ; free physical = 1363 ; free virtual = 25062
Phase 1 Initialization | Checksum: 102a8adb8
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2762.316 ; gain = 0.000 ; free physical = 1363 ; free virtual = 25062
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 102a8adb8
Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2762.316 ; gain = 0.000 ; free physical = 1362 ; free virtual = 25061
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 102a8adb8
Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2762.316 ; gain = 0.000 ; free physical = 1362 ; free virtual = 25061
Phase 2 Timer Update And Timing Data Collection | Checksum: 102a8adb8
Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2762.316 ; gain = 0.000 ; free physical = 1362 ; free virtual = 25061
Phase 3 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 102a8adb8
Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2762.316 ; gain = 0.000 ; free physical = 1362 ; free virtual = 25061
Retarget | Checksum: 102a8adb8
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 18500552e
Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2762.316 ; gain = 0.000 ; free physical = 1362 ; free virtual = 25061
Constant propagation | Checksum: 18500552e
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 1b25c9e0a
Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2762.316 ; gain = 0.000 ; free physical = 1362 ; free virtual = 25061
Sweep | Checksum: 1b25c9e0a
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 1b25c9e0a
Time (s): cpu = 00:00:00.96 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2794.332 ; gain = 32.016 ; free physical = 1362 ; free virtual = 25061
BUFG optimization | Checksum: 1b25c9e0a
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 1b25c9e0a
Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2794.332 ; gain = 32.016 ; free physical = 1362 ; free virtual = 25061
Shift Register Optimization | Checksum: 1b25c9e0a
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1b25c9e0a
Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.6 . Memory (MB): peak = 2794.332 ; gain = 32.016 ; free physical = 1362 ; free virtual = 25061
Post Processing Netlist | Checksum: 1b25c9e0a
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: ccaac246
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2794.332 ; gain = 32.016 ; free physical = 1361 ; free virtual = 25060
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2794.332 ; gain = 0.000 ; free physical = 1360 ; free virtual = 25059
Phase 9.2 Verifying Netlist Connectivity | Checksum: ccaac246
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.68 . Memory (MB): peak = 2794.332 ; gain = 32.016 ; free physical = 1360 ; free virtual = 25059
Phase 9 Finalization | Checksum: ccaac246
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2794.332 ; gain = 32.016 ; free physical = 1359 ; free virtual = 25058
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: ccaac246
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2794.332 ; gain = 32.016 ; free physical = 1359 ; free virtual = 25058
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2794.332 ; gain = 0.000 ; free physical = 1359 ; free virtual = 25058
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: ccaac246
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2794.332 ; gain = 0.000 ; free physical = 1344 ; free virtual = 25043
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: ccaac246
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2794.332 ; gain = 0.000 ; free physical = 1343 ; free virtual = 25043
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2794.332 ; gain = 0.000 ; free physical = 1343 ; free virtual = 25043
Ending Netlist Obfuscation Task | Checksum: ccaac246
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2794.332 ; gain = 0.000 ; free physical = 1343 ; free virtual = 25042
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 2794.332 ; gain = 447.762 ; free physical = 1343 ; free virtual = 25042
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2826.348 ; gain = 0.000 ; free physical = 1356 ; free virtual = 25055
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a3e59a72
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2826.348 ; gain = 0.000 ; free physical = 1356 ; free virtual = 25055
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2826.348 ; gain = 0.000 ; free physical = 1356 ; free virtual = 25055
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e2a882a2
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2826.348 ; gain = 0.000 ; free physical = 1361 ; free virtual = 25060
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 193434f3f
Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2833.375 ; gain = 7.027 ; free physical = 1359 ; free virtual = 25058
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 193434f3f
Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2833.375 ; gain = 7.027 ; free physical = 1359 ; free virtual = 25058
Phase 1 Placer Initialization | Checksum: 193434f3f
Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2833.375 ; gain = 7.027 ; free physical = 1359 ; free virtual = 25058
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1c4b8562e
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2833.375 ; gain = 7.027 ; free physical = 1341 ; free virtual = 25040
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: f9a4c91e
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2833.375 ; gain = 7.027 ; free physical = 1347 ; free virtual = 25046
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: f9a4c91e
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2833.375 ; gain = 7.027 ; free physical = 1356 ; free virtual = 25055
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1a8577b82
Time (s): cpu = 00:00:25 ; elapsed = 00:00:14 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1358 ; free virtual = 25057
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 115 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 55 nets or LUTs. Breaked 0 LUT, combined 55 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1357 ; free virtual = 25056
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 55 | 55 | 0 | 1 | 00:00:01 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 55 | 55 | 0 | 4 | 00:00:01 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 21a9178ec
Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1357 ; free virtual = 25056
Phase 2.4 Global Placement Core | Checksum: 255427abe
Time (s): cpu = 00:00:49 ; elapsed = 00:00:24 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1357 ; free virtual = 25056
Phase 2 Global Placement | Checksum: 255427abe
Time (s): cpu = 00:00:49 ; elapsed = 00:00:24 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1357 ; free virtual = 25056
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 22f297716
Time (s): cpu = 00:00:51 ; elapsed = 00:00:25 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1356 ; free virtual = 25055
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 172fa10db
Time (s): cpu = 00:00:54 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1357 ; free virtual = 25056
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 152194355
Time (s): cpu = 00:00:55 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1357 ; free virtual = 25056
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: e04d9a2e
Time (s): cpu = 00:00:55 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1357 ; free virtual = 25056
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: e68b9756
Time (s): cpu = 00:00:56 ; elapsed = 00:00:29 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1357 ; free virtual = 25056
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1521467e4
Time (s): cpu = 00:00:56 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1352 ; free virtual = 25051
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 21eda2cd8
Time (s): cpu = 00:00:56 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1348 ; free virtual = 25047
Phase 3 Detail Placement | Checksum: 21eda2cd8
Time (s): cpu = 00:00:56 ; elapsed = 00:00:30 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1354 ; free virtual = 25054
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1ac67c638
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.510 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 13ac45181
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.89 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1355 ; free virtual = 25054
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 13ac45181
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.99 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1348 ; free virtual = 25047
Phase 4.1.1.1 BUFG Insertion | Checksum: 1ac67c638
Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1355 ; free virtual = 25054
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=1.510. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1a6d58636
Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1358 ; free virtual = 25057
Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1358 ; free virtual = 25057
Phase 4.1 Post Commit Optimization | Checksum: 1a6d58636
Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1358 ; free virtual = 25057
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1a6d58636
Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1358 ; free virtual = 25057
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 1x1|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1a6d58636
Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1358 ; free virtual = 25057
Phase 4.3 Placer Reporting | Checksum: 1a6d58636
Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1358 ; free virtual = 25057
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1358 ; free virtual = 25057
Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1358 ; free virtual = 25057
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17687ed24
Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1358 ; free virtual = 25057
Ending Placer Task | Checksum: e1b1909b
Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2841.379 ; gain = 15.031 ; free physical = 1358 ; free virtual = 25057
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:05 ; elapsed = 00:00:35 . Memory (MB): peak = 2841.379 ; gain = 47.047 ; free physical = 1358 ; free virtual = 25057
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1358 ; free virtual = 25058
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1358 ; free virtual = 25057
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 7fe5adb8 ConstDB: 0 ShapeSum: 61cbe2e3 RouteDB: 0
Post Restoration Checksum: NetGraph: 9a9e0668 | NumContArr: aec2faf3 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2ceb2f695
Time (s): cpu = 00:01:19 ; elapsed = 00:01:10 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1667 ; free virtual = 25401
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2ceb2f695
Time (s): cpu = 00:01:20 ; elapsed = 00:01:10 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1667 ; free virtual = 25401
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2ceb2f695
Time (s): cpu = 00:01:20 ; elapsed = 00:01:10 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1666 ; free virtual = 25401
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 21b9f41d3
Time (s): cpu = 00:01:27 ; elapsed = 00:01:14 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1537 ; free virtual = 25271
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.646 | TNS=0.000 | WHS=-0.185 | THS=-17.078|
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
Global Horizontal Routing Utilization = 0 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 1455
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 1455
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 2 Router Initialization | Checksum: 2221525d7
Time (s): cpu = 00:01:30 ; elapsed = 00:01:15 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1535 ; free virtual = 25270
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2221525d7
Time (s): cpu = 00:01:30 ; elapsed = 00:01:15 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1535 ; free virtual = 25270
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 245b68cbe
Time (s): cpu = 00:01:33 ; elapsed = 00:01:17 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1530 ; free virtual = 25265
Phase 3 Initial Routing | Checksum: 245b68cbe
Time (s): cpu = 00:01:33 ; elapsed = 00:01:17 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1529 ; free virtual = 25264
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 175
Number of Nodes with overlaps = 22
Number of Nodes with overlaps = 7
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.764 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1e24985fb
Time (s): cpu = 00:01:39 ; elapsed = 00:01:21 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1542 ; free virtual = 25277
Phase 4 Rip-up And Reroute | Checksum: 1e24985fb
Time (s): cpu = 00:01:39 ; elapsed = 00:01:21 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1542 ; free virtual = 25277
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 1eb3487e1
Time (s): cpu = 00:01:40 ; elapsed = 00:01:21 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1510 ; free virtual = 25245
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.844 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 5.1 Delay CleanUp | Checksum: 1eb3487e1
Time (s): cpu = 00:01:40 ; elapsed = 00:01:21 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1510 ; free virtual = 25245
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1eb3487e1
Time (s): cpu = 00:01:40 ; elapsed = 00:01:21 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1510 ; free virtual = 25245
Phase 5 Delay and Skew Optimization | Checksum: 1eb3487e1
Time (s): cpu = 00:01:40 ; elapsed = 00:01:21 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1510 ; free virtual = 25245
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1afdd84d0
Time (s): cpu = 00:01:42 ; elapsed = 00:01:22 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1498 ; free virtual = 25233
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.844 | TNS=0.000 | WHS=0.057 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 2912efba6
Time (s): cpu = 00:01:42 ; elapsed = 00:01:22 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1498 ; free virtual = 25233
Phase 6 Post Hold Fix | Checksum: 2912efba6
Time (s): cpu = 00:01:42 ; elapsed = 00:01:22 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1498 ; free virtual = 25233
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.660008 %
Global Horizontal Routing Utilization = 0.650611 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 2912efba6
Time (s): cpu = 00:01:42 ; elapsed = 00:01:23 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1496 ; free virtual = 25231
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 2912efba6
Time (s): cpu = 00:01:42 ; elapsed = 00:01:23 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1496 ; free virtual = 25231
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 30341c16d
Time (s): cpu = 00:01:43 ; elapsed = 00:01:23 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1492 ; free virtual = 25227
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.844 | TNS=0.000 | WHS=0.057 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 30341c16d
Time (s): cpu = 00:01:44 ; elapsed = 00:01:24 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1492 ; free virtual = 25228
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 17d239498
Time (s): cpu = 00:01:45 ; elapsed = 00:01:24 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1492 ; free virtual = 25228
Ending Routing Task | Checksum: 17d239498
Time (s): cpu = 00:01:45 ; elapsed = 00:01:24 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1492 ; free virtual = 25228
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
13 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:47 ; elapsed = 00:01:25 . Memory (MB): peak = 2841.379 ; gain = 0.000 ; free physical = 1492 ; free virtual = 25228
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (0)
------------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (1)
-------------------------------
There is 1 port with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
1.849 0.000 0 11929 0.060 0.000 0 11929 3.750 0.000 0 1660
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 1.849 0.000 0 11929 0.060 0.000 0 11929 3.750 0.000 0 1660
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "digilent_nexys4_ddr.bit"
Command: write_bitstream -force digilent_nexys4_ddr.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_nexys4_ddr.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 3141.531 ; gain = 251.211 ; free physical = 1148 ; free virtual = 24902
INFO: [Common 17-206] Exiting Vivado at Tue Nov 12 02:44:59 2024...
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia
[Pipeline] {
[Pipeline] echo
FPGA digilent_nexys4_ddr bloqueada para flash.
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b digilent_nexys4_ddr -l
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/build_digilent_nexys4_ddr.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 digilent_nexys4_ddr.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Parse file DONE
Erase SRAM Load SRAM
Load SRAM: [====== ] 10.28%
Load SRAM: [=========== ] 20.56%
Load SRAM: [================ ] 30.83%
Load SRAM: [==================== ] 39.40%
Load SRAM: [========================= ] 49.68%
Load SRAM: [============================== ] 58.24%
Load SRAM: [================================= ] 65.09%
Load SRAM: [====================================== ] 75.37%
Load SRAM: [========================================== ] 83.93%
Load SRAM: [=============================================== ] 92.50%
Load SRAM: [===================================================] 100.00%
Done
DONE
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
[Pipeline] echo
Testando FPGA digilent_nexys4_ddr.
[Pipeline] dir
Running in /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia
[Pipeline] {
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_nexys4_ddr]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: UNSTABLE
![[Jenkins]](/jenkins/static/ee6d6826/images/svgs/logo.svg){kind=logo}
