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Start of Pipeline - (6.1 sec in block)
node - (5.2 sec in block)
node block - (4.6 sec in block)
stage - (2.4 sec in block)Git Clone
stage block (Git Clone) - (1.9 sec in block)
sh - (0.46 sec in self)rm -rf AUK-V-Aethia
sh - (1.2 sec in self)git clone https://github.com/veeYceeY/AUK-V-Aethia.git
stage - (1.7 sec in block)IVerilog
stage block (IVerilog) - (1.4 sec in block)
dir - (0.96 sec in block)AUK-V-Aethia/
dir block - (0.67 sec in block)
sh - (0.47 sec in self) /usr/bin/iverilog -o test.o -s aukv_eggs_soc_tb tb/soc/aukv_eggs_soc_tb.v rtl/core/aukv_alu.v rtl/core/aukv_csr_regfile.v rtl/core/aukv_decode.v rtl/core/aukv_execute.v rtl/core/aukv_fetch.v rtl/core/aukv_gpr_regfilie.v rtl/core/aukv_mem.v rtl/core/aukv.v rtl/memory/cache.v rtl/memory/oc_ram.v rtl/memory/oc_rom.v rtl/soc/aukv_eggs_soc.v rtl/system/reset_sync.v rtl/wishbone/wb_arbiter.v rtl/wishbone/wb_interconnect.v rtl/wishbone/wb_master.v rtl/wishbone/wb_switch.v rtl/peripherals/fifo/fifo.v rtl/peripherals/gpio/gpio.v rtl/peripherals/spi/spi.v rtl/peripherals/uart/baud.v rtl/peripherals/uart/uart_rx.v rtl/peripherals/uart/uart_tx.v rtl/peripherals/uart/uart.v -I rtl/wishbone/