Console Output

+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b digilent_nexys4_ddr -l
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/build_digilent_nexys4_ddr.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 digilent_nexys4_ddr.bit
empty
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Parse file DONE
Erase SRAM Load SRAM 
Load SRAM: [======                                            ] 10.28%
Load SRAM: [=========                                         ] 17.13%
Load SRAM: [=============                                     ] 25.69%
Load SRAM: [==================                                ] 35.97%
Load SRAM: [=======================                           ] 44.54%
Load SRAM: [===========================                       ] 53.10%
Load SRAM: [================================                  ] 63.38%
Load SRAM: [====================================              ] 71.94%
Load SRAM: [=========================================         ] 80.51%
Load SRAM: [==============================================    ] 90.79%
Load SRAM: [==================================================] 99.35%
Load SRAM: [===================================================] 100.00%
Done
DONE