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Start of Pipeline - (5 min 38 sec in block)
node - (5 min 37 sec in block)
node block - (5 min 36 sec in block)
stage - (2.5 sec in block)Git Clone
stage block (Git Clone) - (2 sec in block)
sh - (0.51 sec in self)rm -rf AUK-V-Aethia
sh - (1.2 sec in self)git clone --recursive https://github.com/veeYceeY/AUK-V-Aethia AUK-V-Aethia
stage - (1.9 sec in block)Simulation
stage block (Simulation) - (1.3 sec in block)
dir - (0.92 sec in block)AUK-V-Aethia
dir block - (0.65 sec in block)
sh - (0.42 sec in self)iverilog -o simulation.out -g2005 -s aukv rtl/core/aukv.v rtl/core/aukv_alu.v rtl/core/aukv_csr_regfile.v rtl/core/aukv_decode.v rtl/core/aukv_execute.v rtl/core/aukv_fetch.v rtl/core/aukv_gpr_regfilie.v rtl/core/aukv_mem.v
stage - (5 min 30 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 min 29 sec in block)
parallel - (5 min 29 sec in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (4 min 5 sec in block)colorlight_i9
stage block (colorlight_i9) - (4 min 4 sec in block)
lock - (4 min 4 sec in block)colorlight_i9
lock block - (4 min 2 sec in block)
stage - (3 min 38 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (3 min 38 sec in block)
dir - (3 min 37 sec in block)AUK-V-Aethia
dir block - (3 min 37 sec in block)
echo - (0.16 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (3 min 36 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)AUK-V-Aethia
dir block - (15 sec in block)
echo - (0.19 sec in self)FPGA colorlight_i9 bloqueada para flash.
sh - (15 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b colorlight_i9 -l
stage - (6.3 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (6 sec in block)
echo - (0.22 sec in self)Testando FPGA colorlight_i9.
dir - (5.5 sec in block)AUK-V-Aethia
dir block - (5.2 sec in block)
sh - (5 sec in self)PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py
parallel block (Branch: digilent_nexys4_ddr) - (5 min 28 sec in block)
stage - (5 min 27 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (5 min 27 sec in block)
lock - (5 min 26 sec in block)digilent_nexys4_ddr
lock block - (5 min 25 sec in block)
stage - (5 min 8 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (5 min 8 sec in block)
dir - (5 min 7 sec in block)AUK-V-Aethia
dir block - (5 min 7 sec in block)
echo - (0.17 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (5 min 6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b digilent_nexys4_ddr
stage - (14 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (13 sec in block)
dir - (13 sec in block)AUK-V-Aethia
dir block - (12 sec in block)
echo - (0.16 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (12 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b digilent_nexys4_ddr -l
stage - (1.3 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (1.1 sec in block)
echo - (0.22 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.5 sec in block)AUK-V-Aethia
dir block - (0.24 sec in block)
stage - (1 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.8 sec in block)
junit - (0.51 sec in self)**/test-reports/*.xml