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Start of Pipeline - (9 min 3 sec in block)
node - (9 min 2 sec in block)
node block - (14 sec in block)
stage - (2.9 sec in block)Git Clone
stage block (Git Clone) - (2.3 sec in block)
sh - (0.58 sec in self)rm -rf *.xml
sh - (0.47 sec in self)rm -rf AUK-V-Aethia
sh - (0.91 sec in self)git clone --recursive --depth=1 https://github.com/veeYceeY/AUK-V-Aethia AUK-V-Aethia
stage - (2 sec in block)Simulation
stage block (Simulation) - (1.4 sec in block)
dir - (0.97 sec in block)AUK-V-Aethia
dir block - (0.66 sec in block)
sh - (0.45 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s aukv -I rtl/wishbone/ rtl/core/aukv.v rtl/core/aukv_alu.v rtl/core/aukv_csr_regfile.v rtl/core/aukv_decode.v rtl/core/aukv_execute.v rtl/core/aukv_fetch.v rtl/core/aukv_gpr_regfilie.v rtl/core/aukv_mem.v
stage - (0.99 sec in block)Utilities
stage block (Utilities) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (6.9 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (6.3 sec in block)
getContext - (0.3 sec in self)
parallel - (5.6 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (5 sec in block)
stage - (4.5 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (4 sec in block)
getContext - (0.39 sec in self)
stage - (1.3 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.53 sec in block)
getContext - (0.15 sec in self)
stage - (1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.17 sec in self)
stage - (0.7 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.4 sec in block)
getContext - (0.17 sec in self)
stage - (0.75 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.5 sec in block)
junit - (0.25 sec in self)**/*.xml