Skip to content
[Jenkins]Jenkins
log in

Workspace

/ tinyriscv /
.git
.Xil
fpga
pic
rtl
sim
tb
tests
tools
.gitignoreMay 3, 2025, 2:41:04 AM30 B
build_digilent_arty_a7_100t.tclMay 3, 2025, 2:41:10 AM3.21 KiB
clockInfo.txtMay 3, 2025, 2:42:31 AM375 B
digilent_arty_a7_100t.bitMay 3, 2025, 2:43:38 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptMay 3, 2025, 2:42:40 AM19.71 KiB
digilent_arty_a7_control_sets.rptMay 3, 2025, 2:42:39 AM18.13 KiB
digilent_arty_a7_drc.rptMay 3, 2025, 2:43:17 AM9.28 KiB
digilent_arty_a7_io.rptMay 3, 2025, 2:42:39 AM96.82 KiB
digilent_arty_a7_power.rptMay 3, 2025, 2:43:19 AM8.70 KiB
digilent_arty_a7_route_status.rptMay 3, 2025, 2:43:16 AM651 B
digilent_arty_a7_timing.rptMay 3, 2025, 2:43:18 AM22.59 KiB
digilent_arty_a7_utilization_hierarchical_place.rptMay 3, 2025, 2:42:39 AM6.80 KiB
digilent_arty_a7_utilization_place.rptMay 3, 2025, 2:42:39 AM10.74 KiB
LICENSEMay 3, 2025, 2:41:04 AM11.09 KiB
processor_ci_defines.vhMay 3, 2025, 2:41:10 AM300 B
README.mdMay 3, 2025, 2:41:04 AM9.81 KiB
simulation.outMay 3, 2025, 2:41:05 AM200.45 KiB