Skip to content
[Jenkins]Jenkins
log in

Workspace

/ tinyriscv /
.git
.Xil
fpga
pic
rtl
sim
tb
tests
tools
.gitignoreMay 7, 2025, 2:49:19 AM30 B
build_digilent_arty_a7_100t.tclMay 7, 2025, 2:49:27 AM3.21 KiB
clockInfo.txtMay 7, 2025, 2:52:38 AM375 B
digilent_arty_a7_100t.bitMay 7, 2025, 2:55:20 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptMay 7, 2025, 2:53:05 AM19.71 KiB
digilent_arty_a7_control_sets.rptMay 7, 2025, 2:53:03 AM18.13 KiB
digilent_arty_a7_drc.rptMay 7, 2025, 2:54:45 AM9.28 KiB
digilent_arty_a7_io.rptMay 7, 2025, 2:53:02 AM96.82 KiB
digilent_arty_a7_power.rptMay 7, 2025, 2:54:49 AM8.70 KiB
digilent_arty_a7_route_status.rptMay 7, 2025, 2:54:41 AM651 B
digilent_arty_a7_timing.rptMay 7, 2025, 2:54:46 AM22.59 KiB
digilent_arty_a7_utilization_hierarchical_place.rptMay 7, 2025, 2:53:02 AM6.80 KiB
digilent_arty_a7_utilization_place.rptMay 7, 2025, 2:53:02 AM10.74 KiB
LICENSEMay 7, 2025, 2:49:19 AM11.09 KiB
processor_ci_defines.vhMay 7, 2025, 2:49:27 AM300 B
README.mdMay 7, 2025, 2:49:19 AM9.81 KiB
simulation.outMay 7, 2025, 2:49:21 AM200.45 KiB