| .git |
| .Xil |
| build |
| FPGA |
| rtl |
| sim |
| testbench |
| .gitattributes | Apr 29, 2025, 1:18:54 AM | 66 B | |
| build_digilent_arty_a7_100t.tcl | Apr 29, 2025, 1:19:01 AM | 3.30 KiB | |
| clockInfo.txt | Apr 29, 2025, 1:19:58 AM | 375 B | |
| diagram.png | Apr 29, 2025, 1:18:54 AM | 57.29 KiB | |
| digilent_arty_a7_100t.bit | Apr 29, 2025, 1:20:52 AM | 3.65 MiB | |
| digilent_arty_a7_clock_utilization.rpt | Apr 29, 2025, 1:20:02 AM | 16.56 KiB | |
| digilent_arty_a7_control_sets.rpt | Apr 29, 2025, 1:20:02 AM | 12.48 KiB | |
| digilent_arty_a7_drc.rpt | Apr 29, 2025, 1:20:33 AM | 2.36 KiB | |
| digilent_arty_a7_io.rpt | Apr 29, 2025, 1:20:02 AM | 96.82 KiB | |
| digilent_arty_a7_power.rpt | Apr 29, 2025, 1:20:34 AM | 8.55 KiB | |
| digilent_arty_a7_route_status.rpt | Apr 29, 2025, 1:20:32 AM | 651 B | |
| digilent_arty_a7_timing.rpt | Apr 29, 2025, 1:20:34 AM | 18.47 KiB | |
| digilent_arty_a7_utilization_hierarchical_place.rpt | Apr 29, 2025, 1:20:01 AM | 3.09 KiB | |
| digilent_arty_a7_utilization_place.rpt | Apr 29, 2025, 1:20:01 AM | 10.57 KiB | |
| LICENSE | Apr 29, 2025, 1:18:54 AM | 11.06 KiB | |
| processor_ci_defines.vh | Apr 29, 2025, 1:19:01 AM | 300 B | |
| README.md | Apr 29, 2025, 1:18:54 AM | 3.88 KiB | |
| simulation.out | Apr 29, 2025, 1:18:56 AM | 716.36 KiB | |
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