Skip to content
[Jenkins]Jenkins
log in

Workspace

/ rv3n /
.git
.Xil
build
FPGA
rtl
sim
testbench
.gitattributesMay 12, 2025, 1:26:11 AM66 B
build_digilent_arty_a7_100t.tclMay 12, 2025, 1:26:17 AM3.30 KiB
clockInfo.txtMay 12, 2025, 1:28:27 AM375 B
diagram.pngMay 12, 2025, 1:26:11 AM57.29 KiB
digilent_arty_a7_100t.bitMay 12, 2025, 1:30:33 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptMay 12, 2025, 1:28:41 AM16.56 KiB
digilent_arty_a7_control_sets.rptMay 12, 2025, 1:28:40 AM12.48 KiB
digilent_arty_a7_drc.rptMay 12, 2025, 1:30:04 AM2.36 KiB
digilent_arty_a7_io.rptMay 12, 2025, 1:28:40 AM96.82 KiB
digilent_arty_a7_power.rptMay 12, 2025, 1:30:06 AM8.55 KiB
digilent_arty_a7_route_status.rptMay 12, 2025, 1:30:02 AM651 B
digilent_arty_a7_timing.rptMay 12, 2025, 1:30:05 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptMay 12, 2025, 1:28:39 AM3.09 KiB
digilent_arty_a7_utilization_place.rptMay 12, 2025, 1:28:40 AM10.57 KiB
LICENSEMay 12, 2025, 1:26:11 AM11.06 KiB
processor_ci_defines.vhMay 12, 2025, 1:26:17 AM300 B
README.mdMay 12, 2025, 1:26:11 AM3.88 KiB
simulation.outMay 12, 2025, 1:26:12 AM716.36 KiB