Skip to content

Workspace

/ pulpino /
.git
.Xil
ci
doc
fpga
ips
rtl
sw
tb
vsim
.gitignoreMay 1, 2025, 4:25:28 AM34 B
.gitlab-ci.ymlMay 1, 2025, 4:25:28 AM2.53 KiB
build_digilent_arty_a7_100t.tclMay 1, 2025, 4:25:34 AM5.08 KiB
clockInfo.txtMay 1, 2025, 4:26:31 AM375 B
create-archive.pyMay 1, 2025, 4:25:28 AM1.54 KiB
digilent_arty_a7_100t.bitMay 1, 2025, 4:27:25 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptMay 1, 2025, 4:26:35 AM16.56 KiB
digilent_arty_a7_control_sets.rptMay 1, 2025, 4:26:35 AM12.48 KiB
digilent_arty_a7_drc.rptMay 1, 2025, 4:27:07 AM2.36 KiB
digilent_arty_a7_io.rptMay 1, 2025, 4:26:35 AM96.82 KiB
digilent_arty_a7_power.rptMay 1, 2025, 4:27:07 AM8.55 KiB
digilent_arty_a7_route_status.rptMay 1, 2025, 4:27:06 AM651 B
digilent_arty_a7_timing.rptMay 1, 2025, 4:27:07 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptMay 1, 2025, 4:26:35 AM3.09 KiB
digilent_arty_a7_utilization_place.rptMay 1, 2025, 4:26:35 AM10.57 KiB
generate-scripts.pyMay 1, 2025, 4:25:28 AM2.37 KiB
ips_list.ymlMay 1, 2025, 4:25:28 AM1.24 KiB
LICENSEMay 1, 2025, 4:25:28 AM10.15 KiB
processor_ci_defines.vhMay 1, 2025, 4:25:34 AM300 B
README.mdMay 1, 2025, 4:25:28 AM7.75 KiB
update-ips.pyMay 1, 2025, 4:25:28 AM2.87 KiB