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/ neorv32-verilog / sim /
iverilog_sim.shMay 13, 2025, 5:03:40 AM295 B
MakefileMay 13, 2025, 5:03:40 AM649 B
testbench.vMay 13, 2025, 5:03:40 AM2.53 KiB
uart_sim_receiver.vMay 13, 2025, 5:03:40 AM2.70 KiB