| .git |
| .Xil |
| core |
| documentation |
| lib |
| peripherals |
| processor |
| test |
| build_digilent_arty_a7_100t.tcl | May 2, 2025, 4:15:09 AM | 3.23 KiB | |
| clockInfo.txt | May 2, 2025, 4:16:06 AM | 375 B | |
| digilent_arty_a7_100t.bit | May 2, 2025, 4:17:02 AM | 3.65 MiB | |
| digilent_arty_a7_clock_utilization.rpt | May 2, 2025, 4:16:11 AM | 16.56 KiB | |
| digilent_arty_a7_control_sets.rpt | May 2, 2025, 4:16:10 AM | 12.48 KiB | |
| digilent_arty_a7_drc.rpt | May 2, 2025, 4:16:43 AM | 2.36 KiB | |
| digilent_arty_a7_io.rpt | May 2, 2025, 4:16:10 AM | 96.82 KiB | |
| digilent_arty_a7_power.rpt | May 2, 2025, 4:16:43 AM | 8.55 KiB | |
| digilent_arty_a7_route_status.rpt | May 2, 2025, 4:16:42 AM | 651 B | |
| digilent_arty_a7_timing.rpt | May 2, 2025, 4:16:43 AM | 18.47 KiB | |
| digilent_arty_a7_utilization_hierarchical_place.rpt | May 2, 2025, 4:16:10 AM | 3.09 KiB | |
| digilent_arty_a7_utilization_place.rpt | May 2, 2025, 4:16:10 AM | 10.57 KiB | |
| LICENSE | May 2, 2025, 4:15:03 AM | 1.07 KiB | |
| processor_ci_defines.vh | May 2, 2025, 4:15:09 AM | 300 B | |
| README.md | May 2, 2025, 4:15:03 AM | 812 B | |
| simplified_pipeline.png | May 2, 2025, 4:15:03 AM | 177.18 KiB | |
| simulation.out | May 2, 2025, 4:15:04 AM | 226.29 KiB | |
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