| .git |
| .Xil |
| fpga |
| pic |
| rtl |
| sim |
| tb |
| tests |
| tools |
| .gitignore | Apr 28, 2025, 2:41:04 AM | 30 B | |
| build_digilent_arty_a7_100t.tcl | Apr 28, 2025, 2:41:11 AM | 3.21 KiB | |
| clockInfo.txt | Apr 28, 2025, 2:42:30 AM | 375 B | |
| digilent_arty_a7_100t.bit | Apr 28, 2025, 2:43:38 AM | 3.65 MiB | |
| digilent_arty_a7_clock_utilization.rpt | Apr 28, 2025, 2:42:40 AM | 19.71 KiB | |
| digilent_arty_a7_control_sets.rpt | Apr 28, 2025, 2:42:39 AM | 18.13 KiB | |
| digilent_arty_a7_drc.rpt | Apr 28, 2025, 2:43:17 AM | 9.28 KiB | |
| digilent_arty_a7_io.rpt | Apr 28, 2025, 2:42:39 AM | 96.82 KiB | |
| digilent_arty_a7_power.rpt | Apr 28, 2025, 2:43:19 AM | 8.70 KiB | |
| digilent_arty_a7_route_status.rpt | Apr 28, 2025, 2:43:16 AM | 651 B | |
| digilent_arty_a7_timing.rpt | Apr 28, 2025, 2:43:17 AM | 22.59 KiB | |
| digilent_arty_a7_utilization_hierarchical_place.rpt | Apr 28, 2025, 2:42:39 AM | 6.80 KiB | |
| digilent_arty_a7_utilization_place.rpt | Apr 28, 2025, 2:42:39 AM | 10.74 KiB | |
| LICENSE | Apr 28, 2025, 2:41:04 AM | 11.09 KiB | |
| processor_ci_defines.vh | Apr 28, 2025, 2:41:11 AM | 300 B | |
| README.md | Apr 28, 2025, 2:41:04 AM | 9.81 KiB | |
| simulation.out | Apr 28, 2025, 2:41:06 AM | 200.45 KiB | |
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