Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/tinyriscv [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf tinyriscv [Pipeline] sh + git clone --recursive --depth=1 https://github.com/liangkangnan/tinyriscv tinyriscv Cloning into 'tinyriscv'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s tinyriscv -I rtl/core/ rtl/core/clint.v rtl/core/csr_reg.v rtl/core/ctrl.v rtl/core/div.v rtl/core/ex.v rtl/core/id.v rtl/core/id_ex.v rtl/core/if_id.v rtl/core/pc_reg.v rtl/core/regs.v rtl/core/rib.v rtl/core/tinyriscv.v rtl/utils/gen_dff.v [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/tinyriscv/tinyriscv -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels WARNING: Error reading file /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v with encoding utf-8: 'utf-8' codec can't decode byte 0xba in position 1074: invalid start byte WARNING: Error reading file /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v with encoding utf-8: 'utf-8' codec can't decode byte 0xba in position 1074: invalid start byte Trying to read file: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v Trying to read file: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v Results saved to /jenkins/processor_ci_utils/labels/tinyriscv.json [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] Resource [colorlight_i9] did not exist. Created. Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] Resource [digilent_arty_a7_100t] did not exist. Created. Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] echo Starting synthesis for FPGA colorlight_i9. [Pipeline] sh [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p tinyriscv -b colorlight_i9 [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p tinyriscv -b digilent_arty_a7_100t Final configuration file generated at /var/jenkins_home/workspace/tinyriscv/tinyriscv/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/synlig -c /var/jenkins_home/workspace/tinyriscv/tinyriscv/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096 -- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' -- 1. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v' to AST representation. Generating RTLIL representation for module `\clint'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v' to AST representation. Generating RTLIL representation for module `\csr_reg'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v' to AST representation. Generating RTLIL representation for module `\ctrl'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v' to AST representation. Generating RTLIL representation for module `\div'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v' to AST representation. Generating RTLIL representation for module `\ex'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v' to AST representation. Generating RTLIL representation for module `\id'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v' to AST representation. Generating RTLIL representation for module `\id_ex'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v' to AST representation. Generating RTLIL representation for module `\if_id'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v' to AST representation. Generating RTLIL representation for module `\pc_reg'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v' to AST representation. Generating RTLIL representation for module `\regs'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/rib.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/rib.v' to AST representation. Generating RTLIL representation for module `\rib'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v' to AST representation. Generating RTLIL representation for module `\tinyriscv'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v' to AST representation. Generating RTLIL representation for module `\gen_pipe_dff'. Generating RTLIL representation for module `\gen_rst_0_dff'. Generating RTLIL representation for module `\gen_rst_1_dff'. Generating RTLIL representation for module `\gen_rst_def_dff'. Generating RTLIL representation for module `\gen_en_dff'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: /eda/processor_ci/rtl/tinyriscv.v Parsing Verilog input from `/eda/processor_ci/rtl/tinyriscv.v' to AST representation. Generating RTLIL representation for module `\processorci_top'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation. Generating RTLIL representation for module `\ClkDivider'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 22. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation. Generating RTLIL representation for module `\Interpreter'. Successfully finished Verilog frontend. 23. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation. Generating RTLIL representation for module `\Controller'. Successfully finished Verilog frontend. 24. Executing SYNTH_ECP5 pass. 24.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_sim.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 24.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_bb.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 24.3. Executing HIERARCHY pass (managing design hierarchy). 24.3.1. Analyzing design hierarchy.. Top module: \processorci_top Used module: \ResetBootSystem Used module: \tinyriscv Used module: \clint Used module: \div Used module: \ex Used module: \id_ex Used module: \gen_pipe_dff Used module: \id Used module: \if_id Used module: \csr_reg Used module: \regs Used module: \ctrl Used module: \pc_reg Used module: \Controller Used module: \Memory Used module: \UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: \Interpreter Used module: \ClkDivider Parameter 1 (\DW) = 32 24.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\gen_pipe_dff'. Parameter 1 (\DW) = 32 Generating RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 1 24.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\gen_pipe_dff'. Parameter 1 (\DW) = 1 Generating RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 5 24.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\gen_pipe_dff'. Parameter 1 (\DW) = 5 Generating RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101'. Parameter 1 (\DW) = 1 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 8 24.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\gen_pipe_dff'. Parameter 1 (\DW) = 8 Generating RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter \CYCLES = 20 24.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 24.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 24.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 24.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 24.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 24.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 24.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 24.3.15. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \tinyriscv Used module: \clint Used module: \div Used module: \ex Used module: \id_ex Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101 Used module: \id Used module: \if_id Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000 Used module: \csr_reg Used module: \regs Used module: \ctrl Used module: \pc_reg Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: \Memory Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 24.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 24.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 24.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'. 24.3.19. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \tinyriscv Used module: \clint Used module: \div Used module: \ex Used module: \id_ex Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101 Used module: \id Used module: \if_id Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000 Used module: \csr_reg Used module: \regs Used module: \ctrl Used module: \pc_reg Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.20. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.21. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 24.3.22. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \tinyriscv Used module: \clint Used module: \div Used module: \ex Used module: \id_ex Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101 Used module: \id Used module: \if_id Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000 Used module: \csr_reg Used module: \regs Used module: \ctrl Used module: \pc_reg Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider 24.3.23. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \tinyriscv Used module: \clint Used module: \div Used module: \ex Used module: \id_ex Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101 Used module: \id Used module: \if_id Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000 Used module: \csr_reg Used module: \regs Used module: \ctrl Used module: \pc_reg Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'. Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'. Removing unused module `\Controller'. Removing unused module `\Interpreter'. Removing unused module `\Memory'. Removing unused module `\ClkDivider'. Removing unused module `\ResetBootSystem'. Removing unused module `\FIFO'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\UART'. Removing unused module `\gen_en_dff'. Removing unused module `\gen_rst_def_dff'. Removing unused module `\gen_rst_1_dff'. Removing unused module `\gen_rst_0_dff'. Removing unused module `\gen_pipe_dff'. Removing unused module `\rib'. Removed 20 unused modules. Mapping positional arguments of cell if_id.int_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000). Mapping positional arguments of cell if_id.inst_addr_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell if_id.inst_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.op2_jump_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.op1_jump_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.op2_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.op1_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.csr_rdata_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.csr_waddr_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.csr_we_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001). Mapping positional arguments of cell id_ex.reg2_rdata_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.reg1_rdata_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.reg_waddr_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101). Mapping positional arguments of cell id_ex.reg_we_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001). Mapping positional arguments of cell id_ex.inst_addr_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.inst_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). 24.4. Executing PROC pass (convert processes to netlists). 24.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$681'. Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$875'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$875'. Cleaned up 2 empty switches. 24.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$788 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$740 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$682 in module TRELLIS_DPR16X4. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$1055 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$1047 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1248 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1246 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1238 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1235 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1229 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1224 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1219 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1210 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1197 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1195 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1187 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1173 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1167 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1162 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1149 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1140 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1104 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1096 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1096 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1091 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1086 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$1081 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$864 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$853 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$803 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$799 in module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$796 in module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$793 in module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$790 in module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$262 in module regs. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$256 in module regs. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$250 in module regs. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221 in module regs. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$212 in module pc_reg. Removed 3 dead cases from process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205 in module id. Marked 10 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205 in module id. Removed 2 dead cases from process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142 in module ex. Marked 21 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142 in module ex. Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136 in module ex. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$126 in module ex. Marked 15 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64 in module div. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46 in module ctrl. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$42 in module csr_reg. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$38 in module csr_reg. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34 in module csr_reg. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$31 in module csr_reg. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$27 in module clint. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25 in module clint. Marked 8 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15 in module clint. Marked 5 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$5 in module clint. Removed a total of 6 dead cases. 24.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 15 redundant assignments. Promoted 140 assignments to connections. 24.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$789'. Set init value: \Q = 1'0 Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1080'. Set init value: \read_ptr = 6'000000 Set init value: \write_ptr = 6'000000 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1250'. Set init value: \i = 0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1203'. Set init value: \i = 0 Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1155'. Set init value: \clk_o_auto = 1'0 Set init value: \clk_counter = 0 Set init value: \pulse_counter = 0 Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1133'. Set init value: \state = 8'00000000 Set init value: \counter = 8'00000000 Set init value: \read_buffer = 0 Set init value: \timeout = 0 Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000 Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1103'. Set init value: \read_response = 1'0 Set init value: \write_response = 1'0 Set init value: \read_data = 0 Set init value: \uart_tx_en = 1'0 Set init value: \tx_fifo_read = 1'0 Set init value: \tx_fifo_write = 1'0 Set init value: \rx_fifo_read = 1'0 Set init value: \rx_fifo_write = 1'0 Set init value: \uart_tx_data = 8'00000000 Set init value: \tx_fifo_write_data = 8'00000000 Set init value: \rx_fifo_write_data = 8'00000000 Set init value: \counter_write = 3'000 Set init value: \counter_read = 3'000 Set init value: \state_read = 4'0000 Set init value: \state_write = 4'0000 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$810'. Set init value: \state = 2'01 Set init value: \reset_o = 1'0 Set init value: \counter = 6'000000 24.4.5. Executing PROC_ARST pass (detect async resets in processes). 24.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~193 debug messages> 24.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$789'. Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$788'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$740'. 1/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$739_EN[3:0]$746 2/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$739_DATA[3:0]$745 3/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$739_ADDR[3:0]$744 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$682'. 1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$680_EN[3:0]$688 2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$680_DATA[3:0]$687 3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$680_ADDR[3:0]$686 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$681'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1080'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. 1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1067 2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_DATA[7:0]$1066 3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR[5:0]$1065 4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1061 5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_DATA[7:0]$1060 6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR[5:0]$1059 7/7: $0\write_ptr[5:0] Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1047'. 1/2: $0\read_ptr[5:0] 2/2: $0\read_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1250'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1248'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1246'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1238'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1235'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1229'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1224'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1219'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1210'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1203'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1197'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1195'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1187'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1173'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1167'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1162'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1155'. Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1149'. 1/1: $0\pulse_counter[31:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1140'. 1/2: $0\clk_counter[31:0] 2/2: $0\clk_o_auto[0:0] Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1133'. Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. 1/28: $0\state[7:0] 2/28: $0\reset_bus[0:0] 3/28: $0\memory_write[0:0] 4/28: $0\memory_read[0:0] 5/28: $0\write_pulse[0:0] 6/28: $0\core_reset[0:0] 7/28: $0\communication_write[0:0] 8/28: $0\communication_read[0:0] 9/28: $0\temp_buffer[63:0] 10/28: $0\accumulator[63:0] 11/28: $0\timeout_counter[31:0] 12/28: $0\timeout[31:0] 13/28: $0\read_buffer[31:0] 14/28: $0\communication_buffer[31:0] 15/28: $0\num_of_positions[23:0] 16/28: $0\num_of_pages[23:0] 17/28: $0\return_state[7:0] 18/28: $0\memory_page_number[23:0] 19/28: $0\memory_mux_selector[0:0] 20/28: $0\end_position[31:0] 21/28: $0\memory_page_size[23:0] 22/28: $0\bus_mode[0:0] 23/28: $0\num_of_cycles_to_pulse[31:0] 24/28: $0\core_clk_enable[0:0] 25/28: $0\communication_write_data[31:0] 26/28: $0\counter[7:0] 27/28: $0\write_data[31:0] 28/28: $0\address[31:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1103'. Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. 1/4: $0\tx_fifo_read[0:0] 2/4: $0\uart_tx_en[0:0] 3/4: $0\tx_fifo_read_state[1:0] 4/4: $0\uart_tx_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1091'. 1/2: $0\rx_fifo_write[0:0] 2/2: $0\rx_fifo_write_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. 1/6: $0\tx_fifo_write[0:0] 2/6: $0\write_response[0:0] 3/6: $0\state_write[3:0] 4/6: $0\counter_write[2:0] 5/6: $0\write_data_buffer[31:0] 6/6: $0\tx_fifo_write_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. 1/5: $0\read_response[0:0] 2/5: $0\rx_fifo_read[0:0] 3/5: $0\state_read[3:0] 4/5: $0\counter_read[2:0] 5/5: $0\read_data[31:0] Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$874'. Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$864'. 1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$873 2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_DATA[31:0]$872 3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_ADDR[31:0]$871 4/4: $0\read_sync[31:0] Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$853'. 1/1: $0\finish_execution[0:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$810'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$803'. 1/3: $0\counter[5:0] 2/3: $0\reset_o[0:0] 3/3: $0\state[1:0] Creating decoders for process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$799'. 1/1: $0\qout_r[7:0] Creating decoders for process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$796'. 1/1: $0\qout_r[4:0] Creating decoders for process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$793'. 1/1: $0\qout_r[0:0] Creating decoders for process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$790'. 1/1: $0\qout_r[31:0] Creating decoders for process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$262'. 1/1: $1\jtag_data_o[31:0] Creating decoders for process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$256'. 1/2: $2\rdata2_o[31:0] 2/2: $1\rdata2_o[31:0] Creating decoders for process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$250'. 1/2: $2\rdata1_o[31:0] 2/2: $1\rdata1_o[31:0] Creating decoders for process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'. 1/15: $3$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_EN[31:0]$249 2/15: $3$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_DATA[31:0]$248 3/15: $3$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_ADDR[4:0]$247 4/15: $2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$240 5/15: $2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_DATA[31:0]$239 6/15: $2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_ADDR[4:0]$238 7/15: $2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_EN[31:0]$243 8/15: $2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_DATA[31:0]$242 9/15: $2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_ADDR[4:0]$241 10/15: $1$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_EN[31:0]$234 11/15: $1$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_DATA[31:0]$233 12/15: $1$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_ADDR[4:0]$232 13/15: $1$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$231 14/15: $1$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_DATA[31:0]$230 15/15: $1$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_ADDR[4:0]$229 Creating decoders for process `\pc_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$212'. 1/1: $0\pc_o[31:0] Creating decoders for process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. 1/72: $2\csr_we_o[0:0] 2/72: $10\reg_waddr_o[4:0] 3/72: $10\reg_we_o[0:0] 4/72: $10\reg2_raddr_o[4:0] 5/72: $10\reg1_raddr_o[4:0] 6/72: $5\op2_jump_o[31:0] 7/72: $5\op1_jump_o[31:0] 8/72: $9\op2_o[31:0] 9/72: $9\op1_o[31:0] 10/72: $9\reg_waddr_o[4:0] 11/72: $9\reg_we_o[0:0] 12/72: $9\reg2_raddr_o[4:0] 13/72: $9\reg1_raddr_o[4:0] 14/72: $8\op2_o[31:0] 15/72: $8\op1_o[31:0] 16/72: $8\reg_waddr_o[4:0] 17/72: $8\reg_we_o[0:0] 18/72: $8\reg2_raddr_o[4:0] 19/72: $8\reg1_raddr_o[4:0] 20/72: $7\op2_o[31:0] 21/72: $7\op1_o[31:0] 22/72: $7\reg_waddr_o[4:0] 23/72: $7\reg_we_o[0:0] 24/72: $7\reg2_raddr_o[4:0] 25/72: $7\reg1_raddr_o[4:0] 26/72: $6\op2_o[31:0] 27/72: $6\op1_o[31:0] 28/72: $6\reg2_raddr_o[4:0] 29/72: $6\reg1_raddr_o[4:0] 30/72: $6\reg_waddr_o[4:0] 31/72: $6\reg_we_o[0:0] 32/72: $4\op2_jump_o[31:0] 33/72: $4\op1_jump_o[31:0] 34/72: $3\op2_jump_o[31:0] 35/72: $3\op1_jump_o[31:0] 36/72: $5\op2_o[31:0] 37/72: $5\op1_o[31:0] 38/72: $5\reg2_raddr_o[4:0] 39/72: $5\reg1_raddr_o[4:0] 40/72: $5\reg_we_o[0:0] 41/72: $5\reg_waddr_o[4:0] 42/72: $4\op2_o[31:0] 43/72: $4\op1_o[31:0] 44/72: $4\reg2_raddr_o[4:0] 45/72: $4\reg1_raddr_o[4:0] 46/72: $4\reg_waddr_o[4:0] 47/72: $4\reg_we_o[0:0] 48/72: $3\op2_o[31:0] 49/72: $3\op1_o[31:0] 50/72: $3\reg2_raddr_o[4:0] 51/72: $3\reg1_raddr_o[4:0] 52/72: $3\reg_we_o[0:0] 53/72: $3\reg_waddr_o[4:0] 54/72: $2\op2_jump_o[31:0] 55/72: $2\op1_jump_o[31:0] 56/72: $2\op2_o[31:0] 57/72: $2\op1_o[31:0] 58/72: $2\reg2_raddr_o[4:0] 59/72: $2\reg1_raddr_o[4:0] 60/72: $2\reg_waddr_o[4:0] 61/72: $2\reg_we_o[0:0] 62/72: $1\op2_o[31:0] 63/72: $1\op1_o[31:0] 64/72: $1\reg2_raddr_o[4:0] 65/72: $1\reg1_raddr_o[4:0] 66/72: $1\reg_we_o[0:0] 67/72: $1\reg_waddr_o[4:0] 68/72: $1\op2_jump_o[31:0] 69/72: $1\op1_jump_o[31:0] 70/72: $1\csr_raddr_o[31:0] 71/72: $1\csr_waddr_o[31:0] 72/72: $1\csr_we_o[0:0] Creating decoders for process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. 1/96: $19\reg_wdata[31:0] 2/96: $2\csr_wdata_o[31:0] 3/96: $10\mem_we[0:0] 4/96: $10\jump_addr[31:0] 5/96: $10\jump_flag[0:0] 6/96: $10\hold_flag[0:0] 7/96: $10\mem_waddr_o[31:0] 8/96: $10\mem_raddr_o[31:0] 9/96: $12\mem_wdata_o[31:0] 10/96: $9\jump_addr[31:0] 11/96: $9\jump_flag[0:0] 12/96: $18\reg_wdata[31:0] 13/96: $9\mem_we[0:0] 14/96: $9\mem_waddr_o[31:0] 15/96: $9\mem_raddr_o[31:0] 16/96: $11\mem_wdata_o[31:0] 17/96: $9\hold_flag[0:0] 18/96: $10\mem_wdata_o[31:0] 19/96: $9\mem_wdata_o[31:0] 20/96: $8\mem_wdata_o[31:0] 21/96: $8\mem_raddr_o[31:0] 22/96: $8\mem_waddr_o[31:0] 23/96: $3\mem_req[0:0] 24/96: $8\mem_we[0:0] 25/96: $17\reg_wdata[31:0] 26/96: $8\jump_addr[31:0] 27/96: $8\hold_flag[0:0] 28/96: $8\jump_flag[0:0] 29/96: $16\reg_wdata[31:0] 30/96: $15\reg_wdata[31:0] 31/96: $14\reg_wdata[31:0] 32/96: $13\reg_wdata[31:0] 33/96: $12\reg_wdata[31:0] 34/96: $7\mem_raddr_o[31:0] 35/96: $2\mem_req[0:0] 36/96: $7\mem_we[0:0] 37/96: $7\mem_waddr_o[31:0] 38/96: $7\mem_wdata_o[31:0] 39/96: $7\jump_addr[31:0] 40/96: $7\hold_flag[0:0] 41/96: $7\jump_flag[0:0] 42/96: $11\reg_wdata[31:0] 43/96: $10\reg_wdata[31:0] 44/96: $9\reg_wdata[31:0] 45/96: $6\mem_we[0:0] 46/96: $6\mem_waddr_o[31:0] 47/96: $6\mem_raddr_o[31:0] 48/96: $6\mem_wdata_o[31:0] 49/96: $6\jump_addr[31:0] 50/96: $6\hold_flag[0:0] 51/96: $6\jump_flag[0:0] 52/96: $5\mem_we[0:0] 53/96: $5\jump_addr[31:0] 54/96: $5\jump_flag[0:0] 55/96: $5\hold_flag[0:0] 56/96: $8\reg_wdata[31:0] 57/96: $5\mem_waddr_o[31:0] 58/96: $5\mem_raddr_o[31:0] 59/96: $5\mem_wdata_o[31:0] 60/96: $7\reg_wdata[31:0] 61/96: $6\reg_wdata[31:0] 62/96: $5\reg_wdata[31:0] 63/96: $4\mem_we[0:0] 64/96: $4\mem_waddr_o[31:0] 65/96: $4\mem_raddr_o[31:0] 66/96: $4\mem_wdata_o[31:0] 67/96: $4\jump_addr[31:0] 68/96: $4\hold_flag[0:0] 69/96: $4\jump_flag[0:0] 70/96: $3\mem_we[0:0] 71/96: $3\jump_addr[31:0] 72/96: $3\jump_flag[0:0] 73/96: $3\hold_flag[0:0] 74/96: $4\reg_wdata[31:0] 75/96: $3\mem_waddr_o[31:0] 76/96: $3\mem_raddr_o[31:0] 77/96: $3\mem_wdata_o[31:0] 78/96: $3\reg_wdata[31:0] 79/96: $2\reg_wdata[31:0] 80/96: $2\mem_we[0:0] 81/96: $2\mem_waddr_o[31:0] 82/96: $2\mem_raddr_o[31:0] 83/96: $2\mem_wdata_o[31:0] 84/96: $2\jump_addr[31:0] 85/96: $2\hold_flag[0:0] 86/96: $2\jump_flag[0:0] 87/96: $1\mem_we[0:0] 88/96: $1\jump_addr[31:0] 89/96: $1\jump_flag[0:0] 90/96: $1\hold_flag[0:0] 91/96: $1\reg_wdata[31:0] 92/96: $1\mem_waddr_o[31:0] 93/96: $1\mem_raddr_o[31:0] 94/96: $1\mem_wdata_o[31:0] 95/96: $1\mem_req[0:0] 96/96: $1\csr_wdata_o[31:0] Creating decoders for process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. 1/19: $3\div_we[0:0] 2/19: $3\div_waddr[4:0] 3/19: $3\div_wdata[31:0] 4/19: $3\div_hold_flag[0:0] 5/19: $2\div_waddr[4:0] 6/19: $2\div_wdata[31:0] 7/19: $2\div_we[0:0] 8/19: $3\div_start[0:0] 9/19: $2\div_jump_addr[31:0] 10/19: $2\div_hold_flag[0:0] 11/19: $2\div_jump_flag[0:0] 12/19: $2\div_start[0:0] 13/19: $1\div_start[0:0] 14/19: $1\div_jump_addr[31:0] 15/19: $1\div_jump_flag[0:0] 16/19: $1\div_hold_flag[0:0] 17/19: $1\div_waddr[4:0] 18/19: $1\div_wdata[31:0] 19/19: $1\div_we[0:0] Creating decoders for process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$126'. 1/4: $2\mul_op2[31:0] 2/4: $2\mul_op1[31:0] 3/4: $1\mul_op2[31:0] 4/4: $1\mul_op1[31:0] Creating decoders for process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. 1/13: $0\invert_result[0:0] 2/13: $0\minuend[31:0] 3/13: $0\div_remain[31:0] 4/13: $0\div_result[31:0] 5/13: $0\count[31:0] 6/13: $0\state[3:0] 7/13: $0\op_r[2:0] 8/13: $0\divisor_r[31:0] 9/13: $0\dividend_r[31:0] 10/13: $0\reg_waddr_o[4:0] 11/13: $0\busy_o[0:0] 12/13: $0\ready_o[0:0] 13/13: $0\result_o[31:0] Creating decoders for process `\ctrl.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46'. 1/3: $3\hold_flag_o[2:0] 2/3: $2\hold_flag_o[2:0] 3/3: $1\hold_flag_o[2:0] Creating decoders for process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$42'. 1/2: $2\clint_data_o[31:0] 2/2: $1\clint_data_o[31:0] Creating decoders for process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$38'. 1/2: $2\data_o[31:0] 2/2: $1\data_o[31:0] Creating decoders for process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'. 1/6: $0\mscratch[31:0] 2/6: $0\mstatus[31:0] 3/6: $0\mie[31:0] 4/6: $0\mepc[31:0] 5/6: $0\mcause[31:0] 6/6: $0\mtvec[31:0] Creating decoders for process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$31'. 1/1: $0\cycle[63:0] Creating decoders for process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$27'. 1/2: $0\int_addr_o[31:0] 2/2: $0\int_assert_o[0:0] Creating decoders for process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25'. 1/3: $0\data_o[31:0] 2/3: $0\waddr_o[31:0] 3/3: $0\we_o[0:0] Creating decoders for process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15'. 1/3: $0\cause[31:0] 2/3: $0\inst_addr[31:0] 3/3: $0\csr_state[4:0] Creating decoders for process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$5'. 1/5: $5\int_state[3:0] 2/5: $4\int_state[3:0] 3/5: $3\int_state[3:0] 4/5: $2\int_state[3:0] 5/5: $1\int_state[3:0] 24.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1219'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1162'. No latch inferred for signal `\regs.\jtag_data_o' from process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$262'. No latch inferred for signal `\regs.\rdata2_o' from process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$256'. No latch inferred for signal `\regs.\rdata1_o' from process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$250'. No latch inferred for signal `\id.\reg_waddr_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\reg_we_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\csr_we_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\csr_waddr_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\reg1_raddr_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\reg2_raddr_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\csr_raddr_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\op1_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\op2_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\op1_jump_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\op2_jump_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\inst_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\inst_addr_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\reg1_rdata_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\reg2_rdata_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\id.\csr_rdata_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. No latch inferred for signal `\ex.\mem_wdata_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. No latch inferred for signal `\ex.\mem_raddr_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. No latch inferred for signal `\ex.\mem_waddr_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. No latch inferred for signal `\ex.\csr_wdata_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. No latch inferred for signal `\ex.\reg_wdata' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. No latch inferred for signal `\ex.\reg_we' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. No latch inferred for signal `\ex.\reg_waddr' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. No latch inferred for signal `\ex.\hold_flag' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. No latch inferred for signal `\ex.\jump_flag' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. No latch inferred for signal `\ex.\jump_addr' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. No latch inferred for signal `\ex.\mem_we' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. No latch inferred for signal `\ex.\mem_req' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. No latch inferred for signal `\ex.\div_dividend_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. No latch inferred for signal `\ex.\div_divisor_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. No latch inferred for signal `\ex.\div_op_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. No latch inferred for signal `\ex.\div_reg_waddr_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. No latch inferred for signal `\ex.\div_wdata' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. No latch inferred for signal `\ex.\div_we' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. No latch inferred for signal `\ex.\div_waddr' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. No latch inferred for signal `\ex.\div_hold_flag' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. No latch inferred for signal `\ex.\div_jump_flag' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. No latch inferred for signal `\ex.\div_jump_addr' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. No latch inferred for signal `\ex.\div_start' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. No latch inferred for signal `\ex.\mul_op1' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$126'. No latch inferred for signal `\ex.\mul_op2' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$126'. No latch inferred for signal `\ctrl.\hold_flag_o' from process `\ctrl.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46'. No latch inferred for signal `\ctrl.\jump_flag_o' from process `\ctrl.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46'. No latch inferred for signal `\ctrl.\jump_addr_o' from process `\ctrl.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46'. No latch inferred for signal `\csr_reg.\clint_data_o' from process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$42'. No latch inferred for signal `\csr_reg.\data_o' from process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$38'. No latch inferred for signal `\clint.\int_state' from process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$5'. 24.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$788'. created $dff cell `$procdff$6023' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$724_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$725_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$726_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$727_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$728_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$729_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$730_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$731_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$732_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$733_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$734_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$735_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$736_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$737_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$738_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$739_ADDR' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$740'. created $dff cell `$procdff$6024' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$739_DATA' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$740'. created $dff cell `$procdff$6025' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$739_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$740'. created $dff cell `$procdff$6026' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$664_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$665_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$666_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$667_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$668_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$669_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$670_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$671_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$672_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$673_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$674_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$675_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$676_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$677_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$678_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$679_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$680_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$682'. created $dff cell `$procdff$6027' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$680_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$682'. created $dff cell `$procdff$6028' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$680_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$682'. created $dff cell `$procdff$6029' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$681'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. created $dff cell `$procdff$6030' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. created $dff cell `$procdff$6031' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. created $dff cell `$procdff$6032' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. created $dff cell `$procdff$6033' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1047'. created $dff cell `$procdff$6034' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1047'. created $dff cell `$procdff$6035' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1248'. created $dff cell `$procdff$6036' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1248'. created $dff cell `$procdff$6037' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1246'. created $dff cell `$procdff$6038' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1238'. created $dff cell `$procdff$6039' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1235'. created $dff cell `$procdff$6040' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1229'. created $dff cell `$procdff$6041' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1224'. created $dff cell `$procdff$6042' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1224'. created $dff cell `$procdff$6043' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1210'. created $dff cell `$procdff$6044' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1197'. created $dff cell `$procdff$6045' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1195'. created $dff cell `$procdff$6046' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1187'. created $dff cell `$procdff$6047' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1173'. created $dff cell `$procdff$6048' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1167'. created $dff cell `$procdff$6049' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1167'. created $dff cell `$procdff$6050' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1149'. created $dff cell `$procdff$6051' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1140'. created $dff cell `$procdff$6052' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1140'. created $dff cell `$procdff$6053' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6054' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6055' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6056' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6057' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6058' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6059' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6060' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6061' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6062' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6063' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6064' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6065' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6066' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6067' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6068' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6069' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6070' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6071' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6072' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6073' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6074' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6075' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6076' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6077' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6078' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6079' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6080' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6081' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. created $dff cell `$procdff$6082' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. created $dff cell `$procdff$6083' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. created $dff cell `$procdff$6084' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. created $dff cell `$procdff$6085' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1091'. created $dff cell `$procdff$6086' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1091'. created $dff cell `$procdff$6087' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. created $dff cell `$procdff$6088' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. created $dff cell `$procdff$6089' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. created $dff cell `$procdff$6090' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. created $dff cell `$procdff$6091' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. created $dff cell `$procdff$6092' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. created $dff cell `$procdff$6093' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. created $dff cell `$procdff$6094' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. created $dff cell `$procdff$6095' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. created $dff cell `$procdff$6096' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. created $dff cell `$procdff$6097' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. created $dff cell `$procdff$6098' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$874'. created $dff cell `$procdff$6099' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$874'. created $dff cell `$procdff$6100' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$864'. created $dff cell `$procdff$6101' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$864'. created $dff cell `$procdff$6102' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$864'. created $dff cell `$procdff$6103' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$864'. created $dff cell `$procdff$6104' with positive edge clock. Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$853'. created $dff cell `$procdff$6105' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$803'. created $dff cell `$procdff$6106' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$803'. created $dff cell `$procdff$6107' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$803'. created $dff cell `$procdff$6108' with positive edge clock. Creating register for signal `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.\qout_r' using process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$799'. created $dff cell `$procdff$6109' with positive edge clock. Creating register for signal `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.\qout_r' using process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$796'. created $dff cell `$procdff$6110' with positive edge clock. Creating register for signal `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.\qout_r' using process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$793'. created $dff cell `$procdff$6111' with positive edge clock. Creating register for signal `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.\qout_r' using process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$790'. created $dff cell `$procdff$6112' with positive edge clock. Creating register for signal `\regs.$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_ADDR' using process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'. created $dff cell `$procdff$6113' with positive edge clock. Creating register for signal `\regs.$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_DATA' using process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'. created $dff cell `$procdff$6114' with positive edge clock. Creating register for signal `\regs.$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN' using process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'. created $dff cell `$procdff$6115' with positive edge clock. Creating register for signal `\regs.$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_ADDR' using process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'. created $dff cell `$procdff$6116' with positive edge clock. Creating register for signal `\regs.$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_DATA' using process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'. created $dff cell `$procdff$6117' with positive edge clock. Creating register for signal `\regs.$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_EN' using process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'. created $dff cell `$procdff$6118' with positive edge clock. Creating register for signal `\pc_reg.\pc_o' using process `\pc_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$212'. created $dff cell `$procdff$6119' with positive edge clock. Creating register for signal `\div.\result_o' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6120' with positive edge clock. Creating register for signal `\div.\ready_o' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6121' with positive edge clock. Creating register for signal `\div.\busy_o' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6122' with positive edge clock. Creating register for signal `\div.\reg_waddr_o' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6123' with positive edge clock. Creating register for signal `\div.\dividend_r' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6124' with positive edge clock. Creating register for signal `\div.\divisor_r' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6125' with positive edge clock. Creating register for signal `\div.\op_r' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6126' with positive edge clock. Creating register for signal `\div.\state' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6127' with positive edge clock. Creating register for signal `\div.\count' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6128' with positive edge clock. Creating register for signal `\div.\div_result' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6129' with positive edge clock. Creating register for signal `\div.\div_remain' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6130' with positive edge clock. Creating register for signal `\div.\minuend' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6131' with positive edge clock. Creating register for signal `\div.\invert_result' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. created $dff cell `$procdff$6132' with positive edge clock. Creating register for signal `\csr_reg.\mtvec' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'. created $dff cell `$procdff$6133' with positive edge clock. Creating register for signal `\csr_reg.\mcause' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'. created $dff cell `$procdff$6134' with positive edge clock. Creating register for signal `\csr_reg.\mepc' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'. created $dff cell `$procdff$6135' with positive edge clock. Creating register for signal `\csr_reg.\mie' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'. created $dff cell `$procdff$6136' with positive edge clock. Creating register for signal `\csr_reg.\mstatus' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'. created $dff cell `$procdff$6137' with positive edge clock. Creating register for signal `\csr_reg.\mscratch' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'. created $dff cell `$procdff$6138' with positive edge clock. Creating register for signal `\csr_reg.\cycle' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$31'. created $dff cell `$procdff$6139' with positive edge clock. Creating register for signal `\clint.\int_addr_o' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$27'. created $dff cell `$procdff$6140' with positive edge clock. Creating register for signal `\clint.\int_assert_o' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$27'. created $dff cell `$procdff$6141' with positive edge clock. Creating register for signal `\clint.\we_o' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25'. created $dff cell `$procdff$6142' with positive edge clock. Creating register for signal `\clint.\waddr_o' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25'. created $dff cell `$procdff$6143' with positive edge clock. Creating register for signal `\clint.\data_o' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25'. created $dff cell `$procdff$6144' with positive edge clock. Creating register for signal `\clint.\csr_state' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15'. created $dff cell `$procdff$6145' with positive edge clock. Creating register for signal `\clint.\inst_addr' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15'. created $dff cell `$procdff$6146' with positive edge clock. Creating register for signal `\clint.\cause' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15'. created $dff cell `$procdff$6147' with positive edge clock. 24.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$789'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$788'. Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$788'. Removing empty process `DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$763'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$740'. Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$706'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$682'. Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$681'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1080'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1047'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1047'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1250'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1248'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1248'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1246'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1246'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1238'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1238'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1235'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1235'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1229'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1229'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1224'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1224'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1219'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1219'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1210'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1210'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1203'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1197'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1197'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1195'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1195'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1187'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1187'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1173'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1173'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1167'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1167'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1162'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1162'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1155'. Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1149'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1149'. Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1140'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1140'. Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1133'. Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1103'. Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1091'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1091'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$874'. Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$864'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$864'. Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$853'. Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$853'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$810'. Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$803'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$803'. Found and cleaned up 1 empty switch in `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$799'. Removing empty process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$799'. Found and cleaned up 1 empty switch in `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$796'. Removing empty process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$796'. Found and cleaned up 1 empty switch in `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$793'. Removing empty process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$793'. Found and cleaned up 1 empty switch in `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$790'. Removing empty process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$790'. Found and cleaned up 1 empty switch in `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$262'. Removing empty process `regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$262'. Found and cleaned up 2 empty switches in `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$256'. Removing empty process `regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$256'. Found and cleaned up 2 empty switches in `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$250'. Removing empty process `regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$250'. Found and cleaned up 3 empty switches in `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'. Removing empty process `regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'. Found and cleaned up 3 empty switches in `\pc_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$212'. Removing empty process `pc_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$212'. Found and cleaned up 10 empty switches in `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. Removing empty process `id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'. Found and cleaned up 21 empty switches in `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. Removing empty process `ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'. Found and cleaned up 4 empty switches in `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. Removing empty process `ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'. Found and cleaned up 2 empty switches in `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$126'. Removing empty process `ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$126'. Found and cleaned up 17 empty switches in `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. Removing empty process `div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'. Found and cleaned up 3 empty switches in `\ctrl.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46'. Removing empty process `ctrl.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46'. Found and cleaned up 2 empty switches in `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$42'. Removing empty process `csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$42'. Found and cleaned up 2 empty switches in `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$38'. Removing empty process `csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$38'. Found and cleaned up 5 empty switches in `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'. Removing empty process `csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'. Found and cleaned up 1 empty switch in `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$31'. Removing empty process `csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$31'. Found and cleaned up 2 empty switches in `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$27'. Removing empty process `clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$27'. Found and cleaned up 2 empty switches in `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25'. Removing empty process `clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25'. Found and cleaned up 9 empty switches in `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15'. Removing empty process `clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15'. Found and cleaned up 5 empty switches in `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$5'. Removing empty process `clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$5'. Cleaned up 193 empty switches. 24.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. <suppressed ~5 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. <suppressed ~21 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. <suppressed ~19 debug messages> Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. <suppressed ~9 debug messages> Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. <suppressed ~15 debug messages> Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. <suppressed ~24 debug messages> Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. <suppressed ~3 debug messages> Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. <suppressed ~26 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~8 debug messages> Optimizing module processorci_top. Optimizing module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000. Optimizing module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101. Optimizing module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001. Optimizing module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000. Optimizing module tinyriscv. <suppressed ~1 debug messages> Optimizing module regs. <suppressed ~10 debug messages> Optimizing module pc_reg. <suppressed ~3 debug messages> Optimizing module if_id. Optimizing module id_ex. Optimizing module id. <suppressed ~36 debug messages> Optimizing module ex. <suppressed ~67 debug messages> Optimizing module div. <suppressed ~23 debug messages> Optimizing module ctrl. <suppressed ~5 debug messages> Optimizing module csr_reg. <suppressed ~14 debug messages> Optimizing module clint. <suppressed ~24 debug messages> 24.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000. Deleting now unused module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101. Deleting now unused module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001. Deleting now unused module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000. Deleting now unused module tinyriscv. Deleting now unused module regs. Deleting now unused module pc_reg. Deleting now unused module if_id. Deleting now unused module id_ex. Deleting now unused module id. Deleting now unused module ex. Deleting now unused module div. Deleting now unused module ctrl. Deleting now unused module csr_reg. Deleting now unused module clint. <suppressed ~38 debug messages> 24.6. Executing TRIBUF pass. 24.7. Executing DEMINOUT pass (demote inout ports to input or output). 24.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~72 debug messages> 24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 115 unused cells and 1427 unused wires. <suppressed ~148 debug messages> 24.10. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Warning: Wire processorci_top.\miso is used but has no driver. Warning: Wire processorci_top.\intr is used but has no driver. Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver. Found and reported 3 problems. 24.11. Executing OPT pass (performing simple optimizations). 24.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~2979 debug messages> Removed a total of 993 cells. 24.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $flatten\u_tinyriscv.\u_ex.$ternary$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:185$135: \u_tinyriscv.u_id_ex.reg2_rdata_ff.qout_r -> { 1'0 \u_tinyriscv.u_id_ex.reg2_rdata_ff.qout_r [30:0] } Replacing known input bits on port A of cell $flatten\u_tinyriscv.\u_ex.$ternary$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:184$133: \u_tinyriscv.u_id_ex.reg1_rdata_ff.qout_r -> { 1'0 \u_tinyriscv.u_id_ex.reg1_rdata_ff.qout_r [30:0] } Replacing known input bits on port A of cell $flatten\u_tinyriscv.\u_ex.$ternary$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:180$131: \u_tinyriscv.u_id_ex.reg1_rdata_ff.qout_r -> { 1'0 \u_tinyriscv.u_id_ex.reg1_rdata_ff.qout_r [30:0] } Replacing known input bits on port A of cell $flatten\u_tinyriscv.\u_div.$procmux$5590: \u_tinyriscv.u_div.divisor_r -> { 1'0 \u_tinyriscv.u_div.divisor_r [30:0] } Replacing known input bits on port A of cell $flatten\u_tinyriscv.\u_div.$procmux$5617: \u_tinyriscv.u_div.dividend_r -> { 1'0 \u_tinyriscv.u_div.dividend_r [30:0] } Replacing known input bits on port A of cell $flatten\u_tinyriscv.\u_div.$procmux$5483: { 31'0000000000000000000000000000000 \u_tinyriscv.u_div.dividend_r [31] } -> 0 Analyzing evaluation results. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3776. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3787. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3797. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3807. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3817. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3827. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3837. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3847. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3857. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3873. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3889. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3904. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3919. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3934. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3949. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3964. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3979. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3993. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3995. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4012. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4014. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4028. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4042. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4056. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4070. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4084. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4097. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4110. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4123. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4136. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4150. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4152. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4169. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4171. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4188. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4190. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4210. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4212. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4229. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4246. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4263. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4279. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4295. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4311. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4327. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4343. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4359. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4375. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4377. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4380. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4382. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4401. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4403. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4406. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4408. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4426. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4429. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4431. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4448. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4451. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4453. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4470. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4473. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4475. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4492. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4495. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4497. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4514. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4517. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4519. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4536. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4539. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4541. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4558. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4561. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4563. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4580. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4583. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4585. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4600. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4602. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4617. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4619. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4634. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4636. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4651. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4653. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4668. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4670. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4685. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4687. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4702. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4704. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4719. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4721. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4738. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4740. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4742. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4764. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4766. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4768. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4789. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4791. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4812. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4814. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4835. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4837. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4858. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4860. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4881. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4883. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4904. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4906. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4927. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4929. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4950. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4952. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4966. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4980. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4994. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5008. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5022. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5036. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5050. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5064. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5079. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5081. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5102. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5123. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5144. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5165. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5186. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1278. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5207. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1284. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1290. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5228. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5249. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1278. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1284. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1290. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5338. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5341. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5347. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5350. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5356. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5359. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5365. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5371. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5377. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5383. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5389. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5395. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5401. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5407. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5413. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5440. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5447. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2712. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2719. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2726. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2732. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2739. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2752. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2765. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2778. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2791. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2803. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2815. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2828. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2841. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2855. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2869. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2882. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2895. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2909. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2923. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2938. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2953. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2968. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2983. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2997. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3012. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3029. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3032. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3034. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3051. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3054. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3056. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3073. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3076. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3078. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3095. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3098. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3100. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3117. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3120. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3122. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3139. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3142. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3144. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3161. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3164. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3166. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3183. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3186. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3188. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3205. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3207. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3224. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3226. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3243. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3245. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3262. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3264. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3281. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3283. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3300. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3302. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3319. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3321. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3338. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3340. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3356. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3358. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3374. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3376. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3392. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3394. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$5988. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$5991. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$5994. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3410. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3412. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$6000. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$6003. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$6009. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$6012. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$6018. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3428. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3430. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3446. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3448. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3464. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3480. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3496. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3512. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3528. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3544. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3560. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3576. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_csr_reg.$procmux$5770. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3592. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3608. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3624. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3640. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3656. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3672. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ctrl.$procmux$5732. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ctrl.$procmux$5738. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2603. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2612. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2622. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2624. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2648. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2654. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2660. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2666. Removed 268 multiplexer ports. <suppressed ~188 debug messages> 24.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4398: $auto$opt_reduce.cc:137:opt_pmux$6191 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2296: { $flatten\Controller.\Interpreter.$procmux$1741_CMP $flatten\Controller.\Interpreter.$procmux$1740_CMP $auto$opt_reduce.cc:137:opt_pmux$6193 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1614: { $flatten\Controller.\Interpreter.$procmux$1708_CMP $flatten\Controller.\Interpreter.$procmux$1704_CMP $flatten\Controller.\Interpreter.$procmux$1700_CMP $flatten\Controller.\Interpreter.$procmux$1674_CMP $flatten\Controller.\Interpreter.$procmux$1673_CMP $flatten\Controller.\Interpreter.$procmux$1669_CMP $flatten\Controller.\Interpreter.$procmux$1668_CMP $flatten\Controller.\Interpreter.$procmux$1664_CMP $flatten\Controller.\Interpreter.$procmux$1654_CMP $flatten\Controller.\Interpreter.$procmux$1650_CMP $auto$opt_reduce.cc:137:opt_pmux$6201 $flatten\Controller.\Interpreter.$procmux$1645_CMP $flatten\Controller.\Interpreter.$procmux$1644_CMP $auto$opt_reduce.cc:137:opt_pmux$6199 $flatten\Controller.\Interpreter.$procmux$1639_CMP $flatten\Controller.\Interpreter.$procmux$1638_CMP $flatten\Controller.\Interpreter.$procmux$1633_CMP $flatten\Controller.\Interpreter.$procmux$1629_CMP $flatten\Controller.\Interpreter.$procmux$1628_CMP $auto$opt_reduce.cc:137:opt_pmux$6197 $flatten\Controller.\Interpreter.$procmux$1622_CMP $flatten\Controller.\Interpreter.$procmux$1621_CMP $flatten\Controller.\Interpreter.$procmux$1620_CMP $auto$opt_reduce.cc:137:opt_pmux$6195 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2322: { $auto$opt_reduce.cc:137:opt_pmux$6203 $flatten\Controller.\Interpreter.$procmux$1740_CMP $flatten\Controller.\Interpreter.$procmux$1659_CMP $flatten\Controller.\Interpreter.$procmux$1654_CMP $flatten\Controller.\Interpreter.$procmux$1644_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1939: { $auto$opt_reduce.cc:137:opt_pmux$6207 $auto$opt_reduce.cc:137:opt_pmux$6205 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$3769: $auto$opt_reduce.cc:137:opt_pmux$6209 Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2524: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4803: $auto$opt_reduce.cc:137:opt_pmux$6211 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4826: $auto$opt_reduce.cc:137:opt_pmux$6213 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4849: $auto$opt_reduce.cc:137:opt_pmux$6215 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4872: $auto$opt_reduce.cc:137:opt_pmux$6217 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4895: $auto$opt_reduce.cc:137:opt_pmux$6219 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4918: $auto$opt_reduce.cc:137:opt_pmux$6221 New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2392: $auto$opt_reduce.cc:137:opt_pmux$6223 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4941: $auto$opt_reduce.cc:137:opt_pmux$6225 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2008: $auto$opt_reduce.cc:137:opt_pmux$6227 New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2456: $auto$opt_reduce.cc:137:opt_pmux$6229 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5114: $auto$opt_reduce.cc:137:opt_pmux$6231 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5135: $auto$opt_reduce.cc:137:opt_pmux$6233 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5156: $auto$opt_reduce.cc:137:opt_pmux$6235 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2033: { $flatten\Controller.\Interpreter.$procmux$1654_CMP $auto$opt_reduce.cc:137:opt_pmux$6237 $flatten\Controller.\Interpreter.$procmux$1644_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5177: $auto$opt_reduce.cc:137:opt_pmux$6239 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5198: $auto$opt_reduce.cc:137:opt_pmux$6241 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5219: $auto$opt_reduce.cc:137:opt_pmux$6243 Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2524: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_EN[31:0]$867 [0] } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5240: $auto$opt_reduce.cc:137:opt_pmux$6245 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5252: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5260: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y $flatten\u_tinyriscv.\u_ex.$procmux$3874_CMP $auto$opt_reduce.cc:137:opt_pmux$6247 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5270: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y $flatten\u_tinyriscv.\u_ex.$procmux$3874_CMP $auto$opt_reduce.cc:137:opt_pmux$6249 } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1886: { $flatten\Controller.\Interpreter.$procmux$1654_CMP $auto$opt_reduce.cc:137:opt_pmux$6251 $flatten\Controller.\Interpreter.$procmux$1644_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5280: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5288: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y $flatten\u_tinyriscv.\u_ex.$procmux$4153_CMP $auto$opt_reduce.cc:137:opt_pmux$6253 $flatten\u_tinyriscv.\u_ex.$procmux$3777_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5298: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5306: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y $flatten\u_tinyriscv.\u_ex.$procmux$4153_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5314: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2061: { $flatten\Controller.\Interpreter.$procmux$1640_CMP $flatten\Controller.\Interpreter.$procmux$1633_CMP $flatten\Controller.\Interpreter.$procmux$1622_CMP $flatten\Controller.\Interpreter.$procmux$1616_CMP $auto$opt_reduce.cc:137:opt_pmux$6255 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$2709: $auto$opt_reduce.cc:137:opt_pmux$6257 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$2716: $auto$opt_reduce.cc:137:opt_pmux$6259 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$2723: $auto$opt_reduce.cc:137:opt_pmux$6261 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4038: $auto$opt_reduce.cc:137:opt_pmux$6263 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4052: $auto$opt_reduce.cc:137:opt_pmux$6265 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1819: $auto$opt_reduce.cc:137:opt_pmux$6267 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2093: { $auto$opt_reduce.cc:137:opt_pmux$6271 $auto$opt_reduce.cc:137:opt_pmux$6269 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4066: $auto$opt_reduce.cc:137:opt_pmux$6273 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3026: $auto$opt_reduce.cc:137:opt_pmux$6275 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3048: $auto$opt_reduce.cc:137:opt_pmux$6277 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4080: $auto$opt_reduce.cc:137:opt_pmux$6279 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3070: $auto$opt_reduce.cc:137:opt_pmux$6281 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3092: $auto$opt_reduce.cc:137:opt_pmux$6283 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3114: $auto$opt_reduce.cc:137:opt_pmux$6285 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_clint.$procmux$5888: $auto$opt_reduce.cc:137:opt_pmux$6287 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_clint.$procmux$5904: { $flatten\u_tinyriscv.\u_clint.$procmux$5899_CMP $flatten\u_tinyriscv.\u_clint.$procmux$5883_CMP $auto$opt_reduce.cc:137:opt_pmux$6289 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2175: { $flatten\Controller.\Interpreter.$procmux$1634_CMP $auto$opt_reduce.cc:137:opt_pmux$6291 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_clint.$procmux$5913: $auto$opt_reduce.cc:137:opt_pmux$6293 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1714: $auto$opt_reduce.cc:137:opt_pmux$6295 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1738: $auto$opt_reduce.cc:137:opt_pmux$6297 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2186: { $flatten\Controller.\Interpreter.$procmux$1775_CMP $flatten\Controller.\Interpreter.$procmux$1674_CMP $auto$opt_reduce.cc:137:opt_pmux$6299 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1861: $auto$opt_reduce.cc:137:opt_pmux$6301 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4240: $auto$opt_reduce.cc:137:opt_pmux$6303 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2196: { $flatten\Controller.\Interpreter.$procmux$1673_CMP $auto$opt_reduce.cc:137:opt_pmux$6307 $auto$opt_reduce.cc:137:opt_pmux$6305 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4257: $auto$opt_reduce.cc:137:opt_pmux$6309 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3678: { $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $flatten\u_tinyriscv.\u_id.$procmux$2856_CMP $flatten\u_tinyriscv.\u_id.$procmux$2753_CMP $auto$opt_reduce.cc:137:opt_pmux$6311 $flatten\u_tinyriscv.\u_id.$procmux$3679_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3691: { $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $flatten\u_tinyriscv.\u_id.$procmux$2856_CMP $flatten\u_tinyriscv.\u_id.$procmux$2753_CMP $flatten\u_tinyriscv.\u_id.$procmux$3693_CMP $auto$opt_reduce.cc:137:opt_pmux$6313 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3702: { $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2856_CMP $flatten\u_tinyriscv.\u_id.$procmux$2753_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3719: { $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $auto$opt_reduce.cc:137:opt_pmux$6315 $flatten\u_tinyriscv.\u_id.$procmux$2713_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3731: { $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $auto$opt_reduce.cc:137:opt_pmux$6317 $flatten\u_tinyriscv.\u_id.$procmux$2713_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3752: { $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2753_CMP $flatten\u_tinyriscv.\u_id.$procmux$3680_CMP $auto$opt_reduce.cc:137:opt_pmux$6319 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1760: $auto$opt_reduce.cc:137:opt_pmux$6321 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1771: $auto$opt_reduce.cc:137:opt_pmux$6323 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_regs.$procmux$2646: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_tinyriscv.\u_regs.$procmux$2646_Y New ports: A=1'0, B=1'1, Y=$flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] New connections: $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [31:1] = { $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2272: { $auto$opt_reduce.cc:137:opt_pmux$6325 $flatten\Controller.\Interpreter.$procmux$1673_CMP } Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_regs.$procmux$2664: Old ports: A=$flatten\u_tinyriscv.\u_regs.$3$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_EN[31:0]$249, B=0, Y=$flatten\u_tinyriscv.\u_regs.$procmux$2664_Y New connections: $flatten\u_tinyriscv.\u_regs.$procmux$2664_Y = 0 New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$6246: { $flatten\u_tinyriscv.\u_ex.$procmux$5263_CMP $flatten\u_tinyriscv.\u_ex.$procmux$5262_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$6248: { $flatten\u_tinyriscv.\u_ex.$procmux$5263_CMP $flatten\u_tinyriscv.\u_ex.$procmux$5262_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$6252: { $flatten\u_tinyriscv.\u_ex.$procmux$5290_CMP $flatten\u_tinyriscv.\u_ex.$procmux$5263_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$6256: { $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$6258: { $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$6260: { $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$6274: { $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [2] $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [0] $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$6276: { $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [2] $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [0] $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$6280: { $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [2] $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [0] $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$6282: { $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [2] $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [0] $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$6284: { $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [2] $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [0] $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1293: Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1067, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1293: Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1067, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] } Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_regs.$procmux$2681: Old ports: A=0, B=$flatten\u_tinyriscv.\u_regs.$2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_EN[31:0]$243, Y=$flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_EN[31:0]$227 New connections: $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_EN[31:0]$227 = 0 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_regs.$procmux$2690: Old ports: A=0, B=$flatten\u_tinyriscv.\u_regs.$2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$240, Y=$flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 New ports: A=1'0, B=$flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0], Y=$flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] New connections: $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [31:1] = { $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$224 [0] } Optimizing cells in module \processorci_top. Performed a total of 96 changes. 24.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~210 debug messages> Removed a total of 70 cells. 24.11.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6109 ($dff) from module processorci_top. Setting constant 0-bit at position 1 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6109 ($dff) from module processorci_top. Setting constant 0-bit at position 2 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6109 ($dff) from module processorci_top. Setting constant 0-bit at position 3 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6109 ($dff) from module processorci_top. Setting constant 0-bit at position 4 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6109 ($dff) from module processorci_top. Setting constant 0-bit at position 5 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6109 ($dff) from module processorci_top. Setting constant 0-bit at position 6 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6109 ($dff) from module processorci_top. Setting constant 0-bit at position 7 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6109 ($dff) from module processorci_top. 24.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 3 unused cells and 1140 unused wires. <suppressed ~16 debug messages> 24.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~3 debug messages> 24.11.9. Rerunning OPT passes. (Maybe there is more to do..) 24.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_csr_reg.$ternary$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:58$30. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_csr_reg.$ternary$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:58$30. Removed 2 multiplexer ports. <suppressed ~201 debug messages> 24.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1886: { $auto$opt_reduce.cc:137:opt_pmux$6237 $auto$opt_reduce.cc:137:opt_pmux$6327 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2033: { $auto$opt_reduce.cc:137:opt_pmux$6237 $auto$opt_reduce.cc:137:opt_pmux$6329 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2322: { $auto$opt_reduce.cc:137:opt_pmux$6203 $flatten\Controller.\Interpreter.$procmux$1740_CMP $flatten\Controller.\Interpreter.$procmux$1659_CMP $auto$opt_reduce.cc:137:opt_pmux$6331 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_div.$procmux$5670: { $flatten\u_tinyriscv.\u_div.$procmux$5467_CMP $auto$opt_reduce.cc:137:opt_pmux$6333 $flatten\u_tinyriscv.\u_div.$procmux$5553_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_div.$procmux$5702: { $flatten\u_tinyriscv.\u_div.$procmux$5467_CMP $auto$opt_reduce.cc:137:opt_pmux$6335 $flatten\u_tinyriscv.\u_div.$procmux$5553_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5444: $auto$opt_reduce.cc:137:opt_pmux$6337 Optimizing cells in module \processorci_top. Performed a total of 6 changes. 24.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 24.11.13. Executing OPT_DFF pass (perform DFF optimizations). 24.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 9 unused wires. <suppressed ~4 debug messages> 24.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.11.16. Rerunning OPT passes. (Maybe there is more to do..) 24.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~201 debug messages> 24.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.11.20. Executing OPT_DFF pass (perform DFF optimizations). 24.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.11.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.11.23. Finished OPT passes. (There is nothing left to do.) 24.12. Executing FSM pass (extract and optimize FSM). 24.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking processorci_top.Controller.Interpreter.return_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state. Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking processorci_top.Controller.Uart.state_read as FSM state register: Register has an initialization value. Not marking processorci_top.Controller.Uart.state_write as FSM state register: Register has an initialization value. Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state. Not marking processorci_top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. Not marking processorci_top.u_tinyriscv.u_clint.cause as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.u_tinyriscv.u_clint.csr_state. Not marking processorci_top.u_tinyriscv.u_clint.waddr_o as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.u_tinyriscv.u_div.state. 24.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$6038 root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1214_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1227_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1240_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1226_Y found state code: 3'000 found ctrl input: \Controller.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \Controller.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1240_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1231_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1227_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1226_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1214_Y ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done } ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1214_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1226_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1227_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1231_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1240_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'00-- -> 3'001 8'01010001 transition: 3'000 4'01-- -> 3'000 8'01010000 transition: 3'000 4'1--- -> 3'000 8'01010000 transition: 3'010 4'0--0 -> 3'010 8'00100010 transition: 3'010 4'0--1 -> 3'011 8'00100011 transition: 3'010 4'1--- -> 3'000 8'00100000 transition: 3'001 4'0-0- -> 3'001 8'00011001 transition: 3'001 4'0-1- -> 3'010 8'00011010 transition: 3'001 4'1--- -> 3'000 8'00011000 transition: 3'011 4'0-0- -> 3'011 8'10010011 transition: 3'011 4'0-1- -> 3'000 8'10010000 transition: 3'011 4'1--- -> 3'000 8'10010000 Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Controller.\Uart.$procdff$6085 root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\Controller.\Uart.$procmux$2353_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2348_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2355_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2342_CMP found state code: 2'00 found state code: 2'11 found state code: 2'10 found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1100_Y found state code: 2'01 found ctrl output: $flatten\Controller.\Uart.$procmux$2342_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2348_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2353_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2355_CMP ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1100_Y } ctrl outputs: { $flatten\Controller.\Uart.$procmux$2355_CMP $flatten\Controller.\Uart.$procmux$2353_CMP $flatten\Controller.\Uart.$procmux$2348_CMP $flatten\Controller.\Uart.$procmux$2342_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] } transition: 2'00 2'00 -> 2'00 6'000100 transition: 2'00 2'01 -> 2'01 6'000101 transition: 2'00 2'1- -> 2'00 6'000100 transition: 2'10 2'0- -> 2'11 6'001011 transition: 2'10 2'1- -> 2'00 6'001000 transition: 2'01 2'0- -> 2'10 6'100010 transition: 2'01 2'1- -> 2'00 6'100000 transition: 2'11 2'0- -> 2'00 6'010000 transition: 2'11 2'1- -> 2'00 6'010000 Extracting FSM `\u_tinyriscv.u_clint.csr_state' from module `\processorci_top'. found $dff cell for state register: $flatten\u_tinyriscv.\u_clint.$procdff$6145 root of input selection tree: $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] found reset state: 5'00001 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found state code: 5'00001 found ctrl input: $flatten\u_tinyriscv.\u_clint.$procmux$5897_CMP found ctrl input: $flatten\u_tinyriscv.\u_clint.$procmux$5899_CMP found ctrl input: $flatten\u_tinyriscv.\u_clint.$procmux$5937_CMP found state code: 5'10000 found state code: 5'00010 found ctrl input: $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:120$17_Y found ctrl input: $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:140$20_Y found ctrl input: $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:153$24_Y found state code: 5'01000 found state code: 5'00100 found ctrl output: $flatten\u_tinyriscv.\u_clint.$ne$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:85$2_Y found ctrl output: $flatten\u_tinyriscv.\u_clint.$procmux$5882_CMP found ctrl output: $flatten\u_tinyriscv.\u_clint.$procmux$5883_CMP found ctrl output: $flatten\u_tinyriscv.\u_clint.$procmux$5897_CMP found ctrl output: $flatten\u_tinyriscv.\u_clint.$procmux$5899_CMP found ctrl output: $flatten\u_tinyriscv.\u_clint.$procmux$5937_CMP ctrl inputs: { $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:153$24_Y $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:140$20_Y $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:120$17_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\u_tinyriscv.\u_clint.$procmux$5937_CMP $flatten\u_tinyriscv.\u_clint.$procmux$5899_CMP $flatten\u_tinyriscv.\u_clint.$procmux$5897_CMP $flatten\u_tinyriscv.\u_clint.$procmux$5883_CMP $flatten\u_tinyriscv.\u_clint.$procmux$5882_CMP $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] $flatten\u_tinyriscv.\u_clint.$ne$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:85$2_Y } transition: 5'10000 4'---0 -> 5'00001 11'00010000011 transition: 5'10000 4'---1 -> 5'00001 11'00010000011 transition: 5'01000 4'---0 -> 5'00001 11'00001000011 transition: 5'01000 4'---1 -> 5'00001 11'00001000011 transition: 5'00100 4'---0 -> 5'00001 11'01000000011 transition: 5'00100 4'---1 -> 5'00010 11'01000000101 transition: 5'00010 4'---0 -> 5'00001 11'00100000011 transition: 5'00010 4'---1 -> 5'10000 11'00100100001 transition: 5'00001 4'---0 -> 5'00001 11'10000000010 transition: 5'00001 4'0001 -> 5'00001 11'10000000010 transition: 5'00001 4'1001 -> 5'01000 11'10000010000 transition: 5'00001 4'-101 -> 5'00100 11'10000001000 transition: 5'00001 4'--11 -> 5'00100 11'10000001000 Extracting FSM `\u_tinyriscv.u_div.state' from module `\processorci_top'. found $dff cell for state register: $flatten\u_tinyriscv.\u_div.$procdff$6127 root of input selection tree: $flatten\u_tinyriscv.\u_div.$0\state[3:0] found reset state: 4'0001 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found state code: 4'0001 found ctrl input: $flatten\u_tinyriscv.\u_div.$procmux$5553_CMP found ctrl input: $flatten\u_tinyriscv.\u_div.$procmux$5479_CMP found ctrl input: $flatten\u_tinyriscv.\u_div.$procmux$5467_CMP found ctrl input: $flatten\u_tinyriscv.\u_div.$procmux$5571_CMP found ctrl input: \u_tinyriscv.u_clint.div_started_i found ctrl input: $flatten\u_tinyriscv.\u_div.$procmux$5475_CMP found state code: 4'1000 found ctrl input: $flatten\u_tinyriscv.\u_div.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:110$68_Y found state code: 4'0100 found state code: 4'0010 found ctrl output: $flatten\u_tinyriscv.\u_div.$procmux$5467_CMP found ctrl output: $flatten\u_tinyriscv.\u_div.$procmux$5479_CMP found ctrl output: $flatten\u_tinyriscv.\u_div.$procmux$5553_CMP found ctrl output: $flatten\u_tinyriscv.\u_div.$procmux$5571_CMP ctrl inputs: { \u_tinyriscv.u_clint.div_started_i $flatten\u_tinyriscv.\u_div.$procmux$5475_CMP $flatten\u_tinyriscv.\u_div.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:110$68_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\u_tinyriscv.\u_div.$procmux$5571_CMP $flatten\u_tinyriscv.\u_div.$procmux$5553_CMP $flatten\u_tinyriscv.\u_div.$procmux$5479_CMP $flatten\u_tinyriscv.\u_div.$procmux$5467_CMP $flatten\u_tinyriscv.\u_div.$0\state[3:0] } transition: 4'1000 4'---0 -> 4'0001 8'01000001 transition: 4'1000 4'---1 -> 4'0001 8'01000001 transition: 4'0100 4'---0 -> 4'0001 8'00100001 transition: 4'0100 4'0--1 -> 4'0001 8'00100001 transition: 4'0100 4'10-1 -> 4'1000 8'00101000 transition: 4'0100 4'11-1 -> 4'0100 8'00100100 transition: 4'0010 4'---0 -> 4'0001 8'00010001 transition: 4'0010 4'0--1 -> 4'0001 8'00010001 transition: 4'0010 4'1-01 -> 4'0100 8'00010100 transition: 4'0010 4'1-11 -> 4'0001 8'00010001 transition: 4'0001 4'---0 -> 4'0001 8'10000001 transition: 4'0001 4'0--1 -> 4'0001 8'10000001 transition: 4'0001 4'1--1 -> 4'0010 8'10000010 24.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\u_tinyriscv.u_div.state$6359' from module `\processorci_top'. Merging pattern 4'---0 and 4'---1 from group (0 3 8'01000001). Merging pattern 4'---1 and 4'---0 from group (0 3 8'01000001). Optimizing FSM `$fsm$\u_tinyriscv.u_clint.csr_state$6351' from module `\processorci_top'. Merging pattern 4'---0 and 4'---1 from group (0 4 11'00010000011). Merging pattern 4'---1 and 4'---0 from group (0 4 11'00010000011). Merging pattern 4'---0 and 4'---1 from group (1 4 11'00001000011). Merging pattern 4'---1 and 4'---0 from group (1 4 11'00001000011). Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6345' from module `\processorci_top'. Merging pattern 2'0- and 2'1- from group (3 0 6'010000). Merging pattern 2'1- and 2'0- from group (3 0 6'010000). Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6338' from module `\processorci_top'. 24.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 39 unused cells and 39 unused wires. <suppressed ~40 debug messages> 24.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6338' from module `\processorci_top'. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6345' from module `\processorci_top'. Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0]. Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1]. Removing unused output signal $flatten\Controller.\Uart.$procmux$2353_CMP. Removing unused output signal $flatten\Controller.\Uart.$procmux$2355_CMP. Optimizing FSM `$fsm$\u_tinyriscv.u_clint.csr_state$6351' from module `\processorci_top'. Removing unused output signal $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] [0]. Removing unused output signal $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] [1]. Removing unused output signal $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] [2]. Removing unused output signal $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] [3]. Removing unused output signal $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] [4]. Optimizing FSM `$fsm$\u_tinyriscv.u_div.state$6359' from module `\processorci_top'. Removing unused output signal $flatten\u_tinyriscv.\u_div.$0\state[3:0] [0]. Removing unused output signal $flatten\u_tinyriscv.\u_div.$0\state[3:0] [1]. Removing unused output signal $flatten\u_tinyriscv.\u_div.$0\state[3:0] [2]. Removing unused output signal $flatten\u_tinyriscv.\u_div.$0\state[3:0] [3]. 24.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6338' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6345' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- Recoding FSM `$fsm$\u_tinyriscv.u_clint.csr_state$6351' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 10000 -> ---1- 01000 -> --1-- 00100 -> -1--- 00010 -> 1---- 00001 -> ----1 Recoding FSM `$fsm$\u_tinyriscv.u_div.state$6359' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 1000 -> --1- 0100 -> -1-- 0010 -> 1--- 0001 -> ---1 24.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6338' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$6338 (\Controller.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \Controller.Uart.i_uart_rx.payload_done 1: \Controller.Uart.i_uart_rx.next_bit 2: \Controller.Uart.i_uart_rx.rxd_reg 3: \ResetBootSystem.reset_o Output signals: 0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1240_Y 1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1231_Y 2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1227_Y 3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1226_Y 4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1214_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'01-- -> 0 5'01010 1: 0 4'1--- -> 0 5'01010 2: 0 4'00-- -> 2 5'01010 3: 1 4'1--- -> 0 5'00100 4: 1 4'0--0 -> 1 5'00100 5: 1 4'0--1 -> 3 5'00100 6: 2 4'1--- -> 0 5'00011 7: 2 4'0-1- -> 1 5'00011 8: 2 4'0-0- -> 2 5'00011 9: 3 4'0-1- -> 0 5'10010 10: 3 4'1--- -> 0 5'10010 11: 3 4'0-0- -> 3 5'10010 ------------------------------------- FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6345' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$6345 (\Controller.Uart.tx_fifo_read_state): Number of input signals: 2 Number of output signals: 2 Number of state bits: 4 Input signals: 0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1100_Y 1: \ResetBootSystem.reset_o Output signals: 0: $flatten\Controller.\Uart.$procmux$2342_CMP 1: $flatten\Controller.\Uart.$procmux$2348_CMP State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 2'00 -> 0 2'01 1: 0 2'1- -> 0 2'01 2: 0 2'01 -> 2 2'01 3: 1 2'1- -> 0 2'10 4: 1 2'0- -> 3 2'10 5: 2 2'1- -> 0 2'00 6: 2 2'0- -> 1 2'00 7: 3 2'-- -> 0 2'00 ------------------------------------- FSM `$fsm$\u_tinyriscv.u_clint.csr_state$6351' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\u_tinyriscv.u_clint.csr_state$6351 (\u_tinyriscv.u_clint.csr_state): Number of input signals: 4 Number of output signals: 6 Number of state bits: 5 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:120$17_Y 2: $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:140$20_Y 3: $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:153$24_Y Output signals: 0: $flatten\u_tinyriscv.\u_clint.$ne$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:85$2_Y 1: $flatten\u_tinyriscv.\u_clint.$procmux$5882_CMP 2: $flatten\u_tinyriscv.\u_clint.$procmux$5883_CMP 3: $flatten\u_tinyriscv.\u_clint.$procmux$5897_CMP 4: $flatten\u_tinyriscv.\u_clint.$procmux$5899_CMP 5: $flatten\u_tinyriscv.\u_clint.$procmux$5937_CMP State encoding: 0: 5'---1- 1: 5'--1-- 2: 5'-1--- 3: 5'1---- 4: 5'----1 <RESET STATE> Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'---- -> 4 6'000101 1: 1 4'---- -> 4 6'000011 2: 2 4'---1 -> 3 6'010001 3: 2 4'---0 -> 4 6'010001 4: 3 4'---1 -> 0 6'001001 5: 3 4'---0 -> 4 6'001001 6: 4 4'1001 -> 1 6'100000 7: 4 4'-101 -> 2 6'100000 8: 4 4'--11 -> 2 6'100000 9: 4 4'---0 -> 4 6'100000 10: 4 4'0001 -> 4 6'100000 ------------------------------------- FSM `$fsm$\u_tinyriscv.u_div.state$6359' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\u_tinyriscv.u_div.state$6359 (\u_tinyriscv.u_div.state): Number of input signals: 4 Number of output signals: 4 Number of state bits: 4 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\u_tinyriscv.\u_div.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:110$68_Y 2: $flatten\u_tinyriscv.\u_div.$procmux$5475_CMP 3: \u_tinyriscv.u_clint.div_started_i Output signals: 0: $flatten\u_tinyriscv.\u_div.$procmux$5467_CMP 1: $flatten\u_tinyriscv.\u_div.$procmux$5479_CMP 2: $flatten\u_tinyriscv.\u_div.$procmux$5553_CMP 3: $flatten\u_tinyriscv.\u_div.$procmux$5571_CMP State encoding: 0: 4'--1- 1: 4'-1-- 2: 4'1--- 3: 4'---1 <RESET STATE> Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'---- -> 3 4'0100 1: 1 4'10-1 -> 0 4'0010 2: 1 4'11-1 -> 1 4'0010 3: 1 4'---0 -> 3 4'0010 4: 1 4'0--1 -> 3 4'0010 5: 2 4'1-01 -> 1 4'0001 6: 2 4'---0 -> 3 4'0001 7: 2 4'1-11 -> 3 4'0001 8: 2 4'0--1 -> 3 4'0001 9: 3 4'1--1 -> 2 4'1000 10: 3 4'---0 -> 3 4'1000 11: 3 4'0--1 -> 3 4'1000 ------------------------------------- 24.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6338' from module `\processorci_top'. Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6345' from module `\processorci_top'. Mapping FSM `$fsm$\u_tinyriscv.u_clint.csr_state$6351' from module `\processorci_top'. Mapping FSM `$fsm$\u_tinyriscv.u_div.state$6359' from module `\processorci_top'. 24.13. Executing OPT pass (performing simple optimizations). 24.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~13 debug messages> 24.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~15 debug messages> Removed a total of 5 cells. 24.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~197 debug messages> 24.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\u_tinyriscv.\u_pc_reg.$procdff$6119 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_pc_reg.$procmux$2702_Y, Q = \u_tinyriscv.u_pc_reg.pc_o, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6494 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_pc_reg.$procmux$2702_Y, Q = \u_tinyriscv.u_pc_reg.pc_o). Adding SRST signal on $flatten\u_tinyriscv.\u_if_id.\inst_ff.$procdff$6112 ($dff) from module processorci_top (D = \Controller.memory_read_data [31:1], Q = \u_tinyriscv.u_if_id.inst_ff.qout_r [31:1], rval = 31'0000000000000000000000000000000). Adding SRST signal on $flatten\u_tinyriscv.\u_if_id.\inst_ff.$procdff$6112 ($dff) from module processorci_top (D = \u_tinyriscv.u_if_id.inst_ff.din [0], Q = \u_tinyriscv.u_if_id.inst_ff.qout_r [0], rval = 1'1). Adding SRST signal on $flatten\u_tinyriscv.\u_if_id.\inst_addr_ff.$procdff$6112 ($dff) from module processorci_top (D = \u_tinyriscv.u_pc_reg.pc_o, Q = \u_tinyriscv.u_if_id.inst_addr_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\reg_we_ff.$procdff$6111 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.reg_we_ff.din, Q = \u_tinyriscv.u_id_ex.reg_we_ff.qout_r, rval = 1'0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\reg_waddr_ff.$procdff$6110 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.reg_waddr_ff.din, Q = \u_tinyriscv.u_id_ex.reg_waddr_ff.qout_r, rval = 5'00000). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\reg2_rdata_ff.$procdff$6112 ($dff) from module processorci_top (D = \u_tinyriscv.u_id.reg2_rdata_i, Q = \u_tinyriscv.u_id_ex.reg2_rdata_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\reg1_rdata_ff.$procdff$6112 ($dff) from module processorci_top (D = \u_tinyriscv.u_id.reg1_rdata_i, Q = \u_tinyriscv.u_id_ex.reg1_rdata_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\op2_jump_ff.$procdff$6112 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.op2_jump_ff.din, Q = \u_tinyriscv.u_id_ex.op2_jump_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\op2_ff.$procdff$6112 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.op2_ff.din, Q = \u_tinyriscv.u_id_ex.op2_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\op1_jump_ff.$procdff$6112 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.op1_jump_ff.din, Q = \u_tinyriscv.u_id_ex.op1_jump_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\op1_ff.$procdff$6112 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.op1_ff.din, Q = \u_tinyriscv.u_id_ex.op1_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\inst_ff.$procdff$6112 ($dff) from module processorci_top (D = \u_tinyriscv.u_if_id.inst_ff.qout_r, Q = \u_tinyriscv.u_id_ex.inst_ff.qout_r, rval = 1). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\csr_we_ff.$procdff$6111 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_id.$10\reg_we_o[0:0], Q = \u_tinyriscv.u_id_ex.csr_we_ff.qout_r, rval = 1'0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\csr_waddr_ff.$procdff$6112 ($dff) from module processorci_top (D = { \u_tinyriscv.id_csr_raddr_o [31:12] \u_tinyriscv.u_csr_reg.raddr_i [11:0] }, Q = \u_tinyriscv.u_id_ex.csr_waddr_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\csr_rdata_ff.$procdff$6112 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.csr_rdata_ff.din, Q = \u_tinyriscv.u_id_ex.csr_rdata_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6132 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5466_Y, Q = \u_tinyriscv.u_div.invert_result, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6521 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5459_Y, Q = \u_tinyriscv.u_div.invert_result). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6131 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5478_Y, Q = \u_tinyriscv.u_div.minuend, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6527 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5478_Y, Q = \u_tinyriscv.u_div.minuend). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6130 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5506_Y, Q = \u_tinyriscv.u_div.div_remain, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6541 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5506_Y, Q = \u_tinyriscv.u_div.div_remain). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6129 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5522_Y, Q = \u_tinyriscv.u_div.div_result, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6555 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5522_Y, Q = \u_tinyriscv.u_div.div_result). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6128 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5538_Y, Q = \u_tinyriscv.u_div.count, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6567 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5538_Y, Q = \u_tinyriscv.u_div.count). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6126 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5581_Y, Q = \u_tinyriscv.u_div.op_r, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$6579 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5579_Y, Q = \u_tinyriscv.u_div.op_r). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6125 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5599_Y, Q = \u_tinyriscv.u_div.divisor_r, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6581 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5599_Y [30:0], Q = \u_tinyriscv.u_div.divisor_r [30:0]). Adding EN signal on $auto$ff.cc:266:slice$6581 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5599_Y [31], Q = \u_tinyriscv.u_div.divisor_r [31]). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6124 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5612_Y, Q = \u_tinyriscv.u_div.dividend_r, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6606 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5612_Y [30:0], Q = \u_tinyriscv.u_div.dividend_r [30:0]). Adding EN signal on $auto$ff.cc:266:slice$6606 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5612_Y [31], Q = \u_tinyriscv.u_div.dividend_r [31]). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6123 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5640_Y, Q = \u_tinyriscv.u_div.reg_waddr_o, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$6635 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5638_Y, Q = \u_tinyriscv.u_div.reg_waddr_o). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6122 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5647_Y, Q = \u_tinyriscv.u_div.busy_o, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6637 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5647_Y, Q = \u_tinyriscv.u_div.busy_o). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6121 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5670_Y, Q = \u_tinyriscv.u_div.ready_o, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6645 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5670_Y, Q = \u_tinyriscv.u_div.ready_o). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6120 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5702_Y, Q = \u_tinyriscv.u_div.result_o, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6655 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5702_Y, Q = \u_tinyriscv.u_div.result_o). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6139 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:70$33_Y, Q = \u_tinyriscv.u_csr_reg.cycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6138 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5782_Y, Q = \u_tinyriscv.u_csr_reg.mscratch, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6666 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5782_Y, Q = \u_tinyriscv.u_csr_reg.mscratch). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6137 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5796_Y, Q = \u_tinyriscv.u_csr_reg.mstatus, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6676 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5796_Y, Q = \u_tinyriscv.u_csr_reg.mstatus). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6136 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5812_Y, Q = \u_tinyriscv.u_csr_reg.mie, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6686 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5812_Y, Q = \u_tinyriscv.u_csr_reg.mie). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6135 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5830_Y, Q = \u_tinyriscv.u_csr_reg.mepc, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6696 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5830_Y, Q = \u_tinyriscv.u_csr_reg.mepc). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6134 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5850_Y, Q = \u_tinyriscv.u_csr_reg.mcause, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6706 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5850_Y, Q = \u_tinyriscv.u_csr_reg.mcause). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6133 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5872_Y, Q = \u_tinyriscv.u_csr_reg.mtvec, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6716 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5872_Y, Q = \u_tinyriscv.u_csr_reg.mtvec). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6147 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5936_Y, Q = \u_tinyriscv.u_clint.cause, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6726 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y, Q = \u_tinyriscv.u_clint.cause). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6146 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5961_Y, Q = \u_tinyriscv.u_clint.inst_addr, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6732 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5959_Y, Q = \u_tinyriscv.u_clint.inst_addr). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6144 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5895_Y, Q = \u_tinyriscv.u_clint.data_o, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6143 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5904_Y, Q = \u_tinyriscv.u_clint.waddr_o, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6142 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5913_Y, Q = \u_tinyriscv.u_clint.we_o, rval = 1'0). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6141 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5888_Y, Q = \u_tinyriscv.u_clint.int_assert_o, rval = 1'0). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6140 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5881_Y, Q = \u_tinyriscv.u_clint.int_addr_o, rval = 0). Adding EN signal on $flatten\ResetBootSystem.$procdff$6108 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$6107 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6050 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1564_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1558_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1549_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1540_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1531_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1522_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1504_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1513_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6759 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$6759 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1558_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1549_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1540_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1531_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1522_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1504_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1513_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6048 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1480_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6764 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1480_Y, Q = \Controller.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6047 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1469_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$6770 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1194_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6046 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6045 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1458_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$6775 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1458_Y, Q = \Controller.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6044 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1447_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6781 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6042 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1424_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1415_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1406_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1397_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1388_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1379_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1361_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1370_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6783 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6041 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1343_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6787 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1234_Y, Q = \Controller.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6040 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1338_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6791 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6039 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1330_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$6793 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1245_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6037 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6036 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$6035 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1307_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6799 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1054_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr). Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$6034 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1051_DATA, Q = \Controller.Uart.TX_FIFO.read_data). Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$6030 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1302_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6806 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1070_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr). Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$6035 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1307_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6808 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1054_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr). Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$6034 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1051_DATA, Q = \Controller.Uart.RX_FIFO.read_data). Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$6030 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1302_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6815 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1070_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6098 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2478_Y, Q = \Controller.Uart.state_read, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6817 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2478_Y, Q = \Controller.Uart.state_read). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6097 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2503_Y, Q = \Controller.Uart.counter_read, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$6821 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2503_Y, Q = \Controller.Uart.counter_read). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6096 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2467_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6095 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2518_Y, Q = \Controller.Uart.read_data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6838 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2516_Y, Q = \Controller.Uart.read_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6094 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2456_Y, Q = \Controller.Uart.read_response, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6093 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2400_Y, Q = \Controller.Uart.state_write, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6845 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2400_Y, Q = \Controller.Uart.state_write). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6092 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2422_Y, Q = \Controller.Uart.counter_write, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$6849 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2422_Y, Q = \Controller.Uart.counter_write). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6091 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2436_Y, Q = \Controller.Uart.write_data_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6859 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2436_Y, Q = \Controller.Uart.write_data_buffer). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6090 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2450_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6869 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6089 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2382_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6088 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2392_Y, Q = \Controller.Uart.write_response, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6087 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2373_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6883 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6086 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2368_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6084 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2363_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6886 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6083 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2339_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6082 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2347_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6081 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1886_Y, Q = \Controller.Interpreter.temp_buffer). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6080 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1929_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6903 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1929_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]). Adding EN signal on $auto$ff.cc:266:slice$6903 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1929_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6079 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1939_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6918 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1939_Y, Q = \Controller.Interpreter.timeout_counter). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6078 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6077 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1980_Y, Q = \Controller.Interpreter.read_buffer). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6076 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2008_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6934 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6075 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2033_Y, Q = \Controller.Interpreter.num_of_positions). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6074 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2055_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6945 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6073 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2061_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6947 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2061_Y, Q = \Controller.Interpreter.return_state). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6072 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2085_Y, Q = \Controller.Interpreter.memory_page_number). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6071 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2093_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6962 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2093_Y, Q = \Controller.Interpreter.memory_mux_selector). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6070 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2133_Y, Q = \Controller.Interpreter.end_position, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6966 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2133_Y, Q = \Controller.Interpreter.end_position). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6068 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2175_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6970 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2175_Y, Q = \Controller.Interpreter.bus_mode). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6067 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1714_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6066 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2186_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6065 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1819_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6064 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2196_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6983 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2196_Y, Q = \Controller.Interpreter.core_clk_enable). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6063 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6062 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1838_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6061 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1861_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6060 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1738_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6059 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1760_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6058 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1771_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6057 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2272_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$7001 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2272_Y, Q = \Controller.Interpreter.counter). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6056 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2296_Y, Q = \Controller.Interpreter.write_data). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6055 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2322_Y, Q = \Controller.Interpreter.address). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6054 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1614_Y, Q = \Controller.Interpreter.state, rval = 8'00000000). Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$6051 ($dff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1588_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$7022 ($sdff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1588_Y, Q = \Controller.ClkDivider.pulse_counter). Adding SRST signal on $flatten\Controller.$procdff$6105 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2539_Y, Q = \Controller.finish_execution, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$7030 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2539_Y, Q = \Controller.finish_execution). Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. 24.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 175 unused cells and 202 unused wires. <suppressed ~180 debug messages> 24.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~47 debug messages> 24.13.9. Rerunning OPT passes. (Maybe there is more to do..) 24.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~164 debug messages> 24.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$6789: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] } Optimizing cells in module \processorci_top. Performed a total of 1 changes. 24.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~186 debug messages> Removed a total of 62 cells. 24.13.13. Executing OPT_DFF pass (perform DFF optimizations). 24.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 63 unused wires. <suppressed ~2 debug messages> 24.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.13.16. Rerunning OPT passes. (Maybe there is more to do..) 24.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~166 debug messages> 24.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.13.20. Executing OPT_DFF pass (perform DFF optimizations). 24.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.13.23. Finished OPT passes. (There is nothing left to do.) 24.14. Executing WREDUCE pass (reducing word size of cells). Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$6149 (Controller.Data_Memory.memory). Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$861 (Controller.Data_Memory.memory). Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$6149 (Controller.Memory.memory). Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$861 (Controller.Memory.memory). Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$6148 (Controller.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1051 (Controller.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$6148 (Controller.Uart.TX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1051 (Controller.Uart.TX_FIFO.memory). Removed top 3 bits (of 4) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6459 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6497 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6492 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6385 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1152 ($gt). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1109 ($eq). Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1113 ($add). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1116 ($add). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1125 ($lt). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1130 ($eq). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1132 ($ge). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1615_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1616_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1618 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1620_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1621_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1622_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1623_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1624_CMP0 ($eq). Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1626 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1628_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1629_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1631 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1633_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1634_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1638_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1639_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1640_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1642 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1644_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1645_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1646_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1648 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1650_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1652 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1654_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1655_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1656_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1657_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1658_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1659_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1660_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1662 ($mux). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1664_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1666 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1668_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1669_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1671 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1673_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1674_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1677_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1676 ($pmux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1678_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1679_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1680_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1681_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1682_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1683_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1684_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1685_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1686_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1687_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1688_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1689_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1690_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1691_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1692_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1693_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1694_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1695_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1696_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1697_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1698_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1699_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1700_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1702 ($mux). Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1704_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1706 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1740_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1741_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1742_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1775_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1930_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1931_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1932_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1975_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2101_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2134_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2135_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2208_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2209_CMP0 ($eq). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$1083 ($lt). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1088 ($lt). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2387_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2393_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2394_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2406_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2408 ($mux). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2457_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2458_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2472_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2480_CMP0 ($eq). Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2488 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1299 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1287 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071 ($sub). Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071 ($sub). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1070 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1068 ($eq). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1054 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1052 ($eq). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1299 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1287 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071 ($sub). Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071 ($sub). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1070 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1068 ($eq). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1054 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1052 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1222 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1221 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1220 ($mux). Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1215 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1213 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1189 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1181 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1179 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1176 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1175 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1171 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1166 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1165 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1164 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1163 ($mux). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1159 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1157 ($eq). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2530 ($mux). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2530 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$838 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:90$828 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$822 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$821 ($mux). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6699 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6399 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6709 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6719 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6749 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$7025 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$7035 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6669 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6679 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6689 ($ne). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_div.$ternary$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:67$62 ($mux). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6424 ($eq). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_div.$procmux$5483 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_div.$procmux$5485 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:134$92 ($add). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:135$94 ($add). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:144$100 ($add). Removed top 30 bits (of 32) from port Y of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:146$101 ($add). Removed top 30 bits (of 32) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:146$101 ($add). Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:146$101 ($add). Removed top 30 bits (of 32) from port Y of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:147$103 ($add). Removed top 30 bits (of 32) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:147$103 ($add). Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:147$103 ($add). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127 ($eq). Removed top 6 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$128 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$158 ($eq). Removed top 27 bits (of 32) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:843$202 ($or). Removed top 27 bits (of 32) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$not$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:847$203 ($not). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$3773_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$3774_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$4010_CMP0 ($eq). Removed top 16 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$4148 ($mux). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$4153_CMP0 ($eq). Removed top 24 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$4165 ($pmux). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$4167_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP0 ($eq). Removed top 3 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$5262_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$5290_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$5290_CMP1 ($eq). Removed top 20 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$6519 ($sdff). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:105$207 ($eq). Removed top 6 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:122$209 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$2711_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$2711_CMP1 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$2711_CMP2 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$2856_CMP0 ($eq). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$2939_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6374 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$3035_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$3593_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$3679_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$3693_CMP0 ($eq). Removed top 3 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$3745_CMP0 ($eq). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$3759 ($mux). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5761_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5762_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5763_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5764_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5765_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5766_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5776_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5781_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5789_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5795_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5804_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5811_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5821_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5829_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5840_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5849_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5861_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5871_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_pc_reg.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:43$217 ($ge). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_pc_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:47$218 ($add). Removed top 25 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:93$7 ($eq). Removed top 11 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:93$8 ($eq). Removed top 2 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:102$14 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:120$17 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:124$19 ($sub). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:140$20 ($eq). Removed top 20 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$6739 ($sdff). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:148$23 ($sub). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_clint.$procmux$5904 ($pmux). Removed top 28 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_clint.$procmux$5931 ($pmux). Removed top 2 bits (of 4) from mux cell processorci_top.$flatten\u_tinyriscv.\u_clint.$procmux$6007 ($mux). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id_ex.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v:57$210 ($ge). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_if_id.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v:38$211 ($ge). Removed top 1 bits (of 3) from mux cell processorci_top.$flatten\u_tinyriscv.\u_ctrl.$procmux$5741 ($mux). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$ne$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:85$1 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2556_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$808 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$807 ($add). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$807 ($add). Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$806 ($lt). Removed top 2 bits (of 12) from FF cell processorci_top.$auto$ff.cc:266:slice$6739 ($sdff). Removed top 2 bits (of 12) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5776_CMP0 ($eq). Removed top 2 bits (of 12) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5789_CMP0 ($eq). Removed top 2 bits (of 12) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5804_CMP0 ($eq). Removed top 2 bits (of 12) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5821_CMP0 ($eq). Removed top 2 bits (of 12) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5840_CMP0 ($eq). Removed top 2 bits (of 12) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5861_CMP0 ($eq). Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$821_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_ADDR[31:0]$865. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1618_Y. Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1626_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1631_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1642_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1648_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1652_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1662_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1666_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1671_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1676_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1702_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1706_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$859_ADDR[31:0]$865. Removed top 2 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$861_DATA. Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2408_Y. Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2488_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR[5:0]$1056. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR[5:0]$1065. Removed top 3 bits (of 8) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_DATA[7:0]$1066. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1070_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR[5:0]$1056. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR[5:0]$1065. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1054_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1070_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1163_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1164_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1165_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1166_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$807_Y. Removed top 2 bits (of 4) from wire processorci_top.$flatten\u_tinyriscv.\u_clint.$3\int_state[3:0]. Removed top 22 bits (of 32) from wire processorci_top.$flatten\u_tinyriscv.\u_clint.$procmux$5904_Y. Removed top 28 bits (of 32) from wire processorci_top.$flatten\u_tinyriscv.\u_clint.$procmux$5931_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\u_tinyriscv.\u_div.$procmux$5483_Y. Removed top 24 bits (of 32) from wire processorci_top.$flatten\u_tinyriscv.\u_ex.$15\reg_wdata[31:0]. Removed top 16 bits (of 32) from wire processorci_top.$flatten\u_tinyriscv.\u_ex.$16\reg_wdata[31:0]. Removed top 31 bits (of 32) from wire processorci_top.$flatten\u_tinyriscv.\u_ex.$and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:275$144_Y. Removed top 31 bits (of 32) from wire processorci_top.core_read_data. 24.15. Executing PEEPOPT pass (run peephole optimizers). 24.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 45 unused wires. <suppressed ~1 debug messages> 24.17. Executing SHARE pass (SAT-based resource sharing). Found 11 cells in module processorci_top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\u_tinyriscv.\u_regs.$memrd$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:86$261 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y }. Found 1 candidates: $flatten\u_tinyriscv.\u_regs.$memrd$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:74$255 Analyzing resource sharing with $flatten\u_tinyriscv.\u_regs.$memrd$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:74$255 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y }. Activation pattern for cell $flatten\u_tinyriscv.\u_regs.$memrd$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:86$261: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y } = 2'00 Activation pattern for cell $flatten\u_tinyriscv.\u_regs.$memrd$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:74$255: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y } = 2'00 Size of SAT problem: 0 cells, 1087 variables, 2923 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y } = 4'0000 Analyzing resource sharing options for $flatten\u_tinyriscv.\u_regs.$memrd$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:74$255 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y }. No candidates found. Analyzing resource sharing options for $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:129$88 ($shr): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset }. Found 3 candidates: $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:128$87 $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$86 $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$85 Analyzing resource sharing with $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:128$87 ($shr): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset }. Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:129$88: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 5'10111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:129$88: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 5'10111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:129$88: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset } = 5'11111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:128$87: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset } = 6'111111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:128$87: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } = 6'101111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:128$87: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } = 6'101111 Size of SAT problem: 0 cells, 1170 variables, 3198 clauses According to the SAT solver this pair of cells can be shared. Activation signal for $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:129$88: $auto$share.cc:987:make_cell_activation_logic$7086 New cell: $auto$share.cc:667:make_supercell$7093 ($shr) Analyzing resource sharing options for $auto$share.cc:667:make_supercell$7093 ($shr): Found 6 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset }. Found 2 candidates: $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$86 $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$85 Analyzing resource sharing with $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$86 ($shr): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset }. Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 5'10111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 5'10111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset } = 5'11111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset } = 6'111111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } = 6'101111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } = 6'101111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$86: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 4'1011 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$86: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 4'1011 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$86: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset } = 4'1111 Size of SAT problem: 0 cells, 1162 variables, 3173 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset } = 11'10001111100 Analyzing resource sharing with $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$85 ($shr): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset }. Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 5'10111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 5'10111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset } = 5'11111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset } = 6'111111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } = 6'101111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } = 6'101111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$85: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset } = 5'11111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$85: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } = 5'10111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$85: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } = 5'10111 Size of SAT problem: 0 cells, 1162 variables, 3176 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset } = 11'10001101110 Analyzing resource sharing options for $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$86 ($shr): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset }. Found 1 candidates: $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$85 Analyzing resource sharing with $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$85 ($shr): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset }. Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$86: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 4'1011 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$86: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 4'1011 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$86: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset } = 4'1111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$85: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset } = 5'11111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$85: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } = 5'10111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$85: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } = 5'10111 Size of SAT problem: 0 cells, 1170 variables, 3189 clauses According to the SAT solver this pair of cells can be shared. Activation signal for $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$86: $auto$share.cc:987:make_cell_activation_logic$7100 New cell: $auto$share.cc:667:make_supercell$7107 ($shr) Analyzing resource sharing options for $auto$share.cc:667:make_supercell$7107 ($shr): Found 6 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset }. No candidates found. Analyzing resource sharing options for $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:378$162 ($shl): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset }. Found 1 candidates: $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$150 Analyzing resource sharing with $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$150 ($shl): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP \Controller.Interpreter.core_reset }. Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:378$162: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } = 5'10111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:378$162: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y } = 5'10111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:378$162: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset } = 5'11111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$150: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP \Controller.Interpreter.core_reset } = 4'1111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$150: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP } = 4'1011 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$150: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP } = 4'1011 Size of SAT problem: 0 cells, 1171 variables, 3195 clauses According to the SAT solver this pair of cells can be shared. Activation signal for $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$150: $auto$share.cc:987:make_cell_activation_logic$7114 New cell: $auto$share.cc:667:make_supercell$7121 ($shl) Analyzing resource sharing options for $auto$share.cc:667:make_supercell$7121 ($shl): Found 6 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset }. No candidates found. Analyzing resource sharing options for $flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$98 ($mul): Found 12 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$3872_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3774_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3773_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$159_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$128_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$127_Y \Controller.Interpreter.core_reset }. No candidates found. Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$861 ($memrd): Found 1 activation_patterns using ctrl signal \Controller.Memory.memory_read. No candidates found. Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$861 ($memrd): Found 39 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$260_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$257_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$254_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$251_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$237_Y $flatten\u_tinyriscv.\u_ex.$procmux$4167_CMP $flatten\u_tinyriscv.\u_ex.$procmux$4166_CMP $flatten\u_tinyriscv.\u_ex.$procmux$4153_CMP $flatten\u_tinyriscv.\u_ex.$procmux$4010_CMP $flatten\u_tinyriscv.\u_ex.$procmux$4009_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3872_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3870_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3774_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:674$180_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:571$178_Y \Controller.Data_Memory.memory_write \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1658_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector \Controller.Interpreter.core_reset }. No candidates found. Removing 6 cells in module processorci_top: Removing cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$150 ($shl). Removing cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:378$162 ($shl). Removing cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$85 ($shr). Removing cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$86 ($shr). Removing cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:128$87 ($shr). Removing cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:129$88 ($shr). 24.18. Executing TECHMAP pass (map to technology primitives). 24.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/cmp2lut.v Parsing Verilog input from `/usr/local/share/synlig/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 24.18.2. Continuing TECHMAP pass. Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt. Using template $paramod$2b219144165107f7a748973168aee346c2de5671\_90_lut_cmp_ for cells of type $ge. Using template $paramod$47e13f9af9c2f084dc0140c442912baffd5ee164\_90_lut_cmp_ for cells of type $ge. Using template $paramod$3eab19c3b06c9721d9bc60677e7aee18638008e3\_90_lut_cmp_ for cells of type $ge. No more expansions possible. <suppressed ~287 debug messages> 24.19. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~2 debug messages> 24.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 21 unused wires. <suppressed ~7 debug messages> 24.21. Executing TECHMAP pass (map to technology primitives). 24.21.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/mul2dsp.v Parsing Verilog input from `/usr/local/share/synlig/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 24.21.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/dsp_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 24.21.3. Continuing TECHMAP pass. Using template $paramod$550e203a952dbffa6a242dc3ff52d918f7107edc\_80_mul for cells of type $mul. Using template $paramod$20c936a0792f4d1374c5655c28d1183b326ddc16\_80_mul for cells of type $__mul. Using template $paramod$53619bec844f404c540ad98bff25578b57460b55\_80_mul for cells of type $__mul. Using template $paramod$ba1b36458f074a6329f9cad9c8b71be8774bccea\_80_mul for cells of type $__mul. Using template $paramod$6b575be7a871ec606b9b0767ebd93c7f3c2d2c79\_80_mul for cells of type $__mul. Using template $paramod$dea5bd344db76a97cfc2d2ce1e3c016835e6674d\_80_mul for cells of type $__mul. Using template $paramod$2b87aee4ebaafa612245fc7fd7616dd6042fdae6\_80_mul for cells of type $__mul. Using template $paramod$2d2a570e39348c56898214c319f101b20f7da6fb\$__MUL18X18 for cells of type $__MUL18X18. Using template $paramod$8966f1902fe419d84ad9f3abc17827c8390a13bf\$__MUL18X18 for cells of type $__MUL18X18. Using template $paramod$e5ade21dea2c4d51df0cdca72b2a93a08fd8e7d1\$__MUL18X18 for cells of type $__MUL18X18. No more expansions possible. <suppressed ~651 debug messages> 24.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module processorci_top: creating $macc model for $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$98.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/local/share/synlig/mul2dsp.v:230$7142 ($add). creating $macc model for $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$98.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/usr/local/share/synlig/mul2dsp.v:230$7139 ($add). creating $macc model for $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$98.$add$/usr/local/share/synlig/mul2dsp.v:173$7136 ($add). creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1153 ($sub). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1108 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1112 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1113 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1116 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1123 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1127 ($add). creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1115 ($sub). creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1090 ($add). creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1085 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071 ($sub). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053 ($add). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069 ($add). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071 ($sub). creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1234 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1245 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1183 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1194 ($add). creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$807 ($add). creating $macc model for $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:124$19 ($sub). creating $macc model for $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:148$23 ($sub). creating $macc model for $flatten\u_tinyriscv.\u_csr_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:70$33 ($add). creating $macc model for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:190$83 ($neg). creating $macc model for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:196$84 ($neg). creating $macc model for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:63$58 ($neg). creating $macc model for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:64$59 ($neg). creating $macc model for $flatten\u_tinyriscv.\u_div.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:66$61 ($sub). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:131$89 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:132$90 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:134$92 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:135$94 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:144$100 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:146$101 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:147$103 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:367$161 ($sub). creating $macc model for $flatten\u_tinyriscv.\u_pc_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:47$218 ($add). creating $alu model for $macc $flatten\u_tinyriscv.\u_pc_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:47$218. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:367$161. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:147$103. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:146$101. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:144$100. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:135$94. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:134$92. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:132$90. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:131$89. creating $alu model for $macc $flatten\u_tinyriscv.\u_div.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:66$61. creating $alu model for $macc $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:64$59. creating $alu model for $macc $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:63$58. creating $alu model for $macc $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:196$84. creating $alu model for $macc $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:190$83. creating $alu model for $macc $flatten\u_tinyriscv.\u_csr_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:70$33. creating $alu model for $macc $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:148$23. creating $alu model for $macc $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:124$19. creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$807. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1194. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1183. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1245. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1234. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053. creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1085. creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1090. creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1115. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1127. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1123. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1116. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1113. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1112. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1108. creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1153. creating $alu model for $macc $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$98.$add$/usr/local/share/synlig/mul2dsp.v:173$7136. creating $alu model for $macc $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$98.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/usr/local/share/synlig/mul2dsp.v:230$7139. creating $alu model for $macc $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$98.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/local/share/synlig/mul2dsp.v:230$7142. creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1152 ($gt): new $alu creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1132 ($ge): new $alu creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1125 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1132. creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$806 ($lt): new $alu creating $alu model for $flatten\u_tinyriscv.\u_div.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:65$60 ($ge): merged with $flatten\u_tinyriscv.\u_div.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:66$61. creating $alu model for $flatten\u_tinyriscv.\u_ex.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:138$95 ($ge): new $alu creating $alu model for $flatten\u_tinyriscv.\u_ex.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:140$96 ($ge): merged with $flatten\u_tinyriscv.\u_ex.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:367$161. creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1130 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1132. creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$808 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$806. creating $alu model for $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:141$97 ($eq): merged with $flatten\u_tinyriscv.\u_ex.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:367$161. creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$806, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$808: $auto$alumacc.cc:485:replace_alu$7155 creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1132, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1125, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1130: $auto$alumacc.cc:485:replace_alu$7166 creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1152: $auto$alumacc.cc:485:replace_alu$7179 creating $alu cell for $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$98.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/local/share/synlig/mul2dsp.v:230$7142: $auto$alumacc.cc:485:replace_alu$7184 creating $alu cell for $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$98.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/usr/local/share/synlig/mul2dsp.v:230$7139: $auto$alumacc.cc:485:replace_alu$7187 creating $alu cell for $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$98.$add$/usr/local/share/synlig/mul2dsp.v:173$7136: $auto$alumacc.cc:485:replace_alu$7190 creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1153: $auto$alumacc.cc:485:replace_alu$7193 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1108: $auto$alumacc.cc:485:replace_alu$7196 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1112: $auto$alumacc.cc:485:replace_alu$7199 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1113: $auto$alumacc.cc:485:replace_alu$7202 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1116: $auto$alumacc.cc:485:replace_alu$7205 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1123: $auto$alumacc.cc:485:replace_alu$7208 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1127: $auto$alumacc.cc:485:replace_alu$7211 creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1115: $auto$alumacc.cc:485:replace_alu$7214 creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1090: $auto$alumacc.cc:485:replace_alu$7217 creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1085: $auto$alumacc.cc:485:replace_alu$7220 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053: $auto$alumacc.cc:485:replace_alu$7223 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069: $auto$alumacc.cc:485:replace_alu$7226 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071: $auto$alumacc.cc:485:replace_alu$7229 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053: $auto$alumacc.cc:485:replace_alu$7232 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069: $auto$alumacc.cc:485:replace_alu$7235 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071: $auto$alumacc.cc:485:replace_alu$7238 creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1234: $auto$alumacc.cc:485:replace_alu$7241 creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1245: $auto$alumacc.cc:485:replace_alu$7244 creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1183: $auto$alumacc.cc:485:replace_alu$7247 creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1194: $auto$alumacc.cc:485:replace_alu$7250 creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$807: $auto$alumacc.cc:485:replace_alu$7253 creating $alu cell for $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:124$19: $auto$alumacc.cc:485:replace_alu$7256 creating $alu cell for $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:148$23: $auto$alumacc.cc:485:replace_alu$7259 creating $alu cell for $flatten\u_tinyriscv.\u_csr_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:70$33: $auto$alumacc.cc:485:replace_alu$7262 creating $alu cell for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:190$83: $auto$alumacc.cc:485:replace_alu$7265 creating $alu cell for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:196$84: $auto$alumacc.cc:485:replace_alu$7268 creating $alu cell for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:63$58: $auto$alumacc.cc:485:replace_alu$7271 creating $alu cell for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:64$59: $auto$alumacc.cc:485:replace_alu$7274 creating $alu cell for $flatten\u_tinyriscv.\u_div.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:66$61, $flatten\u_tinyriscv.\u_div.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:65$60: $auto$alumacc.cc:485:replace_alu$7277 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:132$90: $auto$alumacc.cc:485:replace_alu$7290 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:134$92: $auto$alumacc.cc:485:replace_alu$7293 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:135$94: $auto$alumacc.cc:485:replace_alu$7296 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:144$100: $auto$alumacc.cc:485:replace_alu$7299 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:146$101: $auto$alumacc.cc:485:replace_alu$7302 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:147$103: $auto$alumacc.cc:485:replace_alu$7305 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:138$95: $auto$alumacc.cc:485:replace_alu$7308 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:131$89: $auto$alumacc.cc:485:replace_alu$7323 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:367$161, $flatten\u_tinyriscv.\u_ex.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:140$96, $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:141$97: $auto$alumacc.cc:485:replace_alu$7326 creating $alu cell for $flatten\u_tinyriscv.\u_pc_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:47$218: $auto$alumacc.cc:485:replace_alu$7339 created 45 $alu and 0 $macc cells. 24.23. Executing OPT pass (performing simple optimizations). 24.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~3 debug messages> 24.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~12 debug messages> Removed a total of 4 cells. 24.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~170 debug messages> 24.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 24.23.6. Executing OPT_DFF pass (perform DFF optimizations). 24.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 68 unused wires. <suppressed ~1 debug messages> 24.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.23.9. Rerunning OPT passes. (Maybe there is more to do..) 24.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~171 debug messages> 24.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.23.13. Executing OPT_DFF pass (perform DFF optimizations). 24.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.23.16. Finished OPT passes. (There is nothing left to do.) 24.24. Executing MEMORY pass. 24.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 1 transformations. 24.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 24.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing processorci_top.Controller.Data_Memory.memory write port 0. Analyzing processorci_top.Controller.Memory.memory write port 0. Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0. Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0. Analyzing processorci_top.u_tinyriscv.u_regs.regs write port 0. 24.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 24.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\u_tinyriscv.u_regs.regs'[0] in module `\processorci_top': no output FF found. Checking read port `\u_tinyriscv.u_regs.regs'[1] in module `\processorci_top': no output FF found. Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found. Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found. Checking read port address `\u_tinyriscv.u_regs.regs'[0] in module `\processorci_top': no address FF found. Checking read port address `\u_tinyriscv.u_regs.regs'[1] in module `\processorci_top': no address FF found. 24.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 2 unused cells and 18 unused wires. <suppressed ~3 debug messages> 24.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory processorci_top.u_tinyriscv.u_regs.regs by address: 24.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 24.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 24.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0] mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0] mapping memory processorci_top.u_tinyriscv.u_regs.regs via $__TRELLIS_DPR16X4_ <suppressed ~1170 debug messages> 24.27. Executing TECHMAP pass (map to technology primitives). 24.27.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/lutrams_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 24.27.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/brams_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 24.27.3. Continuing TECHMAP pass. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~1078 debug messages> 24.28. Executing OPT pass (performing simple optimizations). 24.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~248 debug messages> 24.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~18 debug messages> Removed a total of 6 cells. 24.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\ResetBootSystem.$procdff$6106 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Adding SRST signal on $auto$ff.cc:266:slice$6955 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1127_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6894 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1886_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]). Adding SRST signal on $auto$ff.cc:266:slice$6743 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2553_Y, Q = \ResetBootSystem.counter, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6495 ($sdffe) from module processorci_top (D = $flatten\u_tinyriscv.\u_pc_reg.$procmux$2702_Y [1:0], Q = \u_tinyriscv.u_pc_reg.pc_o [1:0]). 24.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 9 unused cells and 7587 unused wires. <suppressed ~10 debug messages> 24.28.5. Rerunning OPT passes. (Removed registers in this run.) 24.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~5 debug messages> 24.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$9794 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$7073 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). 24.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 5 unused wires. <suppressed ~2 debug messages> 24.28.10. Rerunning OPT passes. (Removed registers in this run.) 24.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.28.13. Executing OPT_DFF pass (perform DFF optimizations). 24.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.28.15. Finished fast OPT passes. 24.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 24.30. Executing OPT pass (performing simple optimizations). 24.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~113 debug messages> 24.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$9792: { $auto$opt_dff.cc:194:make_patterns_logic$9789 $auto$fsm_map.cc:74:implement_pattern_cache$6419 $auto$opt_dff.cc:194:make_patterns_logic$6897 $auto$opt_dff.cc:194:make_patterns_logic$6895 } Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$821: Old ports: A=\u_tinyriscv.u_pc_reg.pc_o [11:0], B={ \Controller.Interpreter.memory_page_number [5:0] \u_tinyriscv.u_pc_reg.pc_o [5:0] }, Y=$auto$wreduce.cc:461:run$7039 [11:0] New ports: A=\u_tinyriscv.u_pc_reg.pc_o [11:6], B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$7039 [11:6] New connections: $auto$wreduce.cc:461:run$7039 [5:0] = \u_tinyriscv.u_pc_reg.pc_o [5:0] Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1626: Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$7042 [2:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$7042 [2] $auto$wreduce.cc:461:run$7042 [0] } New connections: $auto$wreduce.cc:461:run$7042 [1] = $auto$wreduce.cc:461:run$7042 [0] Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1631: Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$7043 [6:0] New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$7043 [1:0] New connections: $auto$wreduce.cc:461:run$7043 [6:2] = { $auto$wreduce.cc:461:run$7043 [1] 3'010 $auto$wreduce.cc:461:run$7043 [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1642: Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$7044 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$7044 [2] New connections: { $auto$wreduce.cc:461:run$7044 [3] $auto$wreduce.cc:461:run$7044 [1:0] } = { $auto$wreduce.cc:461:run$7044 [2] 2'00 } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1652: Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$7046 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$7046 [0] New connections: $auto$wreduce.cc:461:run$7046 [3:1] = { $auto$wreduce.cc:461:run$7046 [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1666: Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$7048 [6:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$7048 [0] New connections: $auto$wreduce.cc:461:run$7048 [6:1] = { $auto$wreduce.cc:461:run$7048 [0] 1'0 $auto$wreduce.cc:461:run$7048 [0] 3'011 } Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2061: Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$2061_Y New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$2061_Y [4:0] New connections: $flatten\Controller.\Interpreter.$procmux$2061_Y [7:5] = 3'000 Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2186: Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2186_Y New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2186_Y [23:0] New connections: $flatten\Controller.\Interpreter.$procmux$2186_Y [31:24] = 8'00000000 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2196: $auto$opt_reduce.cc:137:opt_pmux$6307 Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2400: Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$7055 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2400_Y New ports: A=3'000, B={ $auto$wreduce.cc:461:run$7055 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2400_Y [2:0] New connections: $flatten\Controller.\Uart.$procmux$2400_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2408: Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$7055 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$7055 [2] New connections: $auto$wreduce.cc:461:run$7055 [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2484: Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2484_Y New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2484_Y [2:1] New connections: { $flatten\Controller.\Uart.$procmux$2484_Y [3] $flatten\Controller.\Uart.$procmux$2484_Y [0] } = 2'00 Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1442: Old ports: A=3'000, B={ 2'00 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1220_Y [0] 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1221_Y [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223_Y [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1220_Y [0] $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1221_Y [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223_Y [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223: Old ports: A=2'11, B=2'00, Y=$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223_Y [1:0] New ports: A=1'1, B=1'0, Y=$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223_Y [0] New connections: $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223_Y [1] = $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223_Y [0] Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1579: Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$7070 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$7072 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$7070 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$7072 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1166: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$7072 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$7072 [0] New connections: $auto$wreduce.cc:461:run$7072 [1] = $auto$wreduce.cc:461:run$7072 [0] New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2571: { $flatten\ResetBootSystem.$procmux$2557_CMP $flatten\ResetBootSystem.$procmux$2556_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2574: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2574_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2574_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2574_Y [0] = 1'0 Consolidated identical input bits for $pmux cell $flatten\u_tinyriscv.\u_clint.$procmux$5904: Old ports: A=10'0000000000, B=30'110100000111010000101100000000, Y=$auto$wreduce.cc:461:run$7075 [9:0] New ports: A=4'0000, B=12'110111101000, Y={ $auto$wreduce.cc:461:run$7075 [8] $auto$wreduce.cc:461:run$7075 [6] $auto$wreduce.cc:461:run$7075 [1:0] } New connections: { $auto$wreduce.cc:461:run$7075 [9] $auto$wreduce.cc:461:run$7075 [7] $auto$wreduce.cc:461:run$7075 [5:2] } = { $auto$wreduce.cc:461:run$7075 [8] 5'00000 } Consolidated identical input bits for $pmux cell $flatten\u_tinyriscv.\u_clint.$procmux$5931: Old ports: A=4'1010, B=8'10110011, Y=$auto$wreduce.cc:461:run$7076 [3:0] New ports: A=2'10, B=4'1101, Y={ $auto$wreduce.cc:461:run$7076 [3] $auto$wreduce.cc:461:run$7076 [0] } New connections: $auto$wreduce.cc:461:run$7076 [2:1] = 2'01 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_clint.$procmux$5934: Old ports: A=32'10000000000000000000000000000100, B={ 28'0000000000000000000000000000 $auto$wreduce.cc:461:run$7076 [3:0] }, Y=$flatten\u_tinyriscv.\u_clint.$procmux$5934_Y New ports: A=5'10100, B={ 1'0 $auto$wreduce.cc:461:run$7076 [3:0] }, Y={ $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [31] $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [3:0] } New connections: $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [30:4] = 27'000000000000000000000000000 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_clint.$procmux$5948: Old ports: A=\u_tinyriscv.u_if_id.inst_addr_ff.qout_r, B={ $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:148$23_Y [31:2] \u_tinyriscv.u_if_id.inst_addr_ff.qout_r [1:0] }, Y=$flatten\u_tinyriscv.\u_clint.$procmux$5948_Y New ports: A=\u_tinyriscv.u_if_id.inst_addr_ff.qout_r [31:2], B=$flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:148$23_Y [31:2], Y=$flatten\u_tinyriscv.\u_clint.$procmux$5948_Y [31:2] New connections: $flatten\u_tinyriscv.\u_clint.$procmux$5948_Y [1:0] = \u_tinyriscv.u_if_id.inst_addr_ff.qout_r [1:0] Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_clint.$procmux$5985: Old ports: A=4'0001, B=4'1000, Y=$flatten\u_tinyriscv.\u_clint.$4\int_state[3:0] New ports: A=2'01, B=2'10, Y={ $flatten\u_tinyriscv.\u_clint.$4\int_state[3:0] [3] $flatten\u_tinyriscv.\u_clint.$4\int_state[3:0] [0] } New connections: $flatten\u_tinyriscv.\u_clint.$4\int_state[3:0] [2:1] = 2'00 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_ctrl.$procmux$5741: Old ports: A=2'00, B=2'11, Y=\u_tinyriscv.u_id_ex.hold_flag_i [1:0] New ports: A=1'0, B=1'1, Y=\u_tinyriscv.u_id_ex.hold_flag_i [0] New connections: \u_tinyriscv.u_id_ex.hold_flag_i [1] = \u_tinyriscv.u_id_ex.hold_flag_i [0] Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_div.$procmux$5538: Old ports: A=1073741824, B={ 1'0 \u_tinyriscv.u_div.count [31:1] }, Y=$flatten\u_tinyriscv.\u_div.$procmux$5538_Y New ports: A=31'1000000000000000000000000000000, B=\u_tinyriscv.u_div.count [31:1], Y=$flatten\u_tinyriscv.\u_div.$procmux$5538_Y [30:0] New connections: $flatten\u_tinyriscv.\u_div.$procmux$5538_Y [31] = 1'0 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_div.$procmux$5647: { \u_tinyriscv.u_div.state [3] $auto$opt_reduce.cc:137:opt_pmux$9807 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_div.$procmux$5670: $auto$opt_reduce.cc:137:opt_pmux$6333 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_ex.$procmux$4186: Old ports: A={ \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31:16] }, B={ \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15:0] }, Y=$flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] New ports: A=\u_tinyriscv.u_ex.mem_rdata_i [31:16], B=\u_tinyriscv.u_ex.mem_rdata_i [15:0], Y=$flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15:0] New connections: $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [31:16] = { $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] } Consolidated identical input bits for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4206: Old ports: A={ \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31:24] }, B={ \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7:0] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15:8] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23:16] }, Y=$flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] New ports: A=\u_tinyriscv.u_ex.mem_rdata_i [31:24], B={ \u_tinyriscv.u_ex.mem_rdata_i [7:0] \u_tinyriscv.u_ex.mem_rdata_i [15:8] \u_tinyriscv.u_ex.mem_rdata_i [23:16] }, Y=$flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7:0] New connections: $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [31:8] = { $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5252: $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5260: { $flatten\u_tinyriscv.\u_ex.$procmux$3874_CMP $auto$opt_reduce.cc:137:opt_pmux$6247 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5270: { $flatten\u_tinyriscv.\u_ex.$procmux$3874_CMP $auto$opt_reduce.cc:137:opt_pmux$6247 } Consolidated identical input bits for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5280: Old ports: A=1'0, B=2'00, Y=\u_tinyriscv.u_ex.hold_flag New connections: \u_tinyriscv.u_ex.hold_flag = 1'0 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5298: $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5306: { $flatten\u_tinyriscv.\u_ex.$procmux$4153_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5314: $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_id.$procmux$2750: Old ports: A=0, B={ \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [7] \u_tinyriscv.u_if_id.inst_ff.qout_r [30:25] \u_tinyriscv.u_if_id.inst_ff.qout_r [11:8] 1'0 }, Y=$flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] New ports: A=12'000000000000, B={ \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [7] \u_tinyriscv.u_if_id.inst_ff.qout_r [30:25] \u_tinyriscv.u_if_id.inst_ff.qout_r [11:8] }, Y=$flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12:1] New connections: { $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [31:13] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [0] } = { $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] 1'0 } Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_id.$procmux$2853: Old ports: A=0, B={ \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31:25] \u_tinyriscv.u_if_id.inst_ff.qout_r [11:7] }, Y=$flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] New ports: A=12'000000000000, B={ \u_tinyriscv.u_if_id.inst_ff.qout_r [31:25] \u_tinyriscv.u_if_id.inst_ff.qout_r [11:7] }, Y=$flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11:0] New connections: $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [31:12] = { $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] } Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_id.$procmux$2936: Old ports: A=0, B={ \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31:20] }, Y=$flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] New ports: A=12'000000000000, B=\u_tinyriscv.u_if_id.inst_ff.qout_r [31:20], Y=$flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11:0] New connections: $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [31:12] = { $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] } Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_id.$procmux$3158: Old ports: A=0, B=4, Y=$flatten\u_tinyriscv.\u_id.$4\op2_jump_o[31:0] New ports: A=1'0, B=1'1, Y=$flatten\u_tinyriscv.\u_id.$4\op2_jump_o[31:0] [2] New connections: { $flatten\u_tinyriscv.\u_id.$4\op2_jump_o[31:0] [31:3] $flatten\u_tinyriscv.\u_id.$4\op2_jump_o[31:0] [1:0] } = 31'0000000000000000000000000000000 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3702: { $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2856_CMP $flatten\u_tinyriscv.\u_id.$procmux$2753_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3710: { $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $flatten\u_tinyriscv.\u_id.$procmux$2856_CMP $flatten\u_tinyriscv.\u_id.$procmux$2753_CMP $auto$opt_reduce.cc:137:opt_pmux$9809 $flatten\u_tinyriscv.\u_id.$procmux$2713_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3719: { $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $auto$opt_reduce.cc:137:opt_pmux$9811 $flatten\u_tinyriscv.\u_id.$procmux$2713_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3731: { $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $auto$opt_reduce.cc:137:opt_pmux$9813 $flatten\u_tinyriscv.\u_id.$procmux$2713_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$9810: { $flatten\u_tinyriscv.\u_id.$procmux$3693_CMP $flatten\u_tinyriscv.\u_id.$procmux$3681_CMP $flatten\u_tinyriscv.\u_id.$procmux$3680_CMP $flatten\u_tinyriscv.\u_id.$procmux$3679_CMP $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$9812: { $flatten\u_tinyriscv.\u_id.$procmux$3693_CMP $flatten\u_tinyriscv.\u_id.$procmux$3681_CMP $flatten\u_tinyriscv.\u_id.$procmux$3680_CMP $flatten\u_tinyriscv.\u_id.$procmux$3679_CMP $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP } Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2478: Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2484_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2478_Y New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2484_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2478_Y [2:0] New connections: $flatten\Controller.\Uart.$procmux$2478_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2580: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2574_Y, Y=$flatten\ResetBootSystem.$procmux$2580_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2574_Y [1], Y=$flatten\ResetBootSystem.$procmux$2580_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2580_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_clint.$procmux$5934: Old ports: A=5'10100, B={ 1'0 $auto$wreduce.cc:461:run$7076 [3:0] }, Y={ $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [31] $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [3:0] } New ports: A=4'0100, B={ $auto$wreduce.cc:461:run$7076 [3] 2'01 $auto$wreduce.cc:461:run$7076 [0] }, Y=$flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [3:0] New connections: $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [31] = $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [2] Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_clint.$procmux$6015: Old ports: A=$flatten\u_tinyriscv.\u_clint.$4\int_state[3:0], B={ 2'00 $auto$wreduce.cc:461:run$7074 [1:0] }, Y=$flatten\u_tinyriscv.\u_clint.$2\int_state[3:0] New ports: A={ $flatten\u_tinyriscv.\u_clint.$4\int_state[3:0] [3] 1'0 $flatten\u_tinyriscv.\u_clint.$4\int_state[3:0] [0] }, B={ 1'0 $auto$wreduce.cc:461:run$7074 [1:0] }, Y={ $flatten\u_tinyriscv.\u_clint.$2\int_state[3:0] [3] $flatten\u_tinyriscv.\u_clint.$2\int_state[3:0] [1:0] } New connections: $flatten\u_tinyriscv.\u_clint.$2\int_state[3:0] [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_id.$procmux$3202: Old ports: A=0, B=$flatten\u_tinyriscv.\u_id.$4\op2_jump_o[31:0], Y=$flatten\u_tinyriscv.\u_id.$3\op2_jump_o[31:0] New ports: A=1'0, B=$flatten\u_tinyriscv.\u_id.$4\op2_jump_o[31:0] [2], Y=$flatten\u_tinyriscv.\u_id.$3\op2_jump_o[31:0] [2] New connections: { $flatten\u_tinyriscv.\u_id.$3\op2_jump_o[31:0] [31:3] $flatten\u_tinyriscv.\u_id.$3\op2_jump_o[31:0] [1:0] } = 31'0000000000000000000000000000000 Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_clint.$procmux$6021: Old ports: A=4'0001, B=$flatten\u_tinyriscv.\u_clint.$2\int_state[3:0], Y=\u_tinyriscv.u_clint.int_state New ports: A=3'001, B={ $flatten\u_tinyriscv.\u_clint.$2\int_state[3:0] [3] $flatten\u_tinyriscv.\u_clint.$2\int_state[3:0] [1:0] }, Y={ \u_tinyriscv.u_clint.int_state [3] \u_tinyriscv.u_clint.int_state [1:0] } New connections: \u_tinyriscv.u_clint.int_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_id.$procmux$3558: Old ports: A=$flatten\u_tinyriscv.\u_id.$3\op2_jump_o[31:0], B=0, Y=$flatten\u_tinyriscv.\u_id.$2\op2_jump_o[31:0] New ports: A=$flatten\u_tinyriscv.\u_id.$3\op2_jump_o[31:0] [2], B=1'0, Y=$flatten\u_tinyriscv.\u_id.$2\op2_jump_o[31:0] [2] New connections: { $flatten\u_tinyriscv.\u_id.$2\op2_jump_o[31:0] [31:3] $flatten\u_tinyriscv.\u_id.$2\op2_jump_o[31:0] [1:0] } = 31'0000000000000000000000000000000 Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3744: Old ports: A=0, B={ $flatten\u_tinyriscv.\u_id.$2\op2_jump_o[31:0] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [19:12] \u_tinyriscv.u_if_id.inst_ff.qout_r [20] \u_tinyriscv.u_if_id.inst_ff.qout_r [30:21] 1'0 \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31:20] 32'00000000000000000000000000000100 }, Y=\u_tinyriscv.u_id_ex.op2_jump_ff.din New ports: A=21'000000000000000000000, B={ 18'000000000000000000 $flatten\u_tinyriscv.\u_id.$2\op2_jump_o[31:0] [2] 2'00 $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12:1] 1'0 \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [19:12] \u_tinyriscv.u_if_id.inst_ff.qout_r [20] \u_tinyriscv.u_if_id.inst_ff.qout_r [30:21] 1'0 \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31:20] 21'000000000000000000100 }, Y=\u_tinyriscv.u_id_ex.op2_jump_ff.din [20:0] New connections: \u_tinyriscv.u_id_ex.op2_jump_ff.din [31:21] = { \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] } Optimizing cells in module \processorci_top. Performed a total of 57 changes. 24.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~12 debug messages> Removed a total of 4 cells. 24.30.6. Executing OPT_DFF pass (perform DFF optimizations). 24.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 5 unused wires. <suppressed ~2 debug messages> 24.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~7 debug messages> 24.30.9. Rerunning OPT passes. (Maybe there is more to do..) 24.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~112 debug messages> 24.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.30.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6568 ($sdffe) from module processorci_top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6739 ($sdff) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6739 ($sdff) from module processorci_top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$6739 ($sdff) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6739 ($sdff) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6739 ($sdff) from module processorci_top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6774 ($sdff) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6818 ($sdffe) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6846 ($sdffe) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6948 ($sdffe) from module processorci_top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6948 ($sdffe) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6948 ($sdffe) from module processorci_top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. 24.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 4 unused wires. <suppressed ~1 debug messages> 24.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~7 debug messages> 24.30.16. Rerunning OPT passes. (Maybe there is more to do..) 24.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~112 debug messages> 24.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1636: Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1636_Y New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1636_Y [4:0] New connections: $flatten\Controller.\Interpreter.$procmux$1636_Y [7:5] = 3'000 Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1614: Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$7052 [0] 6'000000 $auto$wreduce.cc:461:run$7045 [1:0] 1'0 $auto$wreduce.cc:461:run$7050 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$7049 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$7048 [6] 1'0 $auto$wreduce.cc:461:run$7048 [6] 3'011 $auto$wreduce.cc:461:run$7048 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$7044 [3] 2'00 $auto$wreduce.cc:461:run$7044 [3] 6'000010 $auto$wreduce.cc:461:run$7045 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$7044 [3] $auto$wreduce.cc:461:run$7044 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1636_Y 1'0 $auto$wreduce.cc:461:run$7043 [6] 3'010 $auto$wreduce.cc:461:run$7043 [2] $auto$wreduce.cc:461:run$7043 [6] $auto$wreduce.cc:461:run$7043 [2] 13'0001001100010 $auto$wreduce.cc:461:run$7042 [2:1] $auto$wreduce.cc:461:run$7042 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$7041 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1614_Y New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$7052 [0] 5'00000 $auto$wreduce.cc:461:run$7045 [1:0] $auto$wreduce.cc:461:run$7050 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$7049 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$7048 [6] 1'0 $auto$wreduce.cc:461:run$7048 [6] 3'011 $auto$wreduce.cc:461:run$7048 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$7044 [3] 2'00 $auto$wreduce.cc:461:run$7044 [3] 5'00010 $auto$wreduce.cc:461:run$7045 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$7044 [3] $auto$wreduce.cc:461:run$7044 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1636_Y [4:0] $auto$wreduce.cc:461:run$7043 [6] 3'010 $auto$wreduce.cc:461:run$7043 [2] $auto$wreduce.cc:461:run$7043 [6] $auto$wreduce.cc:461:run$7043 [2] 11'00100110010 $auto$wreduce.cc:461:run$7042 [2:1] $auto$wreduce.cc:461:run$7042 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$7041 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1614_Y [6:0] New connections: $flatten\Controller.\Interpreter.$procmux$1614_Y [7] = 1'0 Optimizing cells in module \processorci_top. Performed a total of 2 changes. 24.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 24.30.20. Executing OPT_DFF pass (perform DFF optimizations). 24.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 3 unused wires. <suppressed ~1 debug messages> 24.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.30.23. Rerunning OPT passes. (Maybe there is more to do..) 24.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~112 debug messages> 24.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.30.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.30.27. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$7021 ($sdff) from module processorci_top. 24.30.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.30.29. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 24.30.30. Rerunning OPT passes. (Maybe there is more to do..) 24.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~112 debug messages> 24.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.30.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.30.34. Executing OPT_DFF pass (perform DFF optimizations). 24.30.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.30.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.30.37. Finished OPT passes. (There is nothing left to do.) 24.31. Executing TECHMAP pass (map to technology primitives). 24.31.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 24.31.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/arith_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 24.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $mux. Using template $paramod$constmap:a40e3cf6629147c9dca71662bcd34ce89a9f9989$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $xor. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Analyzing pattern of constant bits for this cell: Creating constmapped module `$paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr'. 24.31.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. <suppressed ~755 debug messages> 24.31.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr. <suppressed ~320 debug messages> Removed 0 unused cells and 14 unused wires. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu. Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $dffe. Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu. Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_not. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu. Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux. Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux. Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux. Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux. Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux. Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux. Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux. Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using extmapper simplemap for cells of type $lut. Using template $paramod$d7c91f8d4ce389beb1bd34b271e05fae2549a2a8\_80_ecp5_alu for cells of type $alu. Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu. Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $bmux. Using template $paramod$c6baa65225090ac0a120feab1b920965244aa496\_80_ecp5_alu for cells of type $alu. Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux. Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu. Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ecp5_alu for cells of type $alu. Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu. Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_80_ecp5_alu for cells of type $alu. Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux. Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_pmux for cells of type $pmux. Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. Using template $paramod$fbf9cabb1106ebb19d2876bda35dcfbc3788d13d\_80_ecp5_alu for cells of type $alu. Using template $paramod$b098bc6f249c0ac91c4d6e19d54b23c285914115\_90_pmux for cells of type $pmux. Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. Using template $paramod$fedb90247e1daaa8b0af86a595f377181f141d27\_90_pmux for cells of type $pmux. Using template $paramod$8e2cd9e836d46c40867c8d0d57053a4e1c3bcdbc\_90_pmux for cells of type $pmux. Using template $paramod$b3b6ac92d800c6f07aa48f510f923d86a674e5a7\_90_pmux for cells of type $pmux. Using template $paramod$c07880a582d15b9cc7030b06c09885efa6c47302\_90_pmux for cells of type $pmux. Using template $paramod$bf8e268f26361094a16ad6650df0ad1ca719658a\_90_pmux for cells of type $pmux. Using template $paramod$861f5302217787cd55fd1a501bc728125f176580\_80_ecp5_alu for cells of type $alu. Using template $paramod$c2e415ef15bc3ccd2723772353a6b450d3d76206\_90_pmux for cells of type $pmux. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $sdffce. Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~6597 debug messages> 24.32. Executing OPT pass (performing simple optimizations). 24.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~13323 debug messages> 24.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~5994 debug messages> Removed a total of 1998 cells. 24.32.3. Executing OPT_DFF pass (perform DFF optimizations). 24.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 2071 unused cells and 8501 unused wires. <suppressed ~2077 debug messages> 24.32.5. Finished fast OPT passes. 24.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 24.35. Executing TECHMAP pass (map to technology primitives). 24.35.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 24.35.2. Continuing TECHMAP pass. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. No more expansions possible. <suppressed ~1745 debug messages> 24.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~168 debug messages> 24.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 24.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in processorci_top. 24.39. Executing ATTRMVCP pass (move or copy attributes). 24.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 9035 unused wires. <suppressed ~1 debug messages> 24.41. Executing TECHMAP pass (map to technology primitives). 24.41.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/latches_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 24.41.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 24.42. Executing ABC9 pass. 24.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.3. Executing PROC pass (convert processes to netlists). 24.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$54762'. Cleaned up 1 empty switch. 24.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$54763 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.3.4. Executing PROC_INIT pass (extract init attributes). 24.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$54763'. 1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$54761_EN[3:0]$54769 2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$54761_DATA[3:0]$54768 3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$54761_ADDR[3:0]$54767 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$54762'. 24.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54747_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54748_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54749_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54753_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54754_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54755_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54759_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54745_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54760_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54750_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54757_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54751_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54756_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54758_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54752_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$54746_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$54761_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$54763'. created $dff cell `$procdff$54813' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$54761_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$54763'. created $dff cell `$procdff$54814' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$54761_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$54763'. created $dff cell `$procdff$54815' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$54762'. created direct connection (no actual register cell created). 24.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$54787'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$54763'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$54762'. Cleaned up 1 empty switch. 24.42.3.12. Executing OPT_EXPR pass (perform const folding). 24.42.4. Executing SCC pass (detecting logic loops). Found an SCC: $auto$simplemap.cc:38:simplemap_not$21112 $auto$ff.cc:266:slice$22804 $auto$ff.cc:266:slice$22800 $auto$simplemap.cc:38:simplemap_not$37267 $auto$ff.cc:266:slice$22858 $auto$simplemap.cc:38:simplemap_not$29417 $auto$ff.cc:266:slice$22857 $auto$simplemap.cc:38:simplemap_not$29416 $auto$ff.cc:266:slice$22856 $auto$simplemap.cc:38:simplemap_not$29412 $auto$ff.cc:266:slice$22852 $auto$simplemap.cc:38:simplemap_not$29415 $auto$ff.cc:266:slice$22855 $auto$simplemap.cc:38:simplemap_not$29411 $auto$ff.cc:266:slice$22851 $auto$simplemap.cc:38:simplemap_not$29410 $auto$ff.cc:266:slice$22850 $auto$simplemap.cc:38:simplemap_not$29409 $auto$ff.cc:266:slice$22849 $auto$simplemap.cc:38:simplemap_not$29408 $auto$ff.cc:266:slice$22848 $auto$simplemap.cc:38:simplemap_not$29407 $auto$ff.cc:266:slice$22847 $auto$simplemap.cc:38:simplemap_not$37254 $auto$ff.cc:266:slice$22845 $auto$simplemap.cc:38:simplemap_not$37255 $auto$ff.cc:266:slice$22846 $auto$ff.cc:266:slice$22799 $auto$ff.cc:266:slice$22798 $auto$ff.cc:266:slice$22797 $auto$simplemap.cc:38:simplemap_not$29402 $auto$ff.cc:266:slice$22842 $auto$simplemap.cc:38:simplemap_not$29401 $auto$ff.cc:266:slice$22841 $auto$simplemap.cc:38:simplemap_not$36847 $auto$ff.cc:266:slice$22840 $auto$simplemap.cc:38:simplemap_not$36851 $auto$ff.cc:266:slice$22844 $auto$simplemap.cc:38:simplemap_not$36846 $auto$ff.cc:266:slice$22839 $auto$simplemap.cc:75:simplemap_bitop$29332 $auto$simplemap.cc:38:simplemap_not$29396 $auto$ff.cc:266:slice$22836 $auto$simplemap.cc:38:simplemap_not$36842 $auto$ff.cc:266:slice$22835 $auto$simplemap.cc:38:simplemap_not$36841 $auto$ff.cc:266:slice$22834 $auto$simplemap.cc:38:simplemap_not$29398 $auto$ff.cc:266:slice$22838 $auto$simplemap.cc:38:simplemap_not$29393 $auto$ff.cc:266:slice$22833 $auto$simplemap.cc:75:simplemap_bitop$29326 $auto$simplemap.cc:38:simplemap_not$36837 $auto$ff.cc:266:slice$22830 $auto$simplemap.cc:126:simplemap_reduce$10884 $auto$simplemap.cc:75:simplemap_bitop$37174 $auto$simplemap.cc:38:simplemap_not$36836 $auto$ff.cc:266:slice$22829 $auto$simplemap.cc:38:simplemap_not$36835 $auto$ff.cc:266:slice$22828 $auto$simplemap.cc:75:simplemap_bitop$29328 $auto$simplemap.cc:38:simplemap_not$29392 $auto$ff.cc:266:slice$22832 $auto$simplemap.cc:75:simplemap_bitop$37203 $auto$ff.cc:266:slice$22826 $auto$simplemap.cc:75:simplemap_bitop$29351 $auto$ff.cc:266:slice$22823 $auto$ff.cc:266:slice$22822 $auto$ff.cc:266:slice$22821 $auto$simplemap.cc:225:simplemap_logbin$37110 $auto$simplemap.cc:225:simplemap_logbin$37111 $auto$simplemap.cc:126:simplemap_reduce$10898 $auto$simplemap.cc:75:simplemap_bitop$29353 $auto$ff.cc:266:slice$22825 $auto$simplemap.cc:75:simplemap_bitop$29348 $auto$ff.cc:266:slice$22820 $auto$simplemap.cc:126:simplemap_reduce$10895 $auto$simplemap.cc:75:simplemap_bitop$29347 $auto$ff.cc:266:slice$22819 $auto$ff.cc:266:slice$22762 $auto$ff.cc:266:slice$22761 $auto$ff.cc:266:slice$22758 $auto$ff.cc:266:slice$22757 $auto$simplemap.cc:75:simplemap_bitop$37191 $auto$ff.cc:266:slice$22814 $auto$simplemap.cc:126:simplemap_reduce$20566 $auto$opt_expr.cc:617:replace_const_cells$50245 $auto$ff.cc:266:slice$22756 $auto$simplemap.cc:126:simplemap_reduce$10892 $auto$simplemap.cc:75:simplemap_bitop$37190 $auto$ff.cc:266:slice$22813 $auto$simplemap.cc:75:simplemap_bitop$29340 $auto$ff.cc:266:slice$22812 $auto$simplemap.cc:167:logic_reduce$20982 $auto$simplemap.cc:167:logic_reduce$20979 $auto$ff.cc:266:slice$22760 $auto$ff.cc:266:slice$22811 $auto$simplemap.cc:75:simplemap_bitop$29336 $auto$ff.cc:266:slice$22808 $auto$simplemap.cc:126:simplemap_reduce$10889 $auto$simplemap.cc:75:simplemap_bitop$29335 $auto$ff.cc:266:slice$22807 $auto$simplemap.cc:75:simplemap_bitop$29334 $auto$ff.cc:266:slice$22806 $auto$simplemap.cc:75:simplemap_bitop$29338 $auto$ff.cc:266:slice$22810 $auto$ff.cc:266:slice$22805 $auto$simplemap.cc:75:simplemap_bitop$29330 $auto$ff.cc:266:slice$22802 $auto$simplemap.cc:126:simplemap_reduce$10886 $auto$simplemap.cc:75:simplemap_bitop$29329 $auto$ff.cc:266:slice$22801 $auto$opt_expr.cc:617:replace_const_cells$50315 $auto$ff.cc:266:slice$22743 $auto$opt_expr.cc:617:replace_const_cells$50261 $auto$ff.cc:266:slice$22745 $auto$opt_expr.cc:617:replace_const_cells$50323 $auto$ff.cc:266:slice$22737 $auto$opt_expr.cc:617:replace_const_cells$51341 $auto$ff.cc:266:slice$22736 $auto$opt_expr.cc:617:replace_const_cells$50341 $auto$ff.cc:266:slice$22734 $auto$simplemap.cc:126:simplemap_reduce$22199 $auto$simplemap.cc:126:simplemap_reduce$22196 $auto$simplemap.cc:126:simplemap_reduce$22243 $auto$simplemap.cc:126:simplemap_reduce$22240 $auto$simplemap.cc:126:simplemap_reduce$22267 $auto$simplemap.cc:126:simplemap_reduce$22264 $auto$opt_expr.cc:617:replace_const_cells$51349 $auto$ff.cc:266:slice$22735 $auto$simplemap.cc:126:simplemap_reduce$22172 $auto$simplemap.cc:126:simplemap_reduce$22217 $auto$simplemap.cc:126:simplemap_reduce$22285 $auto$opt_expr.cc:617:replace_const_cells$51347 $auto$ff.cc:266:slice$22733 $auto$opt_expr.cc:617:replace_const_cells$51343 $auto$ff.cc:266:slice$22731 $auto$simplemap.cc:38:simplemap_not$29387 $auto$ff.cc:266:slice$22827 $auto$simplemap.cc:75:simplemap_bitop$37172 $auto$ff.cc:266:slice$22795 $auto$simplemap.cc:196:simplemap_lognot$20553 $auto$simplemap.cc:126:simplemap_reduce$20551 $auto$simplemap.cc:196:simplemap_lognot$21552 $auto$simplemap.cc:126:simplemap_reduce$21550 $auto$simplemap.cc:126:simplemap_reduce$22175 $auto$simplemap.cc:196:simplemap_lognot$22203 $auto$simplemap.cc:126:simplemap_reduce$22201 $auto$simplemap.cc:126:simplemap_reduce$25635 $auto$simplemap.cc:196:simplemap_lognot$22225 $auto$simplemap.cc:126:simplemap_reduce$22223 $auto$simplemap.cc:126:simplemap_reduce$22220 $auto$simplemap.cc:126:simplemap_reduce$41068 $auto$simplemap.cc:126:simplemap_reduce$25637 $auto$simplemap.cc:196:simplemap_lognot$22247 $auto$simplemap.cc:126:simplemap_reduce$22245 $auto$simplemap.cc:126:simplemap_reduce$22288 $auto$simplemap.cc:126:simplemap_reduce$22284 $auto$opt_expr.cc:617:replace_const_cells$51345 $auto$ff.cc:266:slice$22732 $auto$simplemap.cc:196:simplemap_lognot$21353 $auto$simplemap.cc:126:simplemap_reduce$21351 $auto$simplemap.cc:126:simplemap_reduce$21420 $auto$simplemap.cc:126:simplemap_reduce$38260 $auto$simplemap.cc:196:simplemap_lognot$21398 $auto$simplemap.cc:126:simplemap_reduce$21396 $auto$simplemap.cc:126:simplemap_reduce$21433 $auto$opt_expr.cc:617:replace_const_cells$50523 $auto$simplemap.cc:196:simplemap_lognot$21411 $auto$simplemap.cc:126:simplemap_reduce$21409 $auto$simplemap.cc:75:simplemap_bitop$38253 $auto$simplemap.cc:196:simplemap_lognot$21450 $auto$simplemap.cc:126:simplemap_reduce$21448 $auto$simplemap.cc:126:simplemap_reduce$21446 $auto$simplemap.cc:126:simplemap_reduce$38241 $auto$simplemap.cc:126:simplemap_reduce$40379 $auto$simplemap.cc:196:simplemap_lognot$21525 $auto$simplemap.cc:126:simplemap_reduce$21523 $auto$simplemap.cc:126:simplemap_reduce$38243 $auto$simplemap.cc:126:simplemap_reduce$38262 $auto$simplemap.cc:196:simplemap_lognot$21530 $auto$simplemap.cc:167:logic_reduce$21529 $auto$simplemap.cc:167:logic_reduce$21527 $auto$ff.cc:266:slice$22744 $auto$opt_expr.cc:617:replace_const_cells$51099 $auto$simplemap.cc:267:simplemap_mux$20421 $auto$simplemap.cc:267:simplemap_mux$20454 $auto$simplemap.cc:267:simplemap_mux$20847 $auto$simplemap.cc:225:simplemap_logbin$20576 $auto$simplemap.cc:196:simplemap_lognot$20575 $auto$simplemap.cc:126:simplemap_reduce$20573 $auto$simplemap.cc:126:simplemap_reduce$20570 $auto$simplemap.cc:126:simplemap_reduce$20999 $auto$ff.cc:266:slice$22759 $auto$alumacc.cc:485:replace_alu$7326.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10900 $auto$simplemap.cc:126:simplemap_reduce$10883 $auto$simplemap.cc:75:simplemap_bitop$29324 $auto$alumacc.cc:485:replace_alu$7308.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[0].ccu2c_i $auto$ff.cc:266:slice$22796 $auto$simplemap.cc:126:simplemap_reduce$10887 $auto$simplemap.cc:75:simplemap_bitop$29331 $auto$ff.cc:266:slice$22803 $auto$simplemap.cc:126:simplemap_reduce$10903 $auto$simplemap.cc:126:simplemap_reduce$10890 $auto$simplemap.cc:75:simplemap_bitop$29337 $auto$ff.cc:266:slice$22809 $auto$simplemap.cc:75:simplemap_bitop$37192 $auto$ff.cc:266:slice$22815 $auto$ff.cc:266:slice$22816 $auto$simplemap.cc:75:simplemap_bitop$29345 $auto$ff.cc:266:slice$22817 $auto$simplemap.cc:126:simplemap_reduce$10894 $auto$simplemap.cc:75:simplemap_bitop$29346 $auto$ff.cc:266:slice$22818 $auto$simplemap.cc:126:simplemap_reduce$10907 $auto$simplemap.cc:126:simplemap_reduce$10897 $auto$simplemap.cc:75:simplemap_bitop$29352 $auto$ff.cc:266:slice$22824 $auto$alumacc.cc:485:replace_alu$7326.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10909 $auto$simplemap.cc:126:simplemap_reduce$10901 $auto$simplemap.cc:126:simplemap_reduce$10885 $auto$simplemap.cc:75:simplemap_bitop$29327 $auto$simplemap.cc:38:simplemap_not$29391 $auto$ff.cc:266:slice$22831 $auto$alumacc.cc:485:replace_alu$7326.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[10].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[10].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10914 $auto$simplemap.cc:126:simplemap_reduce$10910 $auto$simplemap.cc:126:simplemap_reduce$10902 $auto$simplemap.cc:126:simplemap_reduce$10888 $auto$simplemap.cc:75:simplemap_bitop$37182 $auto$simplemap.cc:38:simplemap_not$37246 $auto$ff.cc:266:slice$22837 $auto$alumacc.cc:485:replace_alu$7326.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[18].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[16].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[18].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[16].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10904 $auto$simplemap.cc:126:simplemap_reduce$10891 $auto$simplemap.cc:75:simplemap_bitop$29339 $auto$simplemap.cc:38:simplemap_not$29403 $auto$ff.cc:266:slice$22843 $auto$simplemap.cc:75:simplemap_bitop$29349 $auto$simplemap.cc:38:simplemap_not$29413 $auto$ff.cc:266:slice$22853 $auto$simplemap.cc:75:simplemap_bitop$38256 $auto$simplemap.cc:38:simplemap_not$20750 $auto$simplemap.cc:126:simplemap_reduce$38245 $auto$simplemap.cc:75:simplemap_bitop$38257 $auto$simplemap.cc:126:simplemap_reduce$10985 $auto$simplemap.cc:38:simplemap_not$10995 $auto$simplemap.cc:75:simplemap_bitop$10881 $auto$simplemap.cc:38:simplemap_not$10970 $auto$alumacc.cc:485:replace_alu$7326.slice[30].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[28].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[26].ccu2c_i $auto$simplemap.cc:225:simplemap_logbin$37108 $auto$simplemap.cc:225:simplemap_logbin$37109 $auto$simplemap.cc:75:simplemap_bitop$10805 $auto$simplemap.cc:75:simplemap_bitop$38254 $auto$simplemap.cc:38:simplemap_not$20744 $auto$simplemap.cc:126:simplemap_reduce$38249 $auto$simplemap.cc:126:simplemap_reduce$38246 $auto$simplemap.cc:75:simplemap_bitop$38255 $auto$simplemap.cc:126:simplemap_reduce$10983 $auto$simplemap.cc:38:simplemap_not$10880 $auto$simplemap.cc:75:simplemap_bitop$10859 $auto$simplemap.cc:75:simplemap_bitop$10806 $auto$alumacc.cc:485:replace_alu$7308.slice[30].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[28].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[26].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10912 $auto$simplemap.cc:126:simplemap_reduce$10906 $auto$simplemap.cc:126:simplemap_reduce$10896 $auto$simplemap.cc:75:simplemap_bitop$29350 $auto$simplemap.cc:38:simplemap_not$29414 $auto$ff.cc:266:slice$22854 $auto$simplemap.cc:75:simplemap_bitop$22730 $auto$simplemap.cc:341:simplemap_lut$19493 $auto$ff.cc:266:slice$10535 $auto$ff.cc:266:slice$10544 $auto$ff.cc:266:slice$10558 $auto$opt_expr.cc:617:replace_const_cells$50373 $auto$ff.cc:266:slice$10532 $auto$simplemap.cc:126:simplemap_reduce$27491 $auto$ff.cc:266:slice$10559 $auto$ff.cc:266:slice$10552 $auto$ff.cc:266:slice$10555 $auto$opt_expr.cc:617:replace_const_cells$50379 $auto$ff.cc:266:slice$10549 $auto$ff.cc:266:slice$10543 $auto$ff.cc:266:slice$10537 $auto$ff.cc:266:slice$10531 $auto$opt_expr.cc:617:replace_const_cells$50371 $auto$ff.cc:266:slice$10529 $auto$ff.cc:266:slice$10540 $auto$opt_expr.cc:617:replace_const_cells$50381 $auto$ff.cc:266:slice$10556 $auto$simplemap.cc:126:simplemap_reduce$27480 $auto$ff.cc:266:slice$10536 $auto$simplemap.cc:126:simplemap_reduce$27488 $auto$ff.cc:266:slice$10553 $auto$ff.cc:266:slice$10551 $auto$simplemap.cc:126:simplemap_reduce$27499 $auto$simplemap.cc:126:simplemap_reduce$27489 $auto$ff.cc:266:slice$10554 $auto$simplemap.cc:126:simplemap_reduce$27478 $auto$opt_expr.cc:617:replace_const_cells$50375 $auto$ff.cc:266:slice$10533 $auto$simplemap.cc:126:simplemap_reduce$27477 $auto$ff.cc:266:slice$10530 $auto$simplemap.cc:126:simplemap_reduce$27331 $auto$simplemap.cc:126:simplemap_reduce$27405 $auto$opt_expr.cc:617:replace_const_cells$50367 $auto$simplemap.cc:126:simplemap_reduce$27486 $auto$ff.cc:266:slice$10548 $auto$simplemap.cc:126:simplemap_reduce$27343 $auto$simplemap.cc:126:simplemap_reduce$27417 $auto$simplemap.cc:126:simplemap_reduce$27498 $auto$simplemap.cc:126:simplemap_reduce$27487 $auto$ff.cc:266:slice$10550 $auto$ff.cc:266:slice$10538 $auto$simplemap.cc:126:simplemap_reduce$27424 $auto$simplemap.cc:126:simplemap_reduce$27419 $auto$simplemap.cc:126:simplemap_reduce$27409 $auto$simplemap.cc:126:simplemap_reduce$27505 $auto$simplemap.cc:126:simplemap_reduce$27500 $auto$simplemap.cc:126:simplemap_reduce$27490 $auto$opt_expr.cc:617:replace_const_cells$50383 $auto$ff.cc:266:slice$10557 $auto$simplemap.cc:126:simplemap_reduce$27484 $auto$ff.cc:266:slice$10545 $auto$ff.cc:266:slice$10546 $auto$simplemap.cc:126:simplemap_reduce$27353 $auto$simplemap.cc:126:simplemap_reduce$27349 $auto$simplemap.cc:126:simplemap_reduce$27427 $auto$simplemap.cc:126:simplemap_reduce$27423 $auto$simplemap.cc:126:simplemap_reduce$27508 $auto$simplemap.cc:126:simplemap_reduce$27504 $auto$simplemap.cc:126:simplemap_reduce$27497 $auto$simplemap.cc:126:simplemap_reduce$27485 $auto$ff.cc:266:slice$10547 $auto$simplemap.cc:126:simplemap_reduce$27482 $auto$ff.cc:266:slice$10541 $auto$simplemap.cc:126:simplemap_reduce$27495 $auto$simplemap.cc:126:simplemap_reduce$27481 $auto$ff.cc:266:slice$10539 $auto$simplemap.cc:126:simplemap_reduce$27503 $auto$simplemap.cc:126:simplemap_reduce$27496 $auto$simplemap.cc:126:simplemap_reduce$27483 $auto$ff.cc:266:slice$10542 $auto$simplemap.cc:126:simplemap_reduce$27494 $auto$simplemap.cc:126:simplemap_reduce$27479 $auto$opt_expr.cc:617:replace_const_cells$50377 $auto$ff.cc:266:slice$10534 $auto$simplemap.cc:126:simplemap_reduce$19534 $auto$simplemap.cc:196:simplemap_lognot$27357 $auto$simplemap.cc:126:simplemap_reduce$27355 $auto$simplemap.cc:267:simplemap_mux$27805 $auto$simplemap.cc:267:simplemap_mux$27802 $auto$simplemap.cc:126:simplemap_reduce$47494 $auto$simplemap.cc:196:simplemap_lognot$27431 $auto$simplemap.cc:126:simplemap_reduce$27429 $auto$simplemap.cc:126:simplemap_reduce$27939 $auto$opt_expr.cc:617:replace_const_cells$50385 $auto$simplemap.cc:267:simplemap_mux$27804 $auto$simplemap.cc:267:simplemap_mux$27801 $auto$simplemap.cc:75:simplemap_bitop$27283 $auto$simplemap.cc:126:simplemap_reduce$27941 $auto$simplemap.cc:267:simplemap_mux$27806 $auto$simplemap.cc:267:simplemap_mux$27803 $auto$simplemap.cc:196:simplemap_lognot$27512 $auto$simplemap.cc:126:simplemap_reduce$27510 $auto$simplemap.cc:126:simplemap_reduce$27507 $auto$simplemap.cc:126:simplemap_reduce$27502 $auto$simplemap.cc:126:simplemap_reduce$27493 $auto$simplemap.cc:126:simplemap_reduce$27476 $auto$opt_expr.cc:617:replace_const_cells$50369 $auto$ff.cc:266:slice$14521 $auto$simplemap.cc:75:simplemap_bitop$26050 $auto$simplemap.cc:225:simplemap_logbin$27249 $auto$simplemap.cc:225:simplemap_logbin$27248 $auto$simplemap.cc:225:simplemap_logbin$20466 $auto$simplemap.cc:225:simplemap_logbin$20465 $auto$simplemap.cc:267:simplemap_mux$41105 $auto$simplemap.cc:126:simplemap_reduce$41102 $auto$simplemap.cc:75:simplemap_bitop$41103 $auto$simplemap.cc:267:simplemap_mux$38258 $auto$simplemap.cc:126:simplemap_reduce$38251 $auto$simplemap.cc:126:simplemap_reduce$38247 $auto$simplemap.cc:75:simplemap_bitop$38252 $auto$simplemap.cc:126:simplemap_reduce$10858 $auto$simplemap.cc:126:simplemap_reduce$10915 $auto$simplemap.cc:126:simplemap_reduce$10911 $auto$simplemap.cc:126:simplemap_reduce$10905 $auto$simplemap.cc:126:simplemap_reduce$10893 $auto$simplemap.cc:75:simplemap_bitop$37193 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$50691 $auto$ff.cc:266:slice$15193 $auto$simplemap.cc:126:simplemap_reduce$15309 $auto$simplemap.cc:126:simplemap_reduce$15294 $auto$ff.cc:266:slice$15194 $auto$ff.cc:266:slice$15195 $auto$simplemap.cc:75:simplemap_bitop$30835 $auto$simplemap.cc:196:simplemap_lognot$15314 $auto$simplemap.cc:126:simplemap_reduce$15312 $auto$simplemap.cc:126:simplemap_reduce$15310 $auto$opt_expr.cc:617:replace_const_cells$50663 $auto$opt_expr.cc:617:replace_const_cells$50683 $auto$simplemap.cc:267:simplemap_mux$30831 $auto$simplemap.cc:126:simplemap_reduce$30845 $auto$simplemap.cc:126:simplemap_reduce$30842 $auto$simplemap.cc:196:simplemap_lognot$15250 $auto$simplemap.cc:126:simplemap_reduce$15248 $auto$opt_expr.cc:617:replace_const_cells$50681 $auto$simplemap.cc:267:simplemap_mux$30832 $auto$simplemap.cc:126:simplemap_reduce$30850 $auto$simplemap.cc:126:simplemap_reduce$30847 $auto$simplemap.cc:75:simplemap_bitop$30833 $auto$simplemap.cc:267:simplemap_mux$15281 $auto$simplemap.cc:225:simplemap_logbin$15284 $auto$simplemap.cc:196:simplemap_lognot$15299 $auto$simplemap.cc:126:simplemap_reduce$15297 $auto$simplemap.cc:126:simplemap_reduce$15295 $auto$ff.cc:266:slice$15196 $auto$simplemap.cc:126:simplemap_reduce$16261 $auto$simplemap.cc:126:simplemap_reduce$16259 $auto$simplemap.cc:225:simplemap_logbin$15240 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$50689 $auto$ff.cc:266:slice$15059 $auto$simplemap.cc:126:simplemap_reduce$15175 $auto$simplemap.cc:126:simplemap_reduce$15148 $auto$ff.cc:266:slice$15060 $auto$simplemap.cc:38:simplemap_not$30853 $auto$ff.cc:266:slice$15061 $auto$simplemap.cc:126:simplemap_reduce$15180 $auto$simplemap.cc:126:simplemap_reduce$15176 $auto$simplemap.cc:126:simplemap_reduce$15153 $auto$simplemap.cc:126:simplemap_reduce$15149 $auto$simplemap.cc:38:simplemap_not$30854 $auto$ff.cc:266:slice$15062 $auto$simplemap.cc:38:simplemap_not$30855 $auto$ff.cc:266:slice$15063 $auto$simplemap.cc:126:simplemap_reduce$15177 $auto$simplemap.cc:126:simplemap_reduce$15150 $auto$simplemap.cc:38:simplemap_not$30856 $auto$ff.cc:266:slice$15064 $auto$simplemap.cc:38:simplemap_not$30857 $auto$ff.cc:266:slice$15065 $auto$simplemap.cc:126:simplemap_reduce$15156 $auto$simplemap.cc:126:simplemap_reduce$15154 $auto$simplemap.cc:126:simplemap_reduce$15151 $auto$simplemap.cc:126:simplemap_reduce$15183 $auto$simplemap.cc:126:simplemap_reduce$15181 $auto$simplemap.cc:126:simplemap_reduce$15178 $auto$simplemap.cc:38:simplemap_not$30858 $auto$ff.cc:266:slice$15066 $auto$simplemap.cc:196:simplemap_lognot$15187 $auto$simplemap.cc:126:simplemap_reduce$15185 $auto$simplemap.cc:126:simplemap_reduce$15158 $auto$ff.cc:266:slice$15067 $auto$simplemap.cc:167:logic_reduce$27793 $auto$simplemap.cc:225:simplemap_logbin$15132 $auto$simplemap.cc:225:simplemap_logbin$15133 $auto$simplemap.cc:196:simplemap_lognot$15160 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$50685 $auto$ff.cc:266:slice$15197 $auto$simplemap.cc:126:simplemap_reduce$15329 $auto$ff.cc:266:slice$15198 $auto$ff.cc:266:slice$15199 $auto$simplemap.cc:126:simplemap_reduce$15334 $auto$simplemap.cc:126:simplemap_reduce$15330 $auto$simplemap.cc:38:simplemap_not$30749 $auto$ff.cc:266:slice$15200 $auto$simplemap.cc:38:simplemap_not$30750 $auto$ff.cc:266:slice$15201 $auto$simplemap.cc:126:simplemap_reduce$15331 $auto$ff.cc:266:slice$15202 $auto$ff.cc:266:slice$15203 $auto$simplemap.cc:38:simplemap_not$30753 $auto$ff.cc:266:slice$15204 $auto$ff.cc:266:slice$15205 $auto$simplemap.cc:126:simplemap_reduce$16273 $auto$simplemap.cc:196:simplemap_lognot$15341 $auto$simplemap.cc:126:simplemap_reduce$15339 $auto$simplemap.cc:126:simplemap_reduce$15337 $auto$simplemap.cc:126:simplemap_reduce$15335 $auto$simplemap.cc:126:simplemap_reduce$15332 $auto$simplemap.cc:38:simplemap_not$30752 Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$16365 $auto$simplemap.cc:126:simplemap_reduce$16326 $auto$simplemap.cc:126:simplemap_reduce$16368 $auto$simplemap.cc:126:simplemap_reduce$16366 $auto$simplemap.cc:38:simplemap_not$16648 $auto$simplemap.cc:38:simplemap_not$30801 $auto$ff.cc:266:slice$27977 $auto$ff.cc:479:convert_ce_over_srst$53027 $auto$simplemap.cc:126:simplemap_reduce$10999 $auto$ff.cc:266:slice$27976 $auto$ff.cc:479:convert_ce_over_srst$53025 $auto$simplemap.cc:38:simplemap_not$30799 $auto$ff.cc:266:slice$27975 $auto$ff.cc:479:convert_ce_over_srst$53023 $auto$simplemap.cc:126:simplemap_reduce$10998 $auto$ff.cc:266:slice$27974 $auto$ff.cc:479:convert_ce_over_srst$53021 $auto$simplemap.cc:38:simplemap_not$10822 $auto$alumacc.cc:485:replace_alu$7155.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$7155.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$7155.slice[0].ccu2c_i $auto$simplemap.cc:38:simplemap_not$30797 $auto$ff.cc:266:slice$27973 $auto$ff.cc:479:convert_ce_over_srst$53019 $auto$simplemap.cc:126:simplemap_reduce$26821 $auto$simplemap.cc:75:simplemap_bitop$16509 $auto$simplemap.cc:126:simplemap_reduce$11003 $auto$simplemap.cc:126:simplemap_reduce$11001 $auto$simplemap.cc:126:simplemap_reduce$10997 $auto$opt_expr.cc:617:replace_const_cells$50687 $auto$ff.cc:266:slice$27972 $auto$ff.cc:479:convert_ce_over_srst$53017 $auto$simplemap.cc:126:simplemap_reduce$16328 Found 5 SCCs in module processorci_top. Found 5 SCCs. 24.42.5. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.6. Executing PROC pass (convert processes to netlists). 24.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 24.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 24.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 24.42.6.4. Executing PROC_INIT pass (extract init attributes). 24.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 24.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 24.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). 24.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 24.42.6.12. Executing OPT_EXPR pass (perform const folding). 24.42.7. Executing TECHMAP pass (map to technology primitives). 24.42.7.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 24.42.7.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~162 debug messages> 24.42.8. Executing OPT pass (performing simple optimizations). 24.42.8.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 24.42.8.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 24.42.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 24.42.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Performed a total of 0 changes. 24.42.8.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 24.42.8.6. Executing OPT_DFF pass (perform DFF optimizations). 24.42.8.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. 24.42.8.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 24.42.8.9. Finished OPT passes. (There is nothing left to do.) 24.42.9. Executing TECHMAP pass (map to technology primitives). 24.42.9.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_map.v Parsing Verilog input from `/usr/local/share/synlig/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 24.42.9.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~1063 debug messages> 24.42.10. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_model.v Parsing Verilog input from `/usr/local/share/synlig/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 24.42.11. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 24.42.12. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.13. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 24.42.14. Executing TECHMAP pass (map to technology primitives). 24.42.14.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 24.42.14.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using extmapper simplemap for cells of type $and. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $xor. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~201 debug messages> 24.42.15. Executing OPT pass (performing simple optimizations). 24.42.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~18 debug messages> 24.42.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 24.42.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 24.42.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.42.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.42.15.6. Executing OPT_DFF pass (perform DFF optimizations). 24.42.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 24.42.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.42.15.9. Rerunning OPT passes. (Maybe there is more to do..) 24.42.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 24.42.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.42.15.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.42.15.13. Executing OPT_DFF pass (perform DFF optimizations). 24.42.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.42.15.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.42.15.16. Finished OPT passes. (There is nothing left to do.) 24.42.16. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 24.42.17. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 11874 cells with 72675 new cells, skipped 8934 cells. replaced 3 cell types: 3481 $_OR_ 273 $_XOR_ 8120 $_MUX_ not replaced 9 cell types: 38 $scopeinfo 1285 $_NOT_ 3344 $_AND_ 1630 TRELLIS_FF 4 MULT18X18D 512 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 1060 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1060 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 1 $__ABC9_SCC_BREAKER 24.42.17.1. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.17.2. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.17.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 32004 AND gates and 90654 wires from module `processorci_top' to a netlist network with 6010 inputs and 2471 outputs. 24.42.17.4. Executing ABC9_EXE pass (technology mapping using ABC9). 24.42.17.5. Executing ABC9. Running ABC command: "built in abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 6010/ 2471 and = 27374 lev = 62 (3.59) mem = 0.73 MB box = 1572 bb = 1060 ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 1 carries. ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 6010/ 2471 and = 30591 lev = 57 (2.67) mem = 0.77 MB ch = 2858 box = 1571 bb = 1060 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 64. Obj = 148. Set = 672. CutMin = no ABC: Node = 30591. Ch = 2131. Total mem = 9.06 MB. Peak cut mem = 0.31 MB. ABC: P: Del = 6758.00. Ar = 34039.0. Edge = 39045. Cut = 365578. T = 0.19 sec ABC: P: Del = 6487.00. Ar = 34314.0. Edge = 38851. Cut = 361831. T = 0.19 sec ABC: P: Del = 6487.00. Ar = 12836.0. Edge = 29525. Cut = 943403. T = 0.40 sec ABC: F: Del = 6487.00. Ar = 9442.0. Edge = 25926. Cut = 663293. T = 0.30 sec ABC: A: Del = 6487.00. Ar = 8808.0. Edge = 24580. Cut = 633019. T = 0.44 sec ABC: A: Del = 6487.00. Ar = 8713.0. Edge = 24519. Cut = 651217. T = 0.45 sec ABC: Total time = 1.97 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 6010/ 2471 and = 20155 lev = 39 (2.54) mem = 0.65 MB box = 1556 bb = 1060 ABC: Mapping (K=7) : lut = 6196 edge = 24180 lev = 14 (1.16) Boxes are not in a topological order. Switching to level computation without boxes. ABC: levB = 39 mem = 0.32 MB ABC: LUT = 6196 : 2=710 11.5 % 3=769 12.4 % 4=3557 57.4 % 5=877 14.2 % 6=141 2.3 % 7=142 2.3 % Ave = 3.90 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 21.78 seconds, total: 21.78 seconds 24.42.17.6. Executing AIGER frontend. <suppressed ~16990 debug messages> Removed 27340 unused cells and 59104 unused wires. 24.42.17.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 6339 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 496 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 1060 ABC RESULTS: input signals: 1170 ABC RESULTS: output signals: 896 Removing temp directory. 24.42.18. Executing TECHMAP pass (map to technology primitives). 24.42.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_unmap.v Parsing Verilog input from `/usr/local/share/synlig/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 24.42.18.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000111 for cells of type $__ABC9_SCC_BREAKER. No more expansions possible. <suppressed ~2636 debug messages> Removed 801 unused cells and 108121 unused wires. 24.43. Executing TECHMAP pass (map to technology primitives). 24.43.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 24.43.2. Continuing TECHMAP pass. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod$7c68a38461eada437758033cda986c95136e1369\$lut for cells of type $lut. Using template $paramod$4d5682dd6afedfd6df0816b3bca3365bbde91748\$lut for cells of type $lut. Using template $paramod$e99efde60e8bbf071c427dcb0b4fe988dd102747\$lut for cells of type $lut. Using template $paramod$3f5e8e968ca7780b5a760eb196da90e4d94c7d1a\$lut for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod$606f15653d571c851360b76e1498073cdb5dc46e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$927bdb4eb8d02f9706a5d816b5ea39033d471fe3\$lut for cells of type $lut. Using template $paramod$e5b29079c1a88f3fc663c746ec8e3359690ef674\$lut for cells of type $lut. Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. Using template $paramod$0c5a54c406cdb1ed108583f5d43071050a5e4d5c\$lut for cells of type $lut. Using template $paramod$2da4e79babca97798b8fb3b68e51114342ae493f\$lut for cells of type $lut. Using template $paramod$a038b01fe89a3b29f2d4d98f2a4d6878b0b7760e\$lut for cells of type $lut. Using template $paramod$116655be62007216c8cfda4964fcaab629eccb20\$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod$5afe21d6fdc7c33aeb338fdb508ea02813207bfd\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$059968be1ef12c596bb5d360a749040b6777bf4a\$lut for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100111 for cells of type $lut. Using template $paramod$a5788e8bd3559e65ba7c6a1d93529c6fb76569b9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod$78204da8196d468a927dfece17c9d1adec19023e\$lut for cells of type $lut. Using template $paramod$424ce08c2f6321b5fcb06e45c3aa4587fa178c07\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut. Using template $paramod$446d5374f1a9a50c11eb107999155fc0219be593\$lut for cells of type $lut. Using template $paramod$a9fc6e1212e2c97f661279eebf7fa89d410eb14a\$lut for cells of type $lut. Using template $paramod$e8fd0fa4ad0550d14a2e9d5228b6c80ed55d39b8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$9cf044275e70b6dc34d2f815a6f8ffc23f9694a0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod$d4deb40e56924063eb7f8011c5cc44d12ff04ace\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod$26e2480f174c5057502fb95a7a74f2c6b0a38942\$lut for cells of type $lut. Using template $paramod$d6ac8e10b0ed26eaa611fbbc43317c4bf839e778\$lut for cells of type $lut. Using template $paramod$cfea1bc217ea46f20b0865417d911a6c847edf68\$lut for cells of type $lut. Using template $paramod$3156f2d69ee2a18bf68b5d292ef83b87c67861f2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut. Using template $paramod$993ac37420eaaba72705622b0561d42300ea513d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. Using template $paramod$9e2b3514d13061595c3af5bd64b76d7b822b4bf2\$lut for cells of type $lut. Using template $paramod$cf6ab2c0433b8f9b498807313fee7b7dc115199f\$lut for cells of type $lut. Using template $paramod$bf5377eaf86588b19e52fc1c44703af0812fd37b\$lut for cells of type $lut. Using template $paramod$b7a0a32ef8f8e73ab8160d2399482c0c9d5a3edb\$lut for cells of type $lut. Using template $paramod$265fcbe3a58ab11c1b5551ff7c6e80ac20b9b919\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut. Using template $paramod$0fcb06ed76df01e8d45bc2b9e6c8a9b43fa42cb4\$lut for cells of type $lut. Using template $paramod$ea8431eb36f5b8e4b1d51aa5d6313e07b1cf6856\$lut for cells of type $lut. Using template $paramod$a5e3ddb8fcac262e734b9c601fc99d9d1679e5ea\$lut for cells of type $lut. Using template $paramod$f1a66c797a04ffa3622e23bbd2ca1675335789ae\$lut for cells of type $lut. Using template $paramod$e84e4a245515000cd6930e0f4535753ed485f71e\$lut for cells of type $lut. Using template $paramod$f367ee5b59f977a78b21f21683c676ecb4a9ded7\$lut for cells of type $lut. Using template $paramod$e732a470232be3815aa17b1838622260b1fce8bc\$lut for cells of type $lut. Using template $paramod$28a7670e6becaf66a416aceafdbfc8189bc2d4bb\$lut for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. Using template $paramod$cb63a6e25879a415b84a2418577cc471d6e8d208\$lut for cells of type $lut. Using template $paramod$f6690cde0967f912a64bbcf13aedf0c6a76e680d\$lut for cells of type $lut. Using template $paramod$14ad398798db36ba266fc738fbb4b42f0bb4b077\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. Using template $paramod$4a285d83dd4d34ef5222dcefece6b84f861d3d30\$lut for cells of type $lut. Using template $paramod$1c43b39f35f8ddd9b4aed7cce6b72309a3a719ba\$lut for cells of type $lut. Using template $paramod$346842b88e407bf40d83dc890111dffae3530202\$lut for cells of type $lut. Using template $paramod$0211326fe717a1a6c63d9a7869ee144af6ef7e63\$lut for cells of type $lut. Using template $paramod$55668dfd6e901cbdb37e2cafeb410b9fc2f26615\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. Using template $paramod$081e1bdace5c74316867edb86125eec472d5593e\$lut for cells of type $lut. Using template $paramod$6ec3541ea2fa300cfcb514acbaf0c968cfe55a71\$lut for cells of type $lut. Using template $paramod$fe07503be663f9fa136093aa0dea361797ccf48d\$lut for cells of type $lut. Using template $paramod$2014354416722209de7d48370ab008bc2278a034\$lut for cells of type $lut. Using template $paramod$34bf8396dedca6de7f3bf9d87c78bdf264336eb0\$lut for cells of type $lut. Using template $paramod$325e90edf97670f9dea57833ae1f51a5e8bcddea\$lut for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut. Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31\$lut for cells of type $lut. Using template $paramod$855b2c1d6931bc7ac39a5e8ecd8eb6e90ffc6baf\$lut for cells of type $lut. Using template $paramod$ce2313fe337ae8e314a09fc487d4f3c6e1649ed9\$lut for cells of type $lut. Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95\$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod$ff28390cf6454ab7c79b16bc98dc7c8c342da668\$lut for cells of type $lut. Using template $paramod$2e11c0e004fab0373ef80005c65c968bc830b55a\$lut for cells of type $lut. Using template $paramod$e7fa614e5178313a520a3507bd4b759724bc7c45\$lut for cells of type $lut. Using template $paramod$8cac5452d526045503c5864c3a1dac0121c7053e\$lut for cells of type $lut. Using template $paramod$526aff5d8d90bb2e1cf8fcfb9d98f6f0b7d2fa0e\$lut for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. Using template $paramod$430ff3cc137087db51245fe4f94d99755d044b30\$lut for cells of type $lut. Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut. Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. Using template $paramod$cd2eb242e3aed6e464645fe650270f6e9a199e19\$lut for cells of type $lut. Using template $paramod$e9b060c9e52ad8d656b56fa01b49e386848f2a01\$lut for cells of type $lut. Using template $paramod$d7c515d45342dbb94dad81c7db9f1da827f03a1e\$lut for cells of type $lut. Using template $paramod$1114d560ed98e9182fe073c9893577168d869f6b\$lut for cells of type $lut. Using template $paramod$60a3dd1eb5ee49197e27c7336a341ee771404249\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut. Using template $paramod$6565e92242a21f5338d449de809baa175c228bcf\$lut for cells of type $lut. Using template $paramod$1be3a10aca64bc8b3d140a9dcfb9bac7a6744be9\$lut for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut. Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut. Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut. Using template $paramod$71d09d8354f5555fb54ab0bd4f3934a22c793990\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$3e63470ea7a06b3eefdfb990254dd83d20fa13a7\$lut for cells of type $lut. Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut. Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5\$lut for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut. Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut. Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut. Using template $paramod$c66e7b215e6f80c1915bda1df6f2ae95d0bda68c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$872def176acf0af46aee1a4df67a9291309e3c01\$lut for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod$bb4fff1cc3b827238aa40993cafede1c5beecbe3\$lut for cells of type $lut. Using template $paramod$0a4d85497e20c50068555dd5ad9ad3a7952cab73\$lut for cells of type $lut. Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut. Using template $paramod$a8b9523b256193b8ef4d76806da37359144a62fd\$lut for cells of type $lut. Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut. Using template $paramod$c11ee6bbb8d9fd9cf391261624c378fb45e86b84\$lut for cells of type $lut. Using template $paramod$aaccd2b1126a9e80bddea82275abbddfeff70b91\$lut for cells of type $lut. Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. Using template $paramod$e6062a78edaf68ec0dbea59d4c8352dcb2ce0366\$lut for cells of type $lut. Using template $paramod$cd461c672ed9688c18a7c8a3d5efd5e8eb1d5c81\$lut for cells of type $lut. Using template $paramod$983adbc56c7400f95b406f02e82bd0da8b98fd00\$lut for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. Using template $paramod$ec6c71d259df49ae0842190ffaff1179e43a8db4\$lut for cells of type $lut. Using template $paramod$63d4ada4a7f6667f71a49c04ea0126d369f71104\$lut for cells of type $lut. Using template $paramod$23b135911b7c14b5b19b5329e5903bcf58b44188\$lut for cells of type $lut. Using template $paramod$cc08dba3aac8677e797984bdf18a09dd37547dd3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$68f8a3050868da669d94d4e494c893d3dce59229\$lut for cells of type $lut. Using template $paramod$bb52033fa4a868a3e74e1b8840db1141cdc85231\$lut for cells of type $lut. Using template $paramod$adb84e058b0f32ce56f004e6ffa19883ace75fc0\$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$20f3f4b8e32f8a8b038b0056872dc94926194798\$lut for cells of type $lut. Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673\$lut for cells of type $lut. Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut. Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut. Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad\$lut for cells of type $lut. Using template $paramod$f12fe2ef5af134a926cc7292d32ee6988934ef95\$lut for cells of type $lut. Using template $paramod$19451f719aa4a75f15cb977ed4212a1c1a1550e9\$lut for cells of type $lut. Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut. Using template $paramod$c0a4d9417755c1bd5ec9a311325000b8535d91ad\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut. Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut. Using template $paramod$c6a1f9ea79b7bb1672d5d3c63312684d0f3defb6\$lut for cells of type $lut. Using template $paramod$98e99942f364173ee1da9b31f34c7829f11e4be1\$lut for cells of type $lut. Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut. Using template $paramod$51f1ade31abf23f14398d32ccd5a4b830c207a31\$lut for cells of type $lut. Using template $paramod$9b22a1c705c95b6d76d13b5d826906777087290e\$lut for cells of type $lut. Using template $paramod$a778c0a17dd7f7ee20a881578cbbe6a72ebe3b3a\$lut for cells of type $lut. Using template $paramod$dd98204080bd8c9fba759686fd3a1998881d3016\$lut for cells of type $lut. Using template $paramod$e943b0894861e8179e80496d033f3cd541bb6ccc\$lut for cells of type $lut. Using template $paramod$c42ab8d3a0b4f503e2527a4e01b91570a4655ee8\$lut for cells of type $lut. Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e\$lut for cells of type $lut. Using template $paramod$cb32832b462590ba6b4bda2fe4ab0e2da1abc198\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod$3b43e9fbeacef60edfff2e6ed76202ebfac75384\$lut for cells of type $lut. Using template $paramod$1718b78815c197f9cf63419425bee170c76e82fd\$lut for cells of type $lut. Using template $paramod$9fc14cb0ba5120a1da0c687a9fb19472f206fdfe\$lut for cells of type $lut. Using template $paramod$b8c58492c0c5a328af9d8bee395ae322f11fd1b8\$lut for cells of type $lut. Using template $paramod$18fa685a8cdb30eb6c664aa12d728a07c3fe94f1\$lut for cells of type $lut. Using template $paramod$25696d6b21c8ac3da9913114964545779e21cfa5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut. Using template $paramod$c347afbc85ad8703191dacbf5d3590fe54f2e1f8\$lut for cells of type $lut. Using template $paramod$1b4942fad7257f60532954b1eb94a6b84f2e5ae3\$lut for cells of type $lut. Using template $paramod$6375ab94b303a3f3c8d7ca6946328cb3c0b443a7\$lut for cells of type $lut. Using template $paramod$03689da3fbbeab024e5566b38a26f33b669495fc\$lut for cells of type $lut. Using template $paramod$b26fbfdb68e98cf016d61a8611b449e9f4a30f3c\$lut for cells of type $lut. Using template $paramod$d3e8d5ab09bd6b90ac4faa541356d61263b24ae4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut. Using template $paramod$8c14e6d85060218e346675600ae1194fdf5a803e\$lut for cells of type $lut. Using template $paramod$46f7e44fb5d42c7c6e4c2d1915650ac9397db4dd\$lut for cells of type $lut. Using template $paramod$a5585a0d7d274785e9b965eebc7d3a8d39a0d415\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$9c431b511c06506f9a1ef92ce73352313a62b2bd\$lut for cells of type $lut. Using template $paramod$7ca4db46d3cd57dbe2541a389808e6d33af02319\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$fdb7d2f78b1b1d86177579c82e917e4e8af6f77d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod$9cf83e29ae1c8f8c5630302af14d44e670567a7f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut. Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut. Using template $paramod$a4bbe892a28ec0471eac4c548ab7ee6abbaf1e36\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010011 for cells of type $lut. Using template $paramod$bf8a2eb9c34204449ae734db198784b474646269\$lut for cells of type $lut. Using template $paramod$cd49814a234917c3b75448e8be5758d0b107ac14\$lut for cells of type $lut. Using template $paramod$87cad75e5228984b6c2387055450005570b7eea8\$lut for cells of type $lut. Using template $paramod$a101bd9a2a1ab198123948013754530dcd77ffd7\$lut for cells of type $lut. Using template $paramod$c6587c257053203589954461feadb4a6b5bab3a7\$lut for cells of type $lut. Using template $paramod$b55f45c6dc20e6c434e3ecfaac16a92e424cd4fe\$lut for cells of type $lut. Using template $paramod$7746ff5418ce12be74ba995961deeea23e22fd34\$lut for cells of type $lut. Using template $paramod$b3ec6a524ea54feed121c636221e0302f73dea73\$lut for cells of type $lut. Using template $paramod$c5f689f2cc5714dbcb5935134009503adac12228\$lut for cells of type $lut. Using template $paramod$b88b11befce1f2aecefaf907fc5e5a42df806c8f\$lut for cells of type $lut. Using template $paramod$dfefbb1b1f9830381bd1f2abdb50df152af16edb\$lut for cells of type $lut. Using template $paramod$497729093b478f74524f49c7e6002e94c7200c7f\$lut for cells of type $lut. Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$5c2d177c7af3274c403cbda2fdb5c77f74ae1fc6\$lut for cells of type $lut. Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. Using template $paramod$928de89363c1709229b8424c852686f29a7adbd4\$lut for cells of type $lut. Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut. Using template $paramod$717f66aee89077840479c83a1f79be61fd139731\$lut for cells of type $lut. Using template $paramod$14156b2616c16a10f2581287a57d3343ee88c698\$lut for cells of type $lut. Using template $paramod$3d420c45fcaf200a454408122dcbe0a4f1f1628e\$lut for cells of type $lut. Using template $paramod$200337237619ba4c0bed9a492562f1d1b57fb569\$lut for cells of type $lut. Using template $paramod$5f69790c19b5e35c1c6c7354854d5628ca59cfcc\$lut for cells of type $lut. Using template $paramod$a9ba23df824f693c44e722629fd8c1fae157385c\$lut for cells of type $lut. Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut. Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut. Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. Using template $paramod$d9922e15eb5da1acc26e937540cc16b16c2ad42c\$lut for cells of type $lut. Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636\$lut for cells of type $lut. Using template $paramod$71165c7cf8df0ca3c003bcbe5e9c5847fe57731c\$lut for cells of type $lut. Using template $paramod$74c0f3179b5cebe485563ea55e9b637e7ee5c0c3\$lut for cells of type $lut. Using template $paramod$c6a0421f5b5114b68e9782f0585d571421cf8f01\$lut for cells of type $lut. Using template $paramod$ec31065e44bb1d47aaa43a1c21125b869798b46b\$lut for cells of type $lut. Using template $paramod$0f5c4dc6f92c3c6ee36482a209be300a0cac5e25\$lut for cells of type $lut. Using template $paramod$afd7b4c177a33f5eb62789d24240afa93e05edd1\$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut. Using template $paramod$0bbab37fcf0302437391fe05312563764a35f7c5\$lut for cells of type $lut. Using template $paramod$2357431a20f3891da5d1d21801bc815b057e2dac\$lut for cells of type $lut. Using template $paramod$693533864dcce883077306c74cc9c5d64da5eb6b\$lut for cells of type $lut. Using template $paramod$a6300eee50d6e3db53201022f689bb749e0ff001\$lut for cells of type $lut. Using template $paramod$f48b506ee4bc344bff5930bdbbabde68f446d1da\$lut for cells of type $lut. Using template $paramod$b76eeafe3553c6220aebff28fb37e7d4bf1fb01a\$lut for cells of type $lut. Using template $paramod$9506ecf18c91672f3dae4008b6ad1f2863e8019f\$lut for cells of type $lut. Using template $paramod$fb0de4ce305f5626f53c946b949e3067844405a5\$lut for cells of type $lut. Using template $paramod$a197ef6f3b51d411ae3e5b42b5d77a606c4fb11a\$lut for cells of type $lut. Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c\$lut for cells of type $lut. Using template $paramod$6b725f2a20f58e0af3ec1b3e0ff505e4f5b53fa1\$lut for cells of type $lut. Using template $paramod$c52825d0b1a0cfc6362b36af6d13149a97d3e424\$lut for cells of type $lut. Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa\$lut for cells of type $lut. Using template $paramod$e4b832d686d12318ec0715f027fe549b42e45c20\$lut for cells of type $lut. Using template $paramod$14bb3051777a635b2133d8d300420d8e821ee7e4\$lut for cells of type $lut. Using template $paramod$133d442dae750c43071369608380feab91f2bcef\$lut for cells of type $lut. Using template $paramod$3fb3f0de5b347667e45afe024bcf37620e184335\$lut for cells of type $lut. Using template $paramod$6997c909e8db9e06d010d7b1466996d74d8b8d9d\$lut for cells of type $lut. Using template $paramod$9c54389ad71aa60459cfd845237c3c82bd0fdd80\$lut for cells of type $lut. Using template $paramod$c32a5f802076a0651f7a90b14bae6a3ddb70e76b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut. Using template $paramod$c9d86860d7b8a94fe4e147db4941c14e73dd3281\$lut for cells of type $lut. Using template $paramod$d76a082ac65b735f66c3b6bca13712f41180defa\$lut for cells of type $lut. Using template $paramod$ead66ba22839f96e739c8f1b5a09bc1717b3be02\$lut for cells of type $lut. Using template $paramod$a82a699dba54b8465366aeb90aba90d3d29adde0\$lut for cells of type $lut. Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut. Using template $paramod$e7d7e0a998cae7a42b7e98c757d2fa0c66ecec86\$lut for cells of type $lut. Using template $paramod$c1b1e295769db1b6655cd9fa7f1823a266fa6d67\$lut for cells of type $lut. Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut. Using template $paramod$2e4c0c237c045ff8ceaa73482bd46eed54bf8d8c\$lut for cells of type $lut. Using template $paramod$d68c955eab3e0ff857c6b60afe14ca397531beeb\$lut for cells of type $lut. Using template $paramod$10adeab64d84425a03f997a91bad07511719ed14\$lut for cells of type $lut. Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4\$lut for cells of type $lut. Using template $paramod$96bfa5dde5d069b8b26422d7ccfc428bc429d12e\$lut for cells of type $lut. Using template $paramod$c6c8aaf71df0998bf3ec6b2b78bcedc4ed24a6c4\$lut for cells of type $lut. Using template $paramod$1c740251f477df8cb0ebf6cde6641bf0c6d0842e\$lut for cells of type $lut. Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut. Using template $paramod$6f43b0740333ecccb50397cd6888e79f622019d3\$lut for cells of type $lut. Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut. Using template $paramod$aefdc08ea82ee57c767b4cec3efc09bfeef4c872\$lut for cells of type $lut. Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut. Using template $paramod$72d04cda0ad63fcea17225ad4256bc664683b513\$lut for cells of type $lut. Using template $paramod$25cf967f6f7a20c5f5225a9bf423f0bd7295a899\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod$9012351afa37f8c21b210fcb3832dc6e8fd1ab09\$lut for cells of type $lut. Using template $paramod$669a5c8d4e17b4c876b0432af0fe1a8845edc8a3\$lut for cells of type $lut. Using template $paramod$7d5afe14dbe63bbcb001b9ac9ac12f8f5941dc33\$lut for cells of type $lut. Using template $paramod$f8e1bdecd38a1f2a88371fc52b96bff86506a2c7\$lut for cells of type $lut. Using template $paramod$d53578aacfd93124244778d88be0e90eb09c1b1b\$lut for cells of type $lut. Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut. Using template $paramod$52052e62080cd55554d8b6d62f7da8c69ccd50d3\$lut for cells of type $lut. Using template $paramod$a648edd7290dbdc60b4277769ac1653dae6fd74c\$lut for cells of type $lut. Using template $paramod$44c0fe996e6f3f4ba8bae2e194245aa82c30fa47\$lut for cells of type $lut. Using template $paramod$288fccbdccf9b79dcb83b6c42fd2ca69b5839c14\$lut for cells of type $lut. Using template $paramod$078db3dcdab00c5525715fc651615331bbb90453\$lut for cells of type $lut. Using template $paramod$0d6d8bcc141770d0e81988ac647361cba26a9296\$lut for cells of type $lut. Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut. Using template $paramod$323dbb47a6d14615772fecb6fe7c4bec277e6c6b\$lut for cells of type $lut. Using template $paramod$4a14e79756b08a1d692476c2348ee927a696f65b\$lut for cells of type $lut. Using template $paramod$58b33073d6510d6145ff01c28a604d07765b1342\$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. Using template $paramod$4fca5f405a3ded126a54c23f508d7fea5abd1989\$lut for cells of type $lut. Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut. Using template $paramod$9a6dbbcb198d127ed5f43662b90eda25a1c893de\$lut for cells of type $lut. Using template $paramod$3a2cef7720741fa70f359f342fe97875ab2b0e60\$lut for cells of type $lut. Using template $paramod$b7712ad66490a50bf0f0eb1278d478652991d6c1\$lut for cells of type $lut. Using template $paramod$903905cca899aab473483ca27c3db12d7108e3a5\$lut for cells of type $lut. Using template $paramod$4134cc5667d7df2f7b2f67ebf078beb2bcb94f95\$lut for cells of type $lut. Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut. Using template $paramod$c76a8516cecd83b0adb91390511f63a9b6d12fc5\$lut for cells of type $lut. Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut. Using template $paramod$59e5468f3ee6bcbff4ad8c12f8c26700b852ec5c\$lut for cells of type $lut. Using template $paramod$d293278ea85effbafba328cd7d53cacddff56bf0\$lut for cells of type $lut. Using template $paramod$794fc707eff728f4255fe7b40b71979d112bd9de\$lut for cells of type $lut. Using template $paramod$6e84d22ee7c2a4c38bea6ef32c294e3f7fa51831\$lut for cells of type $lut. Using template $paramod$30ccc2d02d561628bd3e8ba21431cf11015685a5\$lut for cells of type $lut. Using template $paramod$ea5280fce2698f0f291737e66fca69a1d9d058e1\$lut for cells of type $lut. Using template $paramod$3ccc54aa62f713851fce629165717bed582b875f\$lut for cells of type $lut. Using template $paramod$0976fedf1659ca5382d7bd92b0f47e685ad59bfe\$lut for cells of type $lut. Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut. Using template $paramod$d5295423ddd22a2d117b1665e8f6f07a6eea42ec\$lut for cells of type $lut. Using template $paramod$c34cb94cec4e7e499aad09a3dff04b1581cf7f5f\$lut for cells of type $lut. Using template $paramod$9ab812a93ab4179cf6e67b879ba197f32ce6f16e\$lut for cells of type $lut. Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut. Using template $paramod$cbb2dfe31d344d3326d567c2ed5a4b2a29f63219\$lut for cells of type $lut. Using template $paramod$7f937f9b61bf542e3f85320ab27ebb3043b4337a\$lut for cells of type $lut. Using template $paramod$828fb0a3098a1273e4ccb049c3c47b7fe60ffb17\$lut for cells of type $lut. Using template $paramod$348f3081ded702ad82b59de5e9de9edc3a7fe822\$lut for cells of type $lut. Using template $paramod$744595302019fbddbf4bb69eba7396d67b1c962b\$lut for cells of type $lut. Using template $paramod$b8dcf181aa65a78b16931a8a90db592676f14a35\$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. Using template $paramod$41ba493959df7c855a1072fbfbf5d900cf13ce42\$lut for cells of type $lut. Using template $paramod$a05170b3f2d3fcb0bf88d37e810984e864962880\$lut for cells of type $lut. Using template $paramod$a238bb199d4b53d4c976c9e68dafcfe86b19f40f\$lut for cells of type $lut. Using template $paramod$b33c06a15b82c3e1c0047f7b3ede69d098f1a571\$lut for cells of type $lut. Using template $paramod$11c86b7a6cb6e98dcfb16c5f4d4cc1052b93d8a4\$lut for cells of type $lut. Using template $paramod$69f79d8ba7203c383d96ac8e821ddf28918012ac\$lut for cells of type $lut. Using template $paramod$e234b33fd72932ba3f0d727e277c697708f63208\$lut for cells of type $lut. Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut. Using template $paramod$b8d276a7eb687b23e60c3ff49ec8000f2ccaf105\$lut for cells of type $lut. Using template $paramod$aeb27cd9efe624def2282ecf09671da132bf31e8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111110 for cells of type $lut. Using template $paramod$7a7a6dcf0756c9d59a91abf38c301d219a65c59f\$lut for cells of type $lut. Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut. Using template $paramod$bc4348b39db21598a89efc3173a4fd7990143f65\$lut for cells of type $lut. Using template $paramod$cd9c6569d01df8505e03a274d799be758732d8c1\$lut for cells of type $lut. Using template $paramod$dc801840eeaf83fdf99128871ec5a9f7070474ca\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut. Using template $paramod$423b68a7f69023921171384cd2d3c41589bfe637\$lut for cells of type $lut. Using template $paramod$8d917a5cddbe3325c6401f7d427ef609dd462aaf\$lut for cells of type $lut. Using template $paramod$8f2db6b8c04ce5ad1e643c3970f4071ac9f9c455\$lut for cells of type $lut. Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut. Using template $paramod$2474607ae544a71944626525d6ae11f1a2baa308\$lut for cells of type $lut. Using template $paramod$84abafac600770dbecbd08e858f90b0a8d019d50\$lut for cells of type $lut. Using template $paramod$0a7817d70895c67313a5df1d76db8357ea7a02a0\$lut for cells of type $lut. Using template $paramod$93785b9c731eec5233cca020cc98b38141190c08\$lut for cells of type $lut. Using template $paramod$c982fc47f348fad396f27b7d5b32546d77327e85\$lut for cells of type $lut. Using template $paramod$ffc80aea4aa44f0166b2d4713ba5912f56e92991\$lut for cells of type $lut. Using template $paramod$d6a246575d0ba3dcbbccd768ad41b602f82ff057\$lut for cells of type $lut. Using template $paramod$b3566c182f404e640146bfd5c5f64dfe4a7bdc9f\$lut for cells of type $lut. Using template $paramod$72e42a096e83f33d00ffad3059e360b5336e0e98\$lut for cells of type $lut. Using template $paramod$734cd1512f671d92bc4f41153da0d9781801dd98\$lut for cells of type $lut. Using template $paramod$be6ccd636c27dfc8a5f20cc84664884880c07417\$lut for cells of type $lut. Using template $paramod$29a0b2f86d2b7a2a2a576ac1ab2bffea635065e7\$lut for cells of type $lut. Using template $paramod$3d0255c404f5260ab9b3caadee9c0aa9fb75cc63\$lut for cells of type $lut. Using template $paramod$c92d19f87f844daa49aa248d8693c365cf26e240\$lut for cells of type $lut. Using template $paramod$27365707c3fa509b7974736419be4f1fe5f00a20\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut. Using template $paramod$30604b87c0fa3124b3f769f4b6c8ebf454070478\$lut for cells of type $lut. Using template $paramod$f921ab2c451d17e196d1dcad0b6d434881387fe3\$lut for cells of type $lut. Using template $paramod$5a08224d27f6506e23571e2fa65d9e96d4340aa2\$lut for cells of type $lut. Using template $paramod$d3d9ee09da3b1640b1bbab80cbf28a3f3e577e57\$lut for cells of type $lut. Using template $paramod$84bef48419505c45080a829b4c4b6379a157eb8b\$lut for cells of type $lut. Using template $paramod$ff74d3b36221c7c7b417c242545ab45c7d96a8ff\$lut for cells of type $lut. Using template $paramod$d17142a673b249da2c9ee65ab7454d9b4c169e7e\$lut for cells of type $lut. Using template $paramod$864ac88ee2e2acdd75dde3881e41ad89166a58d9\$lut for cells of type $lut. Using template $paramod$14efcae0e4bf753ceba5732add425ba401e27e83\$lut for cells of type $lut. Using template $paramod$975ff82b49afff6f152a2206f593fcb70fef6026\$lut for cells of type $lut. Using template $paramod$7058ad23c7aadee3f0e72b9e81092f725bf8f7e1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut. Using template $paramod$fb4ed309581bcd972f41afa8566ae8b9812c7f6c\$lut for cells of type $lut. Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f\$lut for cells of type $lut. Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut. Using template $paramod$9d6b7412f96be7d57bc9a97516a54e753744c7bd\$lut for cells of type $lut. Using template $paramod$12644e0586b19b6dbc4ef139f21c5e9b52a0ad12\$lut for cells of type $lut. Using template $paramod$4cd535c6fe71868affedbe4f7ccdb6859410c959\$lut for cells of type $lut. Using template $paramod$aec61619bef8dc35dc4826da2ba3cca5b04dec66\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut. Using template $paramod$3a2cf6122dbbdd8a600ba04e4c348c13e0f40b2f\$lut for cells of type $lut. Using template $paramod$5b86013103f2e3b8c377793851b53e09a4f50731\$lut for cells of type $lut. Using template $paramod$2b96574b4deafdd87964a849c20ae6b8ce313996\$lut for cells of type $lut. Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut. Using template $paramod$17fd36fab32bce162e5828682c2ba9fa7f9e273b\$lut for cells of type $lut. Using template $paramod$56651ab87cca494f90fbe224456898331a8065fe\$lut for cells of type $lut. Using template $paramod$ffd2daa816943d98d4befd944c0ade9f965da2a3\$lut for cells of type $lut. Using template $paramod$b92b5bde2d596c7853a529ac0e854d9c5db0986b\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod$cbe921739767270a5242fe1efa995c0c059bfc82\$lut for cells of type $lut. Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut. Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut. Using template $paramod$8ba8c1445f2a4422ef36a349554d5680f0e94404\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut. Using template $paramod$742586fa5879da03875f2a6a245f247e65e07ee0\$lut for cells of type $lut. Using template $paramod$a9ade96259ee1af58b7ef48d4714815a6611d062\$lut for cells of type $lut. Using template $paramod$3ac2c0f89fe9b6bdcccc07e049e36584de660216\$lut for cells of type $lut. Using template $paramod$141842c6d76be03c45a40fc50b616548745ab5b5\$lut for cells of type $lut. Using template $paramod$617fb8b8c6abf54315af0410dc775ecddb0c2246\$lut for cells of type $lut. Using template $paramod$4abac05ab829921eae8ddb6c2fe50ac642f441bd\$lut for cells of type $lut. Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut. Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut. Using template $paramod$99887f1c2e5a03e8f2556cde39da8462d14d511e\$lut for cells of type $lut. Using template $paramod$5def6e43c43562078e7d5da26b03e2771c7a5557\$lut for cells of type $lut. Using template $paramod$77710f7ae7b20f77f16b1eb4652da5735e1928d0\$lut for cells of type $lut. Using template $paramod$b6c45f8ba9d325a7b4ae042c8c22a8ae2a2f8a9b\$lut for cells of type $lut. Using template $paramod$90e6d188250469b4f88e9a7feec807353cf7bdb6\$lut for cells of type $lut. Using template $paramod$d3b4003a49cc631c440050b7c68facb2fd644569\$lut for cells of type $lut. Using template $paramod$ee786ca2d564f4b83d01210e297501b9b38ee4ac\$lut for cells of type $lut. Using template $paramod$ddee715beb479c33246354b3331262a41eebdf7e\$lut for cells of type $lut. Using template $paramod$4bd4d1a8a9e346a94507f65b9c1ebde03fcad485\$lut for cells of type $lut. Using template $paramod$57fb39de369415507243314d0ca9b4dec36bed6f\$lut for cells of type $lut. Using template $paramod$72b18ed199cee87ac67c32429378420c34b8db80\$lut for cells of type $lut. Using template $paramod$ebc96d54c58bc295ed1c25971281979887a5ca05\$lut for cells of type $lut. Using template $paramod$f613b8a46d0d9fff817a986e39c342586bc49509\$lut for cells of type $lut. Using template $paramod$57679a36545b618a407a56157de647f8c7efc6bd\$lut for cells of type $lut. Using template $paramod$4b5390143765863dd4ad783d9a1665072f814613\$lut for cells of type $lut. Using template $paramod$0a9be70349ed7de4a28bc66714012b19eb899f8e\$lut for cells of type $lut. Using template $paramod$bea08a495d16293f8cc454a45845d26cde0762b6\$lut for cells of type $lut. Using template $paramod$bbf8c65f00b09f2cf68e6ca5410fa9a0c7a5e2b9\$lut for cells of type $lut. Using template $paramod$7f613862e76f5e365bb417d0d96fa5318ed3cba7\$lut for cells of type $lut. Using template $paramod$0f1054d7a869eb1bffa14eab6537eeff64eb55da\$lut for cells of type $lut. Using template $paramod$e5a7589d84437741870cf13cab7d51bd58be93ec\$lut for cells of type $lut. Using template $paramod$7a0b348a7069d0c8f44afe945e212fcf3f3fd64c\$lut for cells of type $lut. Using template $paramod$a2ed6a4dd24bc44ff58e69442ce51f5feb0937e9\$lut for cells of type $lut. Using template $paramod$95e3af1ce267c2242685f8bd2338d86a179ec7b0\$lut for cells of type $lut. Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut. Using template $paramod$b9c8e0f16e659e340c2be7deef54502a581b2004\$lut for cells of type $lut. Using template $paramod$189bf9f245b75d9f2b69b381ede2eda4baeb4558\$lut for cells of type $lut. Using template $paramod$a0f84909f3ff436ecd0f506c7c01877abed14cd9\$lut for cells of type $lut. Using template $paramod$ececc55fe721b2d80098bfc00a6005f1af14b6e5\$lut for cells of type $lut. Using template $paramod$3310463a8f2f8ca885a2ed16d11ea116163e5150\$lut for cells of type $lut. Using template $paramod$bd6f1738385579a4e17b0d0038af0cd0c956c1f4\$lut for cells of type $lut. Using template $paramod$d3d2b6a5ec102f3c610e97414cb3f20b0198988a\$lut for cells of type $lut. Using template $paramod$253532b742d151c01e8e51f153c24d934b8f6185\$lut for cells of type $lut. Using template $paramod$8ebb8abdd7d9c59d2e7c6f74f49840c04318b238\$lut for cells of type $lut. Using template $paramod$d283e4d1d546b82616305ea15d9964a9be5de2ab\$lut for cells of type $lut. Using template $paramod$39d41e2ce393612a4f98b6db69fcd7eb8dc11e73\$lut for cells of type $lut. Using template $paramod$4b815e6c998e04ad0d0242e44b0c58a7a9d0b3b6\$lut for cells of type $lut. Using template $paramod$a770a58bbf55a5b518b4aab8868b6a99a50f3001\$lut for cells of type $lut. Using template $paramod$316a80854e4e81b9a9ad78bbddcbf2f8da9893f1\$lut for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut. Using template $paramod$d497222f59d990d3f689ed9c6ac453ecc8a2f4b4\$lut for cells of type $lut. Using template $paramod$8c294e395af8077fce1eb138481332c9c1d5a386\$lut for cells of type $lut. Using template $paramod$7febf92beabc81e16882a3f10047be87ba16913b\$lut for cells of type $lut. Using template $paramod$3245212823fc9dd433d12253e714868e7ecd2c5c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$6d42466d8ffd7d74d58269d5ea1c9c846c593262\$lut for cells of type $lut. Using template $paramod$bacdb2105cbfbe75cfbcc2fb021fd3aba864526b\$lut for cells of type $lut. Using template $paramod$2d18417c8888b042100473ce83692d0d5ad94fb2\$lut for cells of type $lut. Using template $paramod$e277a522d8a930c8c8c8cdb56d33d42914aefec4\$lut for cells of type $lut. Using template $paramod$0a9eb06856e79147b55c3d0c0349afae6651a745\$lut for cells of type $lut. Using template $paramod$76a45bb5412277d2821f04d3540e2e79a6895a47\$lut for cells of type $lut. Using template $paramod$962a711d8da50020ec4f3a196d5fda6045749cb5\$lut for cells of type $lut. Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut. Using template $paramod$280adc3d65115ec482e1b15979ea31e2f857b588\$lut for cells of type $lut. Using template $paramod$186d19509be55c5051ccb3e19e9d9f1d3bfe7f4a\$lut for cells of type $lut. Using template $paramod$bbb10333e84a7e80f65e1494ebbfbf3f28568fcd\$lut for cells of type $lut. Using template $paramod$0fa351d24d2713ce0a93e46f5deedd65d95d22b8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut. Using template $paramod$8d4ca37ab8d493342566358608f8bfe2f0356d8a\$lut for cells of type $lut. Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut. Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut. Using template $paramod$edfe6773e2ae95f1f17ad5bea62c0e1b079fa667\$lut for cells of type $lut. Using template $paramod$f5ec0186d011393c254459cea24571ba08de7110\$lut for cells of type $lut. Using template $paramod$389e43ee14507e9d1ff41667d687299eeebb4e34\$lut for cells of type $lut. Using template $paramod$1787ccda58a5cc8148b54583009ad9e384e8c47e\$lut for cells of type $lut. Using template $paramod$58705a0d3f211d68861905aa557c9f341df60a4f\$lut for cells of type $lut. Using template $paramod$e3c5e4de270b555fd5b553e75491e305e290adfd\$lut for cells of type $lut. Using template $paramod$f1a8f82458420077c72e67f22d54faf6d22773a5\$lut for cells of type $lut. Using template $paramod$497b717d4df93f11d39df1f45c14a51eb7808117\$lut for cells of type $lut. Using template $paramod$3ccc23db184ad4ca7ed34ebe2511de41d5d97e78\$lut for cells of type $lut. Using template $paramod$c5af5678e76c2f7359a5d42d1a07c7e309f457a6\$lut for cells of type $lut. Using template $paramod$3bd1bab9042f1dc841db8ee756acaf0d1a52476e\$lut for cells of type $lut. Using template $paramod$46f5b89dfa162bb1c45b8ce513bd0eda5958086c\$lut for cells of type $lut. Using template $paramod$c064d9f267b09049d631f66733af1b91c12aa819\$lut for cells of type $lut. Using template $paramod$25398ce4f7a98fe1fe2b7b5e2ba98d1f8da3ecc5\$lut for cells of type $lut. Using template $paramod$a51481b878721d43d7952f9e8b72ec2ca5b9d883\$lut for cells of type $lut. Using template $paramod$d690ba6e93be4ae5167969ac7042432c04995b2d\$lut for cells of type $lut. Using template $paramod$f8000fe33260f18f98877185a6d2e12a6429deaa\$lut for cells of type $lut. Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f\$lut for cells of type $lut. Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut. Using template $paramod$ff05785cf4c2405b4031fe11a4b329b0d701ff79\$lut for cells of type $lut. Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut. Using template $paramod$90ff8a59949ebefe7489e66601d91f4c2be568b9\$lut for cells of type $lut. Using template $paramod$e4e09968bccb8665ed1d2532c6979f937ac17a70\$lut for cells of type $lut. Using template $paramod$eb6dfd98d38c1cd1b4ab51cd3cc181968d383b7e\$lut for cells of type $lut. Using template $paramod$682a880a2c6363427a46af490189fe31ea1662ab\$lut for cells of type $lut. Using template $paramod$7425d6b117f514d343b9172026ed9ca0b449e677\$lut for cells of type $lut. Using template $paramod$df0f9ff68a105cb1700f706ba4247e741f84656d\$lut for cells of type $lut. Using template $paramod$612a36b8ed208360b5a9f1b4119ff0e83e0a1712\$lut for cells of type $lut. Using template $paramod$1632c1c0242796acfc963a05742c4acd2f475c4e\$lut for cells of type $lut. Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut. Using template $paramod$66933ac98238f0dd23b144826c387b20f30edd68\$lut for cells of type $lut. Using template $paramod$81cb5e29c0effa00451047ceba953612eb78f254\$lut for cells of type $lut. Using template $paramod$bb91a41b6c6e90c9de123b408208c402cb3d3d4b\$lut for cells of type $lut. Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut. Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut. Using template $paramod$8c13ad014d500c3a349fa680995aa7f6f9eaaf87\$lut for cells of type $lut. Using template $paramod$dd860dc915df955be7c55367504d6e99660c7b0b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$1e9d7896e1dd3d2af9633eefc9c29afb478cef41\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut. Using template $paramod$01d6171b877f7655dc0d32e32900a6a207a75b44\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut. Using template $paramod$cd05f04889088c47a0a5abae8c2d644fd314805e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$21f957a7073b1ba634cad0df400394ca323de2fc\$lut for cells of type $lut. Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut. Using template $paramod$354f3ad2016291685024e599e50228612f67e554\$lut for cells of type $lut. Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut. Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut. Using template $paramod$ba1896d66a423e98734f1413876089b255b9a5bb\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. Using template $paramod$5bee13a98e3ca756fe6f0542c76597a5e1533050\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$1bbcbaf30677779d17245c2d62cb0b764a8171b2\$lut for cells of type $lut. Using template $paramod$a124ce6d1ab58c2524d129a6888fc586cd9c7243\$lut for cells of type $lut. Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut. Using template $paramod$42c7f7e0577b90a637faf761b61988640dc1e9f6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110111 for cells of type $lut. Using template $paramod$b39e300df428358845e8c44731004b2539b39f9a\$lut for cells of type $lut. Using template $paramod$f6c04a767ded70f998bd40d5f40315b4f4c4ebb4\$lut for cells of type $lut. Using template $paramod$8ecd04460b81fe9cd26e937976886e7f3ab33e9e\$lut for cells of type $lut. Using template $paramod$bf9d676dd5a15572d0e69198dcbc06929c8bebe6\$lut for cells of type $lut. Using template $paramod$179bbca2dd7fa841ad12e8b0327ef61d6e9a7bc3\$lut for cells of type $lut. Using template $paramod$98b6c97c34eb5a34b24dd0ad7dc5f81c98ba3d01\$lut for cells of type $lut. Using template $paramod$535894650e163be6d7ba33c318478229111914d3\$lut for cells of type $lut. Using template $paramod$17c27ffdda03355f95b2ba5edc73ca082237c935\$lut for cells of type $lut. Using template $paramod$ed89e5bafea5a44fb72d3e7d06b38b80c2d83edf\$lut for cells of type $lut. Using template $paramod$1cf9e525e0d1deef780607055dc8eb9d2e7ed326\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut. Using template $paramod$e76779fd0aff146fdcbb917367fc19054812bcda\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut. Using template $paramod$0932931816a8bff63a4f2c13710e8df083d7cc0c\$lut for cells of type $lut. Using template $paramod$d10f9a84f94c1fdeb995fd3fe4295157e882ad0b\$lut for cells of type $lut. Using template $paramod$1fc816a69c7efc5bd6d94d2b5d76fc9589c4ff07\$lut for cells of type $lut. Using template $paramod$a1a52930161efb3548b305235290095b0bb0b543\$lut for cells of type $lut. Using template $paramod$75020cdf7715bd4a5f7067d80cafc74eabba6a01\$lut for cells of type $lut. Using template $paramod$a707fff23748f6aa14ef55b3ae1f771b0f87b0eb\$lut for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod$0ea9f4e845e52bd7830962784cc82631df5269eb\$lut for cells of type $lut. Using template $paramod$f9b715fbf1040e81e900b2461c2390d17ed5e988\$lut for cells of type $lut. Using template $paramod$34536926332939882b8ff52380fffc08ed1f405f\$lut for cells of type $lut. Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut. Using template $paramod$432e4e01d71b10f1550b48be5a824f4f5138a82c\$lut for cells of type $lut. Using template $paramod$7c9eec7a1ce5f22a1bd81debb84224b99efc1f37\$lut for cells of type $lut. Using template $paramod$044a0ce14c07f8137d92adda275c82e8782a2249\$lut for cells of type $lut. Using template $paramod$a59854b679c443f21a6748ea460109b8241cb007\$lut for cells of type $lut. Using template $paramod$b637cf4714c2e93484bb499728e176a6ab69c910\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$c64dec5f9cba92e7fb1a4ba3987a6ac85d9a3898\$lut for cells of type $lut. Using template $paramod$505ca6f83efadae0442899a08af73f5288142a52\$lut for cells of type $lut. Using template $paramod$9664b2f5fd61944d7798b30cde43b99ccda87303\$lut for cells of type $lut. Using template $paramod$034a69dd110db95ee917f313eafd6833fc6595f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. Using template $paramod$1b9112879b44d8bd06bb18f745e1efd8ce977eed\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut. Using template $paramod$02a84e953c934e9642efdb93d82c4cd5e0545198\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut. Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut. Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut. Using template $paramod$df52426f17762463b0f4c570355d1f823f6f99e8\$lut for cells of type $lut. Using template $paramod$ed10455c824c2a3761aabdeb1e31dad905f66e6e\$lut for cells of type $lut. Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut. Using template $paramod$34daa51327b25c1c5f097db6388cbda2579c130e\$lut for cells of type $lut. Using template $paramod$c24d0e2a94559837d969df5b5aaf84188feaf3d8\$lut for cells of type $lut. Using template $paramod$eac5ed09855cbfd5e73aad679d92627678c878a8\$lut for cells of type $lut. Using template $paramod$c3f75fc9267eea5defcf6d50165c44336d4674aa\$lut for cells of type $lut. Using template $paramod$00e62bca7a10ca0e4ac1f68f81e86362ca44ec30\$lut for cells of type $lut. Using template $paramod$833582361e14b3ee2e66ad676022ab35d7aa7e28\$lut for cells of type $lut. Using template $paramod$6fe34497620f8f4f756f16a037c2550db7a0a0b5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011111 for cells of type $lut. Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut. Using template $paramod$0012980e339f7e11d6853e1ba5b63cdb507326df\$lut for cells of type $lut. Using template $paramod$716ef06fc021a8e7f1011751bf36a7bc77cb5227\$lut for cells of type $lut. Using template $paramod$36a9fdea78660cfe315c27f5513f1b18d4a42960\$lut for cells of type $lut. Using template $paramod$70f68cc10fbeada9b6fa90c3bb75475e348ca467\$lut for cells of type $lut. No more expansions possible. <suppressed ~14537 debug messages> 24.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in processorci_top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201971.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201865.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202183.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$31489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31476.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$31122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$31122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$31109.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30773.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30765.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$30326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$30326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30017.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29786.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$29742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28873.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$28802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$28802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$28451.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$27803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$27803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$27803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$27259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26513.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26351.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23715.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23715.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23715.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22377.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21706.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21701.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21674.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21589.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$21062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$21034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$21034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$21034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$21025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$20060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$20060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$20060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$20051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$19087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$19087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$17458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$17458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$17458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$17449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17437.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17291.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id_ex.op1_ff.din[2].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$16951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$16922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$16903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$auto$fsm_map.cc:170:map_fsm$6365[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15520.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15515.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15305.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14403.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$11951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$11755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11761.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$11768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$11815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$11828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$11841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12481.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$13013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$13185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$13217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$14289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$14293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$14386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$14409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$14460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$14475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$14493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$14554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$auto$abc9_ops.cc:595:break_scc$55964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$14868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$14889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15771.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15995.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16371.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$16773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$16781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$16798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id_ex.op1_ff.din[2].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$17046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17512.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$18057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18299.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$18491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$18781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$18781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$18814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$18821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$19101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$19446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19591.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$19747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19751.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$19886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$20381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20488.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20684.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21453.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21603.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21679.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$21763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21820.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22693.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25286.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25708.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26099.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27435.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27861.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$28416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28416.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28455.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$28570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$28866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$28877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$29200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$29221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$29365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$30012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$30348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$30391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30747.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$31053.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$31146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$31414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$31414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31435.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$31476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$31489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31500.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$31632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$auto$opt_dff.cc:219:make_patterns_logic$6829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29179.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30251.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31595.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\Controller.memory_read_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\Controller.memory_read_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\Controller.memory_read_data[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\Controller.memory_read_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$auto$opt_dff.cc:219:make_patterns_logic$6750.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$flatten\u_tinyriscv.\u_div.$procmux$5478_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25553.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26391.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16069.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29121.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30789.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$31531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$18240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22049.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id_ex.op1_ff.din[2].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201748.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202428.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201793.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202259.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201836.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201941.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202343.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201844.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202267.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202215.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202329.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202325.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Removed 0 unused cells and 17840 unused wires. 24.45. Executing AUTONAME pass. Renamed 760368 objects in module processorci_top (295 iterations). <suppressed ~23173 debug messages> 24.46. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `processorci_top'. Setting top module to processorci_top. 24.46.1. Analyzing design hierarchy.. Top module: \processorci_top 24.46.2. Analyzing design hierarchy.. Top module: \processorci_top Removed 0 unused modules. 24.47. Printing statistics. === processorci_top === Number of wires: 10658 Number of wire bits: 34352 Number of public wires: 10658 Number of public wire bits: 34352 Number of ports: 10 Number of port bits: 10 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 14156 $scopeinfo 38 CCU2C 496 L6MUX21 567 LUT4 8634 MULT18X18D 4 PFUMX 1727 TRELLIS_DPR16X4 1060 TRELLIS_FF 1630 24.48. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Found and reported 0 problems. 24.49. Executing JSON backend. Warnings: 3 unique messages, 3 total End of script. Logfile hash: 0da9916ba5, CPU: user 65.38s system 0.45s, MEM: 378.33 MB peak Time spent: 32% 1x abc9_exe (21 sec), 13% 1x autoname (9 sec), ... /eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \ --lpf /eda/processor_ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \ --speed 6 --lpf-allow-unconstrained --ignore-loops /eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config --bit colorlight_i9.bit [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] echo Flashing FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p tinyriscv -b colorlight_i9 -l Final configuration file generated at /var/jenkins_home/workspace/tinyriscv/tinyriscv/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 (null) Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE Loading: [==== ] 6.91% Loading: [======== ] 14.09% Loading: [=========== ] 21.27% Loading: [=============== ] 28.19% Loading: [================== ] 35.10% Loading: [====================== ] 42.28% Loading: [========================= ] 49.46% Loading: [============================= ] 56.11% Loading: [================================ ] 63.02% Loading: [==================================== ] 70.20% Loading: [======================================= ] 77.11% Loading: [=========================================== ] 84.02% Loading: [============================================== ] 90.94% Loading: [==================================================] 98.12% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test colorlight_i9) [Pipeline] echo Testing FPGA colorlight_i9. [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] sh + echo Test for FPGA in /dev/ttyACM0 Test for FPGA in /dev/ttyACM0 [Pipeline] sh + python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0 Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'} [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Final configuration file generated at /var/jenkins_home/workspace/tinyriscv/tinyriscv/build_digilent_arty_a7_100t.tcl Makefile executed successfully. Makefile output: Building the Design... /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/tinyriscv/tinyriscv/build_digilent_arty_a7_100t.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096" ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source /var/jenkins_home/workspace/tinyriscv/tinyriscv/build_digilent_arty_a7_100t.tcl # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1278.277 ; gain = 28.836 ; free physical = 1993 ; free virtual = 24489 # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/rib.v # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v # read_verilog /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v # read_verilog /eda/processor_ci/rtl/tinyriscv.v # read_verilog /eda/processor-ci-controller/modules/uart.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v # read_verilog /eda/processor-ci-controller/src/fifo.v # read_verilog /eda/processor-ci-controller/src/reset.v # read_verilog /eda/processor-ci-controller/src/clk_divider.v # read_verilog /eda/processor-ci-controller/src/memory.v # read_verilog /eda/processor-ci-controller/src/interpreter.v # read_verilog /eda/processor-ci-controller/src/controller.v # set ID [lindex $argv 0] # set CLOCK_FREQ [lindex $argv 1] # set MEMORY_SIZE [lindex $argv 2] # set HIGH_CLK 1 # read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc" # set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] # synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE \ # -verilog_define $HIGH_CLK Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096 -verilog_define 1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 3666096 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2031.914 ; gain = 404.629 ; free physical = 922 ; free virtual = 23417 --------------------------------------------------------------------------------- INFO: [Synth 8-11241] undeclared symbol 'reset_o', assumed default net type 'wire' [/eda/processor_ci/rtl/tinyriscv.v:55] WARNING: [Synth 8-8895] 'reset_o' is already implicitly declared on line 55 [/eda/processor_ci/rtl/tinyriscv.v:160] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16] WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15] WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16] WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17] WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84] WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85] INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/tinyriscv.v:1] INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer Parameter ID bound to: 0 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1] Parameter COUNTER_BITS bound to: 32 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1] INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter ID bound to: 0 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213] INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1] Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1] INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1] INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1] Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1] WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268] INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1] INFO: [Synth 8-6157] synthesizing module 'tinyriscv' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v:20] INFO: [Synth 8-6157] synthesizing module 'pc_reg' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:20] INFO: [Synth 8-6155] done synthesizing module 'pc_reg' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:20] INFO: [Synth 8-6157] synthesizing module 'ctrl' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:21] INFO: [Synth 8-6155] done synthesizing module 'ctrl' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:21] INFO: [Synth 8-6157] synthesizing module 'regs' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:20] INFO: [Synth 8-6155] done synthesizing module 'regs' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:20] INFO: [Synth 8-6157] synthesizing module 'csr_reg' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:20] INFO: [Synth 8-6155] done synthesizing module 'csr_reg' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:20] INFO: [Synth 8-6157] synthesizing module 'if_id' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v:20] INFO: [Synth 8-6157] synthesizing module 'gen_pipe_dff' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18] Parameter DW bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'gen_pipe_dff' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18] INFO: [Synth 8-6157] synthesizing module 'gen_pipe_dff__parameterized0' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18] Parameter DW bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'gen_pipe_dff__parameterized0' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18] INFO: [Synth 8-6155] done synthesizing module 'if_id' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v:20] INFO: [Synth 8-6157] synthesizing module 'id' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:21] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:87] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:106] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:123] INFO: [Synth 8-6155] done synthesizing module 'id' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:21] INFO: [Synth 8-6157] synthesizing module 'id_ex' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v:20] INFO: [Synth 8-6157] synthesizing module 'gen_pipe_dff__parameterized1' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18] Parameter DW bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'gen_pipe_dff__parameterized1' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18] INFO: [Synth 8-6157] synthesizing module 'gen_pipe_dff__parameterized2' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18] Parameter DW bound to: 5 - type: integer INFO: [Synth 8-6155] done synthesizing module 'gen_pipe_dff__parameterized2' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18] INFO: [Synth 8-6155] done synthesizing module 'id_ex' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v:20] INFO: [Synth 8-6157] synthesizing module 'ex' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:21] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:256] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:355] INFO: [Synth 8-6155] done synthesizing module 'ex' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:21] INFO: [Synth 8-6157] synthesizing module 'div' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:22] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:87] INFO: [Synth 8-6155] done synthesizing module 'div' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:22] INFO: [Synth 8-6157] synthesizing module 'clint' [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:22] INFO: [Synth 8-6155] done synthesizing module 'clint' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:22] INFO: [Synth 8-6155] done synthesizing module 'tinyriscv' (0#1) [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v:20] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1] Parameter CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1] WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/tinyriscv.v:164] WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/tinyriscv.v:164] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/tinyriscv.v:164] INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/tinyriscv.v:1] WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25] WARNING: [Synth 8-3848] Net raddr_o in module/entity clint does not have driver. [/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:56] WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/tinyriscv.v:21] WARNING: [Synth 8-7129] Port raddr_o[31] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[30] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[29] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[28] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[27] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[26] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[25] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[24] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[23] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[22] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[21] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[20] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[19] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[18] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[17] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[16] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[15] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[14] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[13] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[12] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[11] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[10] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[9] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[8] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[7] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[6] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[5] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[4] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[3] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[2] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[1] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_o[0] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port hold_flag_i[2] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port hold_flag_i[1] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port hold_flag_i[0] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[31] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[30] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[29] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[28] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[27] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[26] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[25] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[24] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[23] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[22] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[21] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[20] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[19] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[18] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[17] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[16] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[15] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[14] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[13] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[12] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[11] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[10] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[9] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[8] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[7] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[6] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[5] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[4] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[3] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[2] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[1] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[0] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port csr_mstatus[3] in module clint is either unconnected or has no load WARNING: [Synth 8-7129] Port rst in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_i[11] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_i[10] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_i[9] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[31] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[30] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[29] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[28] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[27] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[26] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[25] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[24] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[23] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[22] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[21] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[20] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[19] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[18] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[17] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[16] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[15] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[14] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[13] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[12] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[11] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[10] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[9] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[8] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[7] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[6] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[5] in module ex is either unconnected or has no load WARNING: [Synth 8-7129] Port inst_addr_i[4] in module ex is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2130.852 ; gain = 503.566 ; free physical = 719 ; free virtual = 23216 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2148.664 ; gain = 521.379 ; free physical = 716 ; free virtual = 23213 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2148.664 ; gain = 521.379 ; free physical = 716 ; free virtual = 23213 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2148.664 ; gain = 0.000 ; free physical = 711 ; free virtual = 23208 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2291.414 ; gain = 0.000 ; free physical = 651 ; free virtual = 23147 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2291.449 ; gain = 0.000 ; free physical = 666 ; free virtual = 23162 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2291.449 ; gain = 664.164 ; free physical = 588 ; free virtual = 23099 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2291.449 ; gain = 664.164 ; free physical = 588 ; free virtual = 23099 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2291.449 ; gain = 664.164 ; free physical = 588 ; free virtual = 23099 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'div' INFO: [Synth 8-802] inferred FSM for state register 'csr_state_reg' in module 'clint' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 READ | 001 | 0001 COPY_READ_BUFFER | 010 | 0100 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 COPY_WRITE_BUFFER | 001 | 0100 WRITE | 010 | 0001 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 0001 | 00 iSTATE0 | 0010 | 01 iSTATE1 | 0100 | 10 iSTATE2 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * STATE_IDLE | 0001 | 0001 STATE_START | 0010 | 0010 STATE_CALC | 0100 | 0100 STATE_END | 1000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_reg' in module 'div' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * S_CSR_IDLE | 00001 | 00001 S_CSR_MEPC | 00100 | 00100 S_CSR_MSTATUS | 00010 | 00010 S_CSR_MCAUSE | 10000 | 10000 S_CSR_MSTATUS_MRET | 01000 | 01000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'csr_state_reg' in module 'clint' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RESET_COUNTER | 00 | 01 IDLE | 01 | 10 INIT | 10 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2291.449 ; gain = 664.164 ; free physical = 583 ; free virtual = 23095 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 3 2 Input 32 Bit Adders := 17 3 Input 32 Bit Adders := 2 2 Input 24 Bit Adders := 2 2 Input 10 Bit Adders := 2 2 Input 8 Bit Adders := 1 2 Input 6 Bit Adders := 4 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 2 Input 3 Bit Adders := 2 2 Input 2 Bit Adders := 2 +---XORs : 2 Input 32 Bit XORs := 1 2 Input 1 Bit XORs := 1 +---Registers : 64 Bit Registers := 2 32 Bit Registers := 44 24 Bit Registers := 5 10 Bit Registers := 2 8 Bit Registers := 12 6 Bit Registers := 1 5 Bit Registers := 2 4 Bit Registers := 2 3 Bit Registers := 3 1 Bit Registers := 35 +---RAMs : 32K Bit (1024 X 32 bit) RAMs := 2 64 Bit (8 X 8 bit) RAMs := 2 +---Muxes : 4 Input 64 Bit Muxes := 1 2 Input 64 Bit Muxes := 1 48 Input 64 Bit Muxes := 2 2 Input 32 Bit Muxes := 90 5 Input 32 Bit Muxes := 9 9 Input 32 Bit Muxes := 2 8 Input 32 Bit Muxes := 2 13 Input 32 Bit Muxes := 1 6 Input 32 Bit Muxes := 3 4 Input 32 Bit Muxes := 8 11 Input 32 Bit Muxes := 5 7 Input 32 Bit Muxes := 1 3 Input 32 Bit Muxes := 1 2 Input 31 Bit Muxes := 1 48 Input 24 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 13 Input 12 Bit Muxes := 1 5 Input 10 Bit Muxes := 1 48 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 5 4 Input 8 Bit Muxes := 1 24 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 2 2 Input 6 Bit Muxes := 4 3 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 22 3 Input 5 Bit Muxes := 2 13 Input 5 Bit Muxes := 1 6 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 7 9 Input 4 Bit Muxes := 2 5 Input 4 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 3 Input 4 Bit Muxes := 2 5 Input 3 Bit Muxes := 4 2 Input 3 Bit Muxes := 8 13 Input 3 Bit Muxes := 3 11 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 19 48 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 4 3 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 78 48 Input 1 Bit Muxes := 22 3 Input 1 Bit Muxes := 8 4 Input 1 Bit Muxes := 5 5 Input 1 Bit Muxes := 25 7 Input 1 Bit Muxes := 6 8 Input 1 Bit Muxes := 6 13 Input 1 Bit Muxes := 2 11 Input 1 Bit Muxes := 3 6 Input 1 Bit Muxes := 3 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met DSP Report: Generating DSP mul_temp, operation Mode is: A*B. DSP Report: operator mul_temp is absorbed into DSP mul_temp. DSP Report: operator mul_temp is absorbed into DSP mul_temp. DSP Report: Generating DSP mul_temp, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator mul_temp is absorbed into DSP mul_temp. DSP Report: operator mul_temp is absorbed into DSP mul_temp. DSP Report: Generating DSP mul_temp, operation Mode is: A*B. DSP Report: operator mul_temp is absorbed into DSP mul_temp. DSP Report: operator mul_temp is absorbed into DSP mul_temp. DSP Report: Generating DSP mul_temp, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator mul_temp is absorbed into DSP mul_temp. DSP Report: operator mul_temp is absorbed into DSP mul_temp. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 2291.449 ; gain = 664.164 ; free physical = 408 ; free virtual = 22931 --------------------------------------------------------------------------------- Sort Area is mul_temp_0 : 0 0 : 2701 5044 : Used 1 time 0 Sort Area is mul_temp_0 : 0 1 : 2343 5044 : Used 1 time 0 Sort Area is mul_temp_3 : 0 0 : 2339 4365 : Used 1 time 0 Sort Area is mul_temp_3 : 0 1 : 2026 4365 : Used 1 time 0 --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------+---------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+---------------------+---------------+----------------+ |Interpreter | memory_mux_selector | 256x1 | LUT | |Interpreter | memory_mux_selector | 256x1 | LUT | +------------+---------------------+---------------+----------------+ Distributed RAM: Preliminary Mapping Report (see note below) +------------+-------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-------------------------+-----------+----------------------+------------------+ |Controller | Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |Controller | Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |u_tinyriscv | u_regs/regs_reg | Implied | 32 x 32 | RAM32M x 18 | +------------+-------------------------+-----------+----------------------+------------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |ex | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |ex | (PCIN>>17)+A*B | 16 | 16 | - | - | 30 | 0 | 0 | - | - | - | 0 | 0 | |ex | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |ex | (PCIN>>17)+A*B | 18 | 16 | - | - | 47 | 0 | 0 | - | - | - | 0 | 0 | +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:55 ; elapsed = 00:01:57 . Memory (MB): peak = 2291.449 ; gain = 664.164 ; free physical = 405 ; free virtual = 22927 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:02:51 ; elapsed = 00:02:54 . Memory (MB): peak = 2299.547 ; gain = 672.262 ; free physical = 325 ; free virtual = 22847 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------+-------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-------------------------+-----------+----------------------+------------------+ |Controller | Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |Controller | Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |u_tinyriscv | u_regs/regs_reg | Implied | 32 x 32 | RAM32M x 18 | +------------+-------------------------+-----------+----------------------+------------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:03:01 ; elapsed = 00:03:04 . Memory (MB): peak = 2299.547 ; gain = 672.262 ; free physical = 334 ; free virtual = 22857 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:03:11 ; elapsed = 00:03:14 . Memory (MB): peak = 2303.516 ; gain = 676.230 ; free physical = 327 ; free virtual = 22850 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:03:11 ; elapsed = 00:03:14 . Memory (MB): peak = 2303.516 ; gain = 676.230 ; free physical = 333 ; free virtual = 22856 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:03:14 ; elapsed = 00:03:16 . Memory (MB): peak = 2303.516 ; gain = 676.230 ; free physical = 432 ; free virtual = 22835 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:03:14 ; elapsed = 00:03:17 . Memory (MB): peak = 2303.516 ; gain = 676.230 ; free physical = 432 ; free virtual = 22835 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:03:14 ; elapsed = 00:03:17 . Memory (MB): peak = 2303.516 ; gain = 676.230 ; free physical = 426 ; free virtual = 22829 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:03:14 ; elapsed = 00:03:17 . Memory (MB): peak = 2303.516 ; gain = 676.230 ; free physical = 422 ; free virtual = 22825 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- DSP Final Report (the ' indicates corresponding REG is set) +------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |ex | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |ex | PCIN>>17+A*B | 15 | 15 | - | - | 30 | 0 | 0 | - | - | - | 0 | 0 | |ex | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |ex | PCIN>>17+A*B | 17 | 15 | - | - | 47 | 0 | 0 | - | - | - | 0 | 0 | +------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 2| |2 |CARRY4 | 229| |3 |DSP48E1 | 4| |4 |LUT1 | 293| |5 |LUT2 | 618| |6 |LUT3 | 524| |7 |LUT4 | 574| |8 |LUT5 | 474| |9 |LUT6 | 1469| |10 |MUXF7 | 9| |11 |RAM256X1S | 256| |12 |RAM32M | 17| |13 |RAM32X1D | 10| |14 |FDRE | 1614| |15 |FDSE | 15| |16 |IBUF | 2| |17 |OBUF | 1| |18 |OBUFT | 2| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:03:14 ; elapsed = 00:03:17 . Memory (MB): peak = 2303.516 ; gain = 676.230 ; free physical = 420 ; free virtual = 22823 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 219 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:03:09 ; elapsed = 00:03:11 . Memory (MB): peak = 2303.516 ; gain = 533.445 ; free physical = 424 ; free virtual = 22828 Synthesis Optimization Complete : Time (s): cpu = 00:03:15 ; elapsed = 00:03:18 . Memory (MB): peak = 2303.523 ; gain = 676.230 ; free physical = 422 ; free virtual = 22826 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2303.523 ; gain = 0.000 ; free physical = 715 ; free virtual = 23128 INFO: [Netlist 29-17] Analyzing 525 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2399.562 ; gain = 0.000 ; free physical = 640 ; free virtual = 23099 INFO: [Project 1-111] Unisim Transformation Summary: A total of 283 instances were transformed. RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 17 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 10 instances Synth Design complete | Checksum: ba99c83 INFO: [Common 17-83] Releasing license: Synthesis 90 Infos, 121 Warnings, 2 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:03:35 ; elapsed = 00:03:33 . Memory (MB): peak = 2399.598 ; gain = 1121.320 ; free physical = 616 ; free virtual = 23094 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2131.425; main = 1837.281; forked = 435.541 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3281.883; main = 2399.566; forked = 982.332 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2463.594 ; gain = 63.996 ; free physical = 570 ; free virtual = 23088 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 13adcb5c9 Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2498.578 ; gain = 34.984 ; free physical = 476 ; free virtual = 23012 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 13adcb5c9 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2733.578 ; gain = 0.000 ; free physical = 219 ; free virtual = 22754 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 13adcb5c9 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2733.578 ; gain = 0.000 ; free physical = 218 ; free virtual = 22754 Phase 1 Initialization | Checksum: 13adcb5c9 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2733.578 ; gain = 0.000 ; free physical = 218 ; free virtual = 22753 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 13adcb5c9 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2733.578 ; gain = 0.000 ; free physical = 218 ; free virtual = 22753 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 13adcb5c9 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2733.578 ; gain = 0.000 ; free physical = 218 ; free virtual = 22753 Phase 2 Timer Update And Timing Data Collection | Checksum: 13adcb5c9 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2733.578 ; gain = 0.000 ; free physical = 218 ; free virtual = 22753 Phase 3 Retarget INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 24 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 201ea961a Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2733.578 ; gain = 0.000 ; free physical = 218 ; free virtual = 22753 Retarget | Checksum: 201ea961a INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 1fe079711 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2733.578 ; gain = 0.000 ; free physical = 218 ; free virtual = 22753 Constant propagation | Checksum: 1fe079711 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 2338b49ef Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2733.578 ; gain = 0.000 ; free physical = 218 ; free virtual = 22753 Sweep | Checksum: 2338b49ef INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 2338b49ef Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2765.594 ; gain = 32.016 ; free physical = 203 ; free virtual = 22738 BUFG optimization | Checksum: 2338b49ef INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 2338b49ef Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2765.594 ; gain = 32.016 ; free physical = 201 ; free virtual = 22736 Shift Register Optimization | Checksum: 2338b49ef INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 2338b49ef Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2765.594 ; gain = 32.016 ; free physical = 211 ; free virtual = 22747 Post Processing Netlist | Checksum: 2338b49ef INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 19017de08 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2765.594 ; gain = 32.016 ; free physical = 210 ; free virtual = 22745 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2765.594 ; gain = 0.000 ; free physical = 218 ; free virtual = 22753 Phase 9.2 Verifying Netlist Connectivity | Checksum: 19017de08 Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2765.594 ; gain = 32.016 ; free physical = 217 ; free virtual = 22753 Phase 9 Finalization | Checksum: 19017de08 Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2765.594 ; gain = 32.016 ; free physical = 217 ; free virtual = 22752 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 1 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 19017de08 Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2765.594 ; gain = 32.016 ; free physical = 216 ; free virtual = 22752 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2765.594 ; gain = 0.000 ; free physical = 213 ; free virtual = 22748 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 19017de08 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2765.594 ; gain = 0.000 ; free physical = 204 ; free virtual = 22740 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 19017de08 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2765.594 ; gain = 0.000 ; free physical = 204 ; free virtual = 22740 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2765.594 ; gain = 0.000 ; free physical = 204 ; free virtual = 22740 Ending Netlist Obfuscation Task | Checksum: 19017de08 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2765.594 ; gain = 0.000 ; free physical = 204 ; free virtual = 22739 INFO: [Common 17-83] Releasing license: Implementation 19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 2765.594 ; gain = 365.996 ; free physical = 203 ; free virtual = 22739 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2797.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 22758 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1107087ae Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2797.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 22758 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2797.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 22758 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 5c7665a9 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2797.609 ; gain = 0.000 ; free physical = 240 ; free virtual = 22775 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 92aa770e Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 251 ; free virtual = 22860 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 92aa770e Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 251 ; free virtual = 22860 Phase 1 Placer Initialization | Checksum: 92aa770e Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 251 ; free virtual = 22860 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: e53a63ad Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 244 ; free virtual = 22853 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: a6cfb4ad Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 246 ; free virtual = 22855 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 111d33b86 Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 246 ; free virtual = 22855 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1951d905d Time (s): cpu = 00:00:58 ; elapsed = 00:00:37 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 264 ; free virtual = 22830 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 49 LUTNM shape to break, 146 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 17, two critical 32, total 49, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 98 nets or LUTs. Breaked 49 LUTs, combined 49 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2804.637 ; gain = 0.000 ; free physical = 262 ; free virtual = 22827 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 49 | 49 | 98 | 0 | 1 | 00:00:01 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 49 | 49 | 98 | 0 | 9 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1380424a1 Time (s): cpu = 00:01:02 ; elapsed = 00:00:41 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 265 ; free virtual = 22830 Phase 2.4 Global Placement Core | Checksum: 1c2d44e9d Time (s): cpu = 00:01:33 ; elapsed = 00:00:57 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 264 ; free virtual = 22829 Phase 2 Global Placement | Checksum: 1c2d44e9d Time (s): cpu = 00:01:33 ; elapsed = 00:00:57 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 264 ; free virtual = 22829 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1c5b824bc Time (s): cpu = 00:01:36 ; elapsed = 00:00:58 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 268 ; free virtual = 22833 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: eba86ef2 Time (s): cpu = 00:01:42 ; elapsed = 00:01:02 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 263 ; free virtual = 22828 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 138748c00 Time (s): cpu = 00:01:43 ; elapsed = 00:01:03 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 262 ; free virtual = 22827 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 112679529 Time (s): cpu = 00:01:43 ; elapsed = 00:01:03 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 257 ; free virtual = 22823 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: a4ddc2ad Time (s): cpu = 00:02:02 ; elapsed = 00:01:19 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 263 ; free virtual = 22828 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 1050b07a5 Time (s): cpu = 00:02:07 ; elapsed = 00:01:24 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 267 ; free virtual = 22833 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: f151cb10 Time (s): cpu = 00:02:08 ; elapsed = 00:01:25 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 267 ; free virtual = 22832 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 18926fccd Time (s): cpu = 00:02:08 ; elapsed = 00:01:25 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 260 ; free virtual = 22825 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 11de6e418 Time (s): cpu = 00:02:35 ; elapsed = 00:01:47 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 265 ; free virtual = 22831 Phase 3 Detail Placement | Checksum: 11de6e418 Time (s): cpu = 00:02:35 ; elapsed = 00:01:47 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 260 ; free virtual = 22825 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1dd863df5 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-8.430 | TNS=-3253.574 | Phase 1 Physical Synthesis Initialization | Checksum: 1881e73b9 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2804.637 ; gain = 0.000 ; free physical = 267 ; free virtual = 22832 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 1881e73b9 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2804.637 ; gain = 0.000 ; free physical = 267 ; free virtual = 22832 Phase 4.1.1.1 BUFG Insertion | Checksum: 1dd863df5 Time (s): cpu = 00:02:47 ; elapsed = 00:01:54 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 267 ; free virtual = 22832 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=-6.962. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 2351e6d2c Time (s): cpu = 00:03:37 ; elapsed = 00:02:38 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 263 ; free virtual = 22828 Time (s): cpu = 00:03:37 ; elapsed = 00:02:38 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 263 ; free virtual = 22828 Phase 4.1 Post Commit Optimization | Checksum: 2351e6d2c Time (s): cpu = 00:03:37 ; elapsed = 00:02:38 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 267 ; free virtual = 22832 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 2351e6d2c Time (s): cpu = 00:03:37 ; elapsed = 00:02:38 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 257 ; free virtual = 22823 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 2351e6d2c Time (s): cpu = 00:03:37 ; elapsed = 00:02:39 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 251 ; free virtual = 22816 Phase 4.3 Placer Reporting | Checksum: 2351e6d2c Time (s): cpu = 00:03:38 ; elapsed = 00:02:39 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 267 ; free virtual = 22832 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2804.637 ; gain = 0.000 ; free physical = 267 ; free virtual = 22832 Time (s): cpu = 00:03:38 ; elapsed = 00:02:39 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 267 ; free virtual = 22832 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2338d996a Time (s): cpu = 00:03:38 ; elapsed = 00:02:39 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 267 ; free virtual = 22832 Ending Placer Task | Checksum: 158a997ba Time (s): cpu = 00:03:38 ; elapsed = 00:02:39 . Memory (MB): peak = 2804.637 ; gain = 7.027 ; free physical = 267 ; free virtual = 22832 37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:03:41 ; elapsed = 00:02:41 . Memory (MB): peak = 2804.637 ; gain = 39.043 ; free physical = 267 ; free virtual = 22832 # report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt # report_utilization -file digilent_arty_a7_utilization_place.rpt # report_io -file digilent_arty_a7_io.rpt report_io: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2804.637 ; gain = 0.000 ; free physical = 268 ; free virtual = 22833 # report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2804.637 ; gain = 0.000 ; free physical = 268 ; free virtual = 22833 # report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: 902bf1cf ConstDB: 0 ShapeSum: c87da5eb RouteDB: 0 Post Restoration Checksum: NetGraph: 18b83c73 | NumContArr: 8750f780 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 2255b292d Time (s): cpu = 00:01:25 ; elapsed = 00:01:15 . Memory (MB): peak = 2804.637 ; gain = 0.000 ; free physical = 772 ; free virtual = 23362 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 2255b292d Time (s): cpu = 00:01:25 ; elapsed = 00:01:15 . Memory (MB): peak = 2804.637 ; gain = 0.000 ; free physical = 772 ; free virtual = 23362 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 2255b292d Time (s): cpu = 00:01:25 ; elapsed = 00:01:15 . Memory (MB): peak = 2804.637 ; gain = 0.000 ; free physical = 772 ; free virtual = 23362 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2453ecb94 Time (s): cpu = 00:01:40 ; elapsed = 00:01:23 . Memory (MB): peak = 2804.637 ; gain = 0.000 ; free physical = 771 ; free virtual = 23361 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-6.884 | TNS=-2292.111| WHS=-0.834 | THS=-318.457| Router Utilization Summary Global Vertical Routing Utilization = 0.00661531 % Global Horizontal Routing Utilization = 0.00738846 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 5234 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 5198 Number of Partially Routed Nets = 36 Number of Node Overlaps = 32 Phase 2 Router Initialization | Checksum: 1c5664d5e Time (s): cpu = 00:01:45 ; elapsed = 00:01:26 . Memory (MB): peak = 2804.637 ; gain = 0.000 ; free physical = 776 ; free virtual = 23366 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 1c5664d5e Time (s): cpu = 00:01:45 ; elapsed = 00:01:26 . Memory (MB): peak = 2804.637 ; gain = 0.000 ; free physical = 776 ; free virtual = 23366 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 1496ec0ce Time (s): cpu = 00:01:53 ; elapsed = 00:01:29 . Memory (MB): peak = 2832.559 ; gain = 27.922 ; free physical = 726 ; free virtual = 23316 Phase 3 Initial Routing | Checksum: 1496ec0ce Time (s): cpu = 00:01:53 ; elapsed = 00:01:29 . Memory (MB): peak = 2832.559 ; gain = 27.922 ; free physical = 726 ; free virtual = 23316 INFO: [Route 35-580] Design has 98 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +====================+===================+=============================================+ | Launch Setup Clock | Launch Hold Clock | Pin | +====================+===================+=============================================+ | sys_clk_pin | sys_clk_pin | u_tinyriscv/u_id_ex/op1_ff/qout_r_reg[12]/D | | sys_clk_pin | sys_clk_pin | u_tinyriscv/u_id_ex/op1_ff/qout_r_reg[16]/D | | sys_clk_pin | sys_clk_pin | u_tinyriscv/u_id_ex/op2_ff/qout_r_reg[16]/D | | sys_clk_pin | sys_clk_pin | u_tinyriscv/u_id_ex/op1_ff/qout_r_reg[14]/D | | sys_clk_pin | sys_clk_pin | u_tinyriscv/u_id_ex/op1_ff/qout_r_reg[15]/D | +--------------------+-------------------+---------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 717 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-7.771 | TNS=-3214.834| WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 2cb39b3e0 Time (s): cpu = 00:02:38 ; elapsed = 00:02:08 . Memory (MB): peak = 2845.559 ; gain = 40.922 ; free physical = 712 ; free virtual = 23302 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 288 Number of Nodes with overlaps = 26 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-7.669 | TNS=-3183.630| WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 2e54652fa Time (s): cpu = 00:05:06 ; elapsed = 00:04:35 . Memory (MB): peak = 2869.559 ; gain = 64.922 ; free physical = 685 ; free virtual = 23276 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 237 Number of Nodes with overlaps = 160 Number of Nodes with overlaps = 51 Number of Nodes with overlaps = 40 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-7.386 | TNS=-3144.215| WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 1f2a9f095 Time (s): cpu = 00:08:31 ; elapsed = 00:07:57 . Memory (MB): peak = 2891.559 ; gain = 86.922 ; free physical = 678 ; free virtual = 23269 Phase 4.4 Global Iteration 3 Number of Nodes with overlaps = 236 Number of Nodes with overlaps = 84 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 22 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-7.855 | TNS=-3260.598| WHS=N/A | THS=N/A | Phase 4.4 Global Iteration 3 | Checksum: 275cc0602 Time (s): cpu = 00:12:26 ; elapsed = 00:11:49 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 660 ; free virtual = 23259 Phase 4 Rip-up And Reroute | Checksum: 275cc0602 Time (s): cpu = 00:12:26 ; elapsed = 00:11:50 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 659 ; free virtual = 23258 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 2ac6adc53 Time (s): cpu = 00:12:29 ; elapsed = 00:11:51 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 667 ; free virtual = 23266 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-7.290 | TNS=-3106.721| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 1d27a9ab2 Time (s): cpu = 00:12:30 ; elapsed = 00:11:52 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 666 ; free virtual = 23265 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1d27a9ab2 Time (s): cpu = 00:12:30 ; elapsed = 00:11:52 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 666 ; free virtual = 23265 Phase 5 Delay and Skew Optimization | Checksum: 1d27a9ab2 Time (s): cpu = 00:12:30 ; elapsed = 00:11:52 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 666 ; free virtual = 23265 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 275ef5e3d Time (s): cpu = 00:12:35 ; elapsed = 00:11:54 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 662 ; free virtual = 23261 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-7.277 | TNS=-3068.703| WHS=0.059 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 213cfca98 Time (s): cpu = 00:12:35 ; elapsed = 00:11:54 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 662 ; free virtual = 23260 Phase 6 Post Hold Fix | Checksum: 213cfca98 Time (s): cpu = 00:12:35 ; elapsed = 00:11:54 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 662 ; free virtual = 23260 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 1.46664 % Global Horizontal Routing Utilization = 1.7927 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report North Dir 1x1 Area, Max Cong = 58.5586%, No Congested Regions. South Dir 1x1 Area, Max Cong = 66.6667%, No Congested Regions. East Dir 1x1 Area, Max Cong = 69.1176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 69.1176%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 7 Route finalize | Checksum: 213cfca98 Time (s): cpu = 00:12:35 ; elapsed = 00:11:55 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 664 ; free virtual = 23263 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 213cfca98 Time (s): cpu = 00:12:35 ; elapsed = 00:11:55 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 664 ; free virtual = 23263 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 2189d38ac Time (s): cpu = 00:12:37 ; elapsed = 00:11:56 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 667 ; free virtual = 23266 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=-7.277 | TNS=-3068.703| WHS=0.059 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 10 Post Router Timing | Checksum: 2189d38ac Time (s): cpu = 00:12:40 ; elapsed = 00:11:57 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 652 ; free virtual = 23251 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 1afc9d398 Time (s): cpu = 00:12:40 ; elapsed = 00:11:58 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 656 ; free virtual = 23254 Ending Routing Task | Checksum: 1afc9d398 Time (s): cpu = 00:12:41 ; elapsed = 00:11:58 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 656 ; free virtual = 23255 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 16 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:12:45 ; elapsed = 00:12:01 . Memory (MB): peak = 2899.559 ; gain = 94.922 ; free physical = 658 ; free virtual = 23256 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (1) 6. checking no_output_delay (1) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (1) ------------------------------ There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (1) ------------------------------- There is 1 port with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -7.280 -3070.241 1187 15237 0.060 0.000 0 15237 3.750 0.000 0 2811 Timing constraints are not met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sck {0.000 50.000} 100.000 10.000 sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin -7.280 -3070.241 1187 15237 0.060 0.000 0 15237 3.750 0.000 0 2811 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_arty_a7_route_status.rpt # report_drc -file digilent_arty_a7_drc.rpt Command: report_drc -file digilent_arty_a7_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/tinyriscv/tinyriscv/digilent_arty_a7_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_arty_a7_power.rpt Command: report_power -file digilent_arty_a7_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "digilent_arty_a7_100t.bit" Command: write_bitstream -force digilent_arty_a7_100t.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [DRC DPIP-1] Input pipelining: DSP u_tinyriscv/u_ex/mul_temp input u_tinyriscv/u_ex/mul_temp/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP u_tinyriscv/u_ex/mul_temp input u_tinyriscv/u_ex/mul_temp/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP u_tinyriscv/u_ex/mul_temp__0 input u_tinyriscv/u_ex/mul_temp__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP u_tinyriscv/u_ex/mul_temp__0 input u_tinyriscv/u_ex/mul_temp__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP u_tinyriscv/u_ex/mul_temp__1 input u_tinyriscv/u_ex/mul_temp__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP u_tinyriscv/u_ex/mul_temp__1 input u_tinyriscv/u_ex/mul_temp__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP u_tinyriscv/u_ex/mul_temp__2 input u_tinyriscv/u_ex/mul_temp__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP u_tinyriscv/u_ex/mul_temp__2 input u_tinyriscv/u_ex/mul_temp__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP u_tinyriscv/u_ex/mul_temp output u_tinyriscv/u_ex/mul_temp/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP u_tinyriscv/u_ex/mul_temp__0 output u_tinyriscv/u_ex/mul_temp__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP u_tinyriscv/u_ex/mul_temp__1 output u_tinyriscv/u_ex/mul_temp__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP u_tinyriscv/u_ex/mul_temp__2 output u_tinyriscv/u_ex/mul_temp__2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP u_tinyriscv/u_ex/mul_temp multiplier stage u_tinyriscv/u_ex/mul_temp/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP u_tinyriscv/u_ex/mul_temp__0 multiplier stage u_tinyriscv/u_ex/mul_temp__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP u_tinyriscv/u_ex/mul_temp__1 multiplier stage u_tinyriscv/u_ex/mul_temp__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP u_tinyriscv/u_ex/mul_temp__2 multiplier stage u_tinyriscv/u_ex/mul_temp__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 17 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./digilent_arty_a7_100t.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 17 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:33 ; elapsed = 00:00:32 . Memory (MB): peak = 3136.230 ; gain = 180.645 ; free physical = 398 ; free virtual = 23001 # exit INFO: [Common 17-206] Exiting Vivado at Sat Apr 5 23:01:06 2025... [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] echo Flashing FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p tinyriscv -b digilent_arty_a7_100t -l Final configuration file generated at /var/jenkins_home/workspace/tinyriscv/tinyriscv/build_digilent_arty_a7_100t.tcl Makefile executed successfully. Makefile output: Flashing the FPGA... /eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit empty Jtag frequency : requested 10.00MHz -> real 10.00MHz Open file DONE Parse file DONE load program Load SRAM: [=============== ] 30.00% Load SRAM: [=============================== ] 62.00% Load SRAM: [=============================================== ] 94.00% Load SRAM: [===================================================] 100.00% Done Shift IR 35 ir: 1 isc_done 1 isc_ena 0 init 1 done 1 [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) [Pipeline] echo Testing FPGA digilent_arty_a7_100t. [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] sh + echo Test for FPGA in /dev/ttyUSB1 Test for FPGA in /dev/ttyUSB1 [Pipeline] sh + python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1 Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'} [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 97481a11-0c45-42a7-b685-b5baa76e6c8b hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: No test report files were found. Configuration error? Finished: FAILURE