Skip to content

Workspace

/ rv3n /
.git
.Xil
build
FPGA
rtl
sim
testbench
.gitattributesMay 1, 2025, 1:18:54 AM66 B
build_digilent_arty_a7_100t.tclMay 1, 2025, 1:19:01 AM3.30 KiB
clockInfo.txtMay 1, 2025, 1:19:57 AM375 B
diagram.pngMay 1, 2025, 1:18:54 AM57.29 KiB
digilent_arty_a7_100t.bitMay 1, 2025, 1:20:52 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptMay 1, 2025, 1:20:02 AM16.56 KiB
digilent_arty_a7_control_sets.rptMay 1, 2025, 1:20:01 AM12.48 KiB
digilent_arty_a7_drc.rptMay 1, 2025, 1:20:33 AM2.36 KiB
digilent_arty_a7_io.rptMay 1, 2025, 1:20:01 AM96.82 KiB
digilent_arty_a7_power.rptMay 1, 2025, 1:20:34 AM8.55 KiB
digilent_arty_a7_route_status.rptMay 1, 2025, 1:20:32 AM651 B
digilent_arty_a7_timing.rptMay 1, 2025, 1:20:33 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptMay 1, 2025, 1:20:01 AM3.09 KiB
digilent_arty_a7_utilization_place.rptMay 1, 2025, 1:20:01 AM10.57 KiB
LICENSEMay 1, 2025, 1:18:54 AM11.06 KiB
processor_ci_defines.vhMay 1, 2025, 1:19:01 AM300 B
README.mdMay 1, 2025, 1:18:54 AM3.88 KiB
simulation.outMay 1, 2025, 1:18:56 AM716.36 KiB