Started by user Julio Nunes Avelar [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/lib/jenkins/workspace/riskow [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf riskow [Pipeline] sh + git clone --recursive https://github.com/racerxdl/riskow riskow Cloning into 'riskow'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/lib/jenkins/workspace/riskow/riskow [Pipeline] { [Pipeline] sh + iverilog -o simulation.out -g2005 -s CPU cpu/alu.v cpu/comp.v cpu/cpu.v cpu/instruction_decoder.v cpu/program_counter.v cpu/register_bank.v [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_nexys4_ddr) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_nexys4_ddr) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] The resource [colorlight_i9] is locked by build riscado-v #3 #3 since Oct 8, 2024, 12:52 AM. [Resource: colorlight_i9] is not free, waiting for execution ... [Required resources: [colorlight_i9]] added into queue at position 0 [Pipeline] lock Trying to acquire lock on [Resource: digilent_nexys4_ddr] The resource [digilent_nexys4_ddr] is locked by build riscado-v #3 #3 since Oct 8, 2024, 12:52 AM. [Resource: digilent_nexys4_ddr] is not free, waiting for execution ... [Required resources: [digilent_nexys4_ddr]] added into queue at position 1 Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] stage [Pipeline] { (Síntese e PnR) [Pipeline] dir Running in /var/lib/jenkins/workspace/riskow/riskow [Pipeline] { [Pipeline] echo Iniciando síntese para FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b colorlight_i9 Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/riskow/riskow/build_colorlight_i9.tcl Erro ao executar o Makefile. Info: constraining clock net 'sck' to 10.00 MHz Info: constraining clock net 'clk' to 25.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 13422/43848 30% Info: logic LUTs: 6582/43848 15% Info: carry LUTs: 576/43848 1% Info: RAM LUTs: 4176/ 5481 76% Info: RAMW LUTs: 2088/10962 19% Info: Total DFFs: 915/43848 2% Info: Packing IOs.. Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 'sck$tr_io' constrained to Bel 'X4/Y71/PIOA'. Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: pin 'rw$tr_io' constrained to Bel 'X4/Y71/PIOB'. Info: pin 'reset$tr_io' constrained to Bel 'X6/Y71/PIOB'. Info: pin 'mosi$tr_io' constrained to Bel 'X9/Y71/PIOA'. Info: pin 'miso$tr_io' constrained to Bel 'X0/Y65/PIOB'. Info: pin 'intr$tr_io' constrained to Bel 'X9/Y71/PIOB'. Info: pin 'cs$tr_io' constrained to Bel 'X6/Y71/PIOA'. Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 509 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: promoting clock net clk_core to global network Info: Checksum: 0x09775124 Info: Device utilisation: Info: TRELLIS_IO: 10/ 245 4% Info: DCCA: 2/ 56 3% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 915/ 43848 2% Info: TRELLIS_COMB: 13540/ 43848 30% Info: TRELLIS_RAMW: 1044/ 5481 19% Info: Found 49 combinational loops: Info: loop 1: Info: Riskow.alu.O_LUT4_Z.B (Riskow.aluO[0]) Info: Riskow.alu.O_LUT4_Z.F (Riskow.aluO[0]) Info: loop 2: Info: Riskow.alu.O_LUT4_Z_1.B (Riskow.aluO[1]) Info: Riskow.alu.O_LUT4_Z_1.F (Riskow.aluO[1]) Info: loop 3: Info: Riskow.alu.O_LUT4_Z_10.B (Riskow.aluO[22]) Info: Riskow.alu.O_LUT4_Z_10.F (Riskow.aluO[22]) Info: loop 4: Info: Riskow.alu.O_LUT4_Z_11.A (Riskow.aluO[23]) Info: Riskow.alu.O_LUT4_Z_11.F (Riskow.aluO[23]) Info: loop 5: Info: Riskow.alu.O_LUT4_Z_12.B (Riskow.aluO[28]) Info: Riskow.alu.O_LUT4_Z_12.F (Riskow.aluO[28]) Info: loop 6: Info: Riskow.alu.O_LUT4_Z_13.B (Riskow.aluO[31]) Info: Riskow.alu.O_LUT4_Z_13.F (Riskow.aluO[31]) Info: loop 7: Info: Riskow.alu.O_LUT4_Z_2.B (Riskow.aluO[5]) Info: Riskow.alu.O_LUT4_Z_2.F (Riskow.aluO[5]) Info: loop 8: Info: Riskow.alu.O_LUT4_Z_3.A (Riskow.aluO[8]) Info: Riskow.alu.O_LUT4_Z_3.F (Riskow.aluO[8]) Info: loop 9: Info: Riskow.alu.O_LUT4_Z_4.B (Riskow.aluO[12]) Info: Riskow.alu.O_LUT4_Z_4.F (Riskow.aluO[12]) Info: loop 10: Info: Riskow.alu.O_LUT4_Z_5.A (Riskow.aluO[13]) Info: Riskow.alu.O_LUT4_Z_5.F (Riskow.aluO[13]) Info: loop 11: Info: Riskow.alu.O_LUT4_Z_6.B (Riskow.aluO[16]) Info: Riskow.alu.O_LUT4_Z_6.F (Riskow.aluO[16]) Info: loop 12: Info: Riskow.alu.O_LUT4_Z_7.A (Riskow.aluO[17]) Info: Riskow.alu.O_LUT4_Z_7.F (Riskow.aluO[17]) Info: loop 13: Info: Riskow.alu.O_LUT4_Z_8.B (Riskow.aluO[19]) Info: Riskow.alu.O_LUT4_Z_8.F (Riskow.aluO[19]) Info: loop 14: Info: Riskow.alu.O_LUT4_Z_9.B (Riskow.aluO[21]) Info: Riskow.alu.O_LUT4_Z_9.F (Riskow.aluO[21]) Info: loop 15: Info: Riskow.alu.O_PFUMX_Z_10_ALUT_LUT4_Z.A (Riskow.aluO[18]) Info: Riskow.alu.O_PFUMX_Z_10_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_10_ALUT) Info: Riskow.alu.O_PFUMX_Z_10_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_10_ALUT) Info: Riskow.alu.O_PFUMX_Z_10_BLUT_LUT4_Z.OFX (Riskow.aluO[18]) Info: loop 16: Info: Riskow.alu.O_PFUMX_Z_10_BLUT_LUT4_Z.C (Riskow.aluO[18]) Info: Riskow.alu.O_PFUMX_Z_10_BLUT_LUT4_Z.OFX (Riskow.aluO[18]) Info: loop 17: Info: Riskow.alu.O_PFUMX_Z_11_ALUT_LUT4_Z.A (Riskow.aluO[20]) Info: Riskow.alu.O_PFUMX_Z_11_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_11_ALUT) Info: Riskow.alu.O_PFUMX_Z_11_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_11_ALUT) Info: Riskow.alu.O_PFUMX_Z_11_BLUT_LUT4_Z.OFX (Riskow.aluO[20]) Info: loop 18: Info: Riskow.alu.O_PFUMX_Z_11_BLUT_LUT4_Z.C (Riskow.aluO[20]) Info: Riskow.alu.O_PFUMX_Z_11_BLUT_LUT4_Z.OFX (Riskow.aluO[20]) Info: loop 19: Info: Riskow.alu.O_PFUMX_Z_12_ALUT_LUT4_Z.A (Riskow.aluO[24]) Info: Riskow.alu.O_PFUMX_Z_12_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_12_ALUT) Info: Riskow.alu.O_PFUMX_Z_12_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_12_ALUT) Info: Riskow.alu.O_PFUMX_Z_12_BLUT_LUT4_Z.OFX (Riskow.aluO[24]) Info: loop 20: Info: Riskow.alu.O_PFUMX_Z_12_BLUT_LUT4_Z.C (Riskow.aluO[24]) Info: Riskow.alu.O_PFUMX_Z_12_BLUT_LUT4_Z.OFX (Riskow.aluO[24]) Info: loop 21: Info: Riskow.alu.O_PFUMX_Z_13_ALUT_LUT4_Z.A (Riskow.aluO[25]) Info: Riskow.alu.O_PFUMX_Z_13_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_13_ALUT) Info: Riskow.alu.O_PFUMX_Z_13_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_13_ALUT) Info: Riskow.alu.O_PFUMX_Z_13_BLUT_LUT4_Z.OFX (Riskow.aluO[25]) Info: loop 22: Info: Riskow.alu.O_PFUMX_Z_13_BLUT_LUT4_Z.C (Riskow.aluO[25]) Info: Riskow.alu.O_PFUMX_Z_13_BLUT_LUT4_Z.OFX (Riskow.aluO[25]) Info: loop 23: Info: Riskow.alu.O_PFUMX_Z_14_ALUT_LUT4_Z.A (Riskow.aluO[26]) Info: Riskow.alu.O_PFUMX_Z_14_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_14_ALUT) Info: Riskow.alu.O_PFUMX_Z_14_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_14_ALUT) Info: Riskow.alu.O_PFUMX_Z_14_BLUT_LUT4_Z.OFX (Riskow.aluO[26]) Info: loop 24: Info: Riskow.alu.O_PFUMX_Z_14_BLUT_LUT4_Z.C (Riskow.aluO[26]) Info: Riskow.alu.O_PFUMX_Z_14_BLUT_LUT4_Z.OFX (Riskow.aluO[26]) Info: loop 25: Info: Riskow.alu.O_PFUMX_Z_15_ALUT_LUT4_Z.A (Riskow.aluO[27]) Info: Riskow.alu.O_PFUMX_Z_15_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_15_ALUT) Info: Riskow.alu.O_PFUMX_Z_15_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_15_ALUT) Info: Riskow.alu.O_PFUMX_Z_15_BLUT_LUT4_Z.OFX (Riskow.aluO[27]) Info: loop 26: Info: Riskow.alu.O_PFUMX_Z_15_BLUT_LUT4_Z.C (Riskow.aluO[27]) Info: Riskow.alu.O_PFUMX_Z_15_BLUT_LUT4_Z.OFX (Riskow.aluO[27]) Info: loop 27: Info: Riskow.alu.O_PFUMX_Z_16_ALUT_LUT4_Z.A (Riskow.aluO[29]) Info: Riskow.alu.O_PFUMX_Z_16_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_16_ALUT) Info: Riskow.alu.O_PFUMX_Z_16_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_16_ALUT) Info: Riskow.alu.O_PFUMX_Z_16_BLUT_LUT4_Z.OFX (Riskow.aluO[29]) Info: loop 28: Info: Riskow.alu.O_PFUMX_Z_16_BLUT_LUT4_Z.C (Riskow.aluO[29]) Info: Riskow.alu.O_PFUMX_Z_16_BLUT_LUT4_Z.OFX (Riskow.aluO[29]) Info: loop 29: Info: Riskow.alu.O_PFUMX_Z_17_ALUT_LUT4_Z.A (Riskow.aluO[30]) Info: Riskow.alu.O_PFUMX_Z_17_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_17_ALUT) Info: Riskow.alu.O_PFUMX_Z_17_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_17_ALUT) Info: Riskow.alu.O_PFUMX_Z_17_BLUT_LUT4_Z.OFX (Riskow.aluO[30]) Info: loop 30: Info: Riskow.alu.O_PFUMX_Z_17_BLUT_LUT4_Z.C (Riskow.aluO[30]) Info: Riskow.alu.O_PFUMX_Z_17_BLUT_LUT4_Z.OFX (Riskow.aluO[30]) Info: loop 31: Info: Riskow.alu.O_PFUMX_Z_1_ALUT_LUT4_Z.B (Riskow.aluO[3]) Info: Riskow.alu.O_PFUMX_Z_1_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_1_ALUT) Info: Riskow.alu.O_PFUMX_Z_1_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_1_ALUT) Info: Riskow.alu.O_PFUMX_Z_1_BLUT_LUT4_Z.OFX (Riskow.aluO[3]) Info: loop 32: Info: Riskow.alu.O_PFUMX_Z_1_BLUT_LUT4_Z.B (Riskow.aluO[3]) Info: Riskow.alu.O_PFUMX_Z_1_BLUT_LUT4_Z.OFX (Riskow.aluO[3]) Info: loop 33: Info: Riskow.alu.O_PFUMX_Z_2_ALUT_LUT4_Z.A (Riskow.aluO[2]) Info: Riskow.alu.O_PFUMX_Z_2_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_2_ALUT) Info: Riskow.alu.O_PFUMX_Z_2_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_2_ALUT) Info: Riskow.alu.O_PFUMX_Z_2_BLUT_LUT4_Z.OFX (Riskow.aluO[2]) Info: loop 34: Info: Riskow.alu.O_PFUMX_Z_2_BLUT_LUT4_Z.C (Riskow.aluO[2]) Info: Riskow.alu.O_PFUMX_Z_2_BLUT_LUT4_Z.OFX (Riskow.aluO[2]) Info: loop 35: Info: Riskow.alu.O_PFUMX_Z_3_ALUT_LUT4_Z.A (Riskow.aluO[4]) Info: Riskow.alu.O_PFUMX_Z_3_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_3_ALUT) Info: Riskow.alu.O_PFUMX_Z_3_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_3_ALUT) Info: Riskow.alu.O_PFUMX_Z_3_BLUT_LUT4_Z.OFX (Riskow.aluO[4]) Info: loop 36: Info: Riskow.alu.O_PFUMX_Z_3_BLUT_LUT4_Z.C (Riskow.aluO[4]) Info: Riskow.alu.O_PFUMX_Z_3_BLUT_LUT4_Z.OFX (Riskow.aluO[4]) Info: loop 37: Info: Riskow.alu.O_PFUMX_Z_4_ALUT_LUT4_Z.A (Riskow.aluO[6]) Info: Riskow.alu.O_PFUMX_Z_4_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_4_ALUT) Info: Riskow.alu.O_PFUMX_Z_4_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_4_ALUT) Info: Riskow.alu.O_PFUMX_Z_4_BLUT_LUT4_Z.OFX (Riskow.aluO[6]) Info: loop 38: Info: Riskow.alu.O_PFUMX_Z_4_BLUT_LUT4_Z.C (Riskow.aluO[6]) Info: Riskow.alu.O_PFUMX_Z_4_BLUT_LUT4_Z.OFX (Riskow.aluO[6]) Info: loop 39: Info: Riskow.alu.O_PFUMX_Z_5_ALUT_LUT4_Z.A (Riskow.aluO[7]) Info: Riskow.alu.O_PFUMX_Z_5_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_5_ALUT) Info: Riskow.alu.O_PFUMX_Z_5_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_5_ALUT) Info: Riskow.alu.O_PFUMX_Z_5_BLUT_LUT4_Z.OFX (Riskow.aluO[7]) Info: loop 40: Info: Riskow.alu.O_PFUMX_Z_5_BLUT_LUT4_Z.C (Riskow.aluO[7]) Info: Riskow.alu.O_PFUMX_Z_5_BLUT_LUT4_Z.OFX (Riskow.aluO[7]) Info: loop 41: Info: Riskow.alu.O_PFUMX_Z_6_ALUT_LUT4_Z.A (Riskow.aluO[9]) Info: Riskow.alu.O_PFUMX_Z_6_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_6_ALUT) Info: Riskow.alu.O_PFUMX_Z_6_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_6_ALUT) Info: Riskow.alu.O_PFUMX_Z_6_BLUT_LUT4_Z.OFX (Riskow.aluO[9]) Info: loop 42: Info: Riskow.alu.O_PFUMX_Z_6_BLUT_LUT4_Z.C (Riskow.aluO[9]) Info: Riskow.alu.O_PFUMX_Z_6_BLUT_LUT4_Z.OFX (Riskow.aluO[9]) Info: loop 43: Info: Riskow.alu.O_PFUMX_Z_7_ALUT_LUT4_Z.A (Riskow.aluO[10]) Info: Riskow.alu.O_PFUMX_Z_7_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_7_ALUT) Info: Riskow.alu.O_PFUMX_Z_7_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_7_ALUT) Info: Riskow.alu.O_PFUMX_Z_7_BLUT_LUT4_Z.OFX (Riskow.aluO[10]) Info: loop 44: Info: Riskow.alu.O_PFUMX_Z_7_BLUT_LUT4_Z.C (Riskow.aluO[10]) Info: Riskow.alu.O_PFUMX_Z_7_BLUT_LUT4_Z.OFX (Riskow.aluO[10]) Info: loop 45: Info: Riskow.alu.O_PFUMX_Z_8_ALUT_LUT4_Z.A (Riskow.aluO[11]) Info: Riskow.alu.O_PFUMX_Z_8_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_8_ALUT) Info: Riskow.alu.O_PFUMX_Z_8_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_8_ALUT) Info: Riskow.alu.O_PFUMX_Z_8_BLUT_LUT4_Z.OFX (Riskow.aluO[11]) Info: loop 46: Info: Riskow.alu.O_PFUMX_Z_8_BLUT_LUT4_Z.C (Riskow.aluO[11]) Info: Riskow.alu.O_PFUMX_Z_8_BLUT_LUT4_Z.OFX (Riskow.aluO[11]) Info: loop 47: Info: Riskow.alu.O_PFUMX_Z_9_ALUT_LUT4_Z.A (Riskow.aluO[15]) Info: Riskow.alu.O_PFUMX_Z_9_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_9_ALUT) Info: Riskow.alu.O_PFUMX_Z_9_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_9_ALUT) Info: Riskow.alu.O_PFUMX_Z_9_BLUT_LUT4_Z.OFX (Riskow.aluO[15]) Info: loop 48: Info: Riskow.alu.O_PFUMX_Z_9_BLUT_LUT4_Z.C (Riskow.aluO[15]) Info: Riskow.alu.O_PFUMX_Z_9_BLUT_LUT4_Z.OFX (Riskow.aluO[15]) Info: loop 49: Info: Riskow.alu.O_PFUMX_Z_ALUT_LUT4_Z.A (Riskow.aluO[14]) Info: Riskow.alu.O_PFUMX_Z_ALUT_LUT4_Z.F (Riskow.alu.O_PFUMX_Z_ALUT) Info: Riskow.alu.O_PFUMX_Z_BLUT_LUT4_Z.F1 (Riskow.alu.O_PFUMX_Z_ALUT) Info: Riskow.alu.O_PFUMX_Z_BLUT_LUT4_Z.OFX (Riskow.aluO[14]) ERROR: Timing analysis failed due to combinational loops. 0 warnings, 1 error make: *** [/eda/processor-ci/makefiles/colorlight_i9.mk:7: colorlight_i9.config] Error 255 Traceback (most recent call last): File "/eda/processor-ci/main.py", line 79, in main( File "/eda/processor-ci/main.py", line 26, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor-ci/core/fpga.py", line 113, in build raise subprocess.CalledProcessError(process.returncode, "make") subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) Stage "Flash colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Teste colorlight_i9) Stage "Teste colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch colorlight_i9 Lock acquired on [Resource: digilent_nexys4_ddr] [Pipeline] { [Pipeline] stage [Pipeline] { (Síntese e PnR) [Pipeline] dir Running in /var/lib/jenkins/workspace/riskow/riskow [Pipeline] { [Pipeline] echo Iniciando síntese para FPGA digilent_nexys4_ddr. [Pipeline] sh + python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b digilent_nexys4_ddr Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/riskow/riskow/build_digilent_nexys4_ddr.tcl Makefile executado com sucesso. Sa��da do Makefile: Building the Design... /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/lib/jenkins/workspace/riskow/riskow/build_digilent_nexys4_ddr.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096" ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source /var/lib/jenkins/workspace/riskow/riskow/build_digilent_nexys4_ddr.tcl # read_verilog /eda/processor-ci/rtl/riskow.v read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1304.188 ; gain = 0.023 ; free physical = 2164 ; free virtual = 26537 # read_verilog /var/lib/jenkins/workspace/riskow/riskow/cpu/alu.v # read_verilog /var/lib/jenkins/workspace/riskow/riskow/cpu/comp.v # read_verilog /var/lib/jenkins/workspace/riskow/riskow/cpu/cpu.v # read_verilog /var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v # read_verilog /var/lib/jenkins/workspace/riskow/riskow/cpu/program_counter.v # read_verilog /var/lib/jenkins/workspace/riskow/riskow/cpu/register_bank.v # set ID 0x6a6a6a6a # set CLOCK_FREQ 50000000 # read_verilog /eda/processor-ci-controller/modules/uart.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v # read_verilog /eda/processor-ci-controller/src/fifo.v # read_verilog /eda/processor-ci-controller/src/reset.v # read_verilog /eda/processor-ci-controller/src/clk_divider.v # read_verilog /eda/processor-ci-controller/src/memory.v # read_verilog /eda/processor-ci-controller/src/interpreter.v # read_verilog /eda/processor-ci-controller/src/controller.v # set ID [lindex $argv 0] # set CLOCK_FREQ [lindex $argv 1] # set MEMORY_SIZE [lindex $argv 2] # read_xdc "/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc" # set_property PROCESSING_ORDER EARLY [get_files /eda/processor-ci/constraints/digilent_nexys4_ddr.xdc] # synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 195061 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2030.941 ; gain = 405.715 ; free physical = 1224 ; free virtual = 25598 --------------------------------------------------------------------------------- INFO: [Synth 8-11241] undeclared symbol 'memory_read', assumed default net type 'wire' [/eda/processor-ci/rtl/riskow.v:85] INFO: [Synth 8-11241] undeclared symbol 'memory_write', assumed default net type 'wire' [/eda/processor-ci/rtl/riskow.v:86] CRITICAL WARNING: [Synth 8-9339] data object 'reset_o' is already declared [/eda/processor-ci/rtl/riskow.v:146] INFO: [Synth 8-6826] previous declaration of 'reset_o' is from here [/eda/processor-ci/rtl/riskow.v:29] CRITICAL WARNING: [Synth 8-11152] second declaration of 'reset_o' is ignored [/eda/processor-ci/rtl/riskow.v:146] WARNING: [Synth 8-6901] identifier 'funct3' is used before its declaration [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:92] WARNING: [Synth 8-6901] identifier 'funct3' is used before its declaration [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:96] WARNING: [Synth 8-6901] identifier 'i' is used before its declaration [/var/lib/jenkins/workspace/riskow/riskow/cpu/register_bank.v:22] WARNING: [Synth 8-6901] identifier 'i' is used before its declaration [/var/lib/jenkins/workspace/riskow/riskow/cpu/register_bank.v:22] WARNING: [Synth 8-6901] identifier 'i' is used before its declaration [/var/lib/jenkins/workspace/riskow/riskow/cpu/register_bank.v:22] WARNING: [Synth 8-6901] identifier 'i' is used before its declaration [/var/lib/jenkins/workspace/riskow/riskow/cpu/register_bank.v:22] WARNING: [Synth 8-6901] identifier 'i' is used before its declaration [/var/lib/jenkins/workspace/riskow/riskow/cpu/register_bank.v:22] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16] WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15] WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16] WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17] WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84] WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85] INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor-ci/rtl/riskow.v:1] INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer Parameter ID bound to: 0 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1] Parameter COUNTER_BITS bound to: 32 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1] INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter ID bound to: 0 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213] INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1] Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1] INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1] INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1] Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1] WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268] INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1] INFO: [Synth 8-6157] synthesizing module 'CPU' [/var/lib/jenkins/workspace/riskow/riskow/cpu/cpu.v:1] INFO: [Synth 8-6157] synthesizing module 'ProgramCounter' [/var/lib/jenkins/workspace/riskow/riskow/cpu/program_counter.v:1] INFO: [Synth 8-6155] done synthesizing module 'ProgramCounter' (0#1) [/var/lib/jenkins/workspace/riskow/riskow/cpu/program_counter.v:1] INFO: [Synth 8-6157] synthesizing module 'RegisterBank' [/var/lib/jenkins/workspace/riskow/riskow/cpu/register_bank.v:1] INFO: [Synth 8-6155] done synthesizing module 'RegisterBank' (0#1) [/var/lib/jenkins/workspace/riskow/riskow/cpu/register_bank.v:1] INFO: [Synth 8-6157] synthesizing module 'ALU' [/var/lib/jenkins/workspace/riskow/riskow/cpu/alu.v:1] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/alu.v:29] INFO: [Synth 8-6155] done synthesizing module 'ALU' (0#1) [/var/lib/jenkins/workspace/riskow/riskow/cpu/alu.v:1] INFO: [Synth 8-6157] synthesizing module 'InstructionDecoder' [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:1] Parameter EXCEPTION_HANDLING bound to: 1 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:259] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:292] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:328] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:325] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:380] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:407] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:427] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:454] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:530] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:538] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:545] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:478] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:620] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:628] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:635] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:570] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:682] INFO: [Synth 8-6155] done synthesizing module 'InstructionDecoder' (0#1) [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:1] INFO: [Synth 8-6155] done synthesizing module 'CPU' (0#1) [/var/lib/jenkins/workspace/riskow/riskow/cpu/cpu.v:1] WARNING: [Synth 8-7071] port 'csrDataIn' of module 'CPU' is unconnected for instance 'Riskow' [/eda/processor-ci/rtl/riskow.v:95] WARNING: [Synth 8-7071] port 'csrDataOut' of module 'CPU' is unconnected for instance 'Riskow' [/eda/processor-ci/rtl/riskow.v:95] WARNING: [Synth 8-7071] port 'csrNumber' of module 'CPU' is unconnected for instance 'Riskow' [/eda/processor-ci/rtl/riskow.v:95] WARNING: [Synth 8-7071] port 'csrWriteEnable' of module 'CPU' is unconnected for instance 'Riskow' [/eda/processor-ci/rtl/riskow.v:95] WARNING: [Synth 8-7071] port 'instructionsExecuted' of module 'CPU' is unconnected for instance 'Riskow' [/eda/processor-ci/rtl/riskow.v:95] WARNING: [Synth 8-7023] instance 'Riskow' of module 'CPU' has 14 connections declared, but only 9 given [/eda/processor-ci/rtl/riskow.v:95] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1] Parameter CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1] WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor-ci/rtl/riskow.v:150] WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor-ci/rtl/riskow.v:150] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor-ci/rtl/riskow.v:150] INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor-ci/rtl/riskow.v:1] WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25] WARNING: [Synth 8-6014] Unused sequential element rs1_reg was removed. [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:150] WARNING: [Synth 8-6014] Unused sequential element rs2_reg was removed. [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:151] WARNING: [Synth 8-6014] Unused sequential element rd_reg was removed. [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:152] WARNING: [Synth 8-6014] Unused sequential element tmpInstruction_reg was removed. [/var/lib/jenkins/workspace/riskow/riskow/cpu/instruction_decoder.v:157] WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/riskow.v:21] WARNING: [Synth 8-3848] Net memory_read in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/riskow.v:85] WARNING: [Synth 8-3848] Net memory_write in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/riskow.v:86] WARNING: [Synth 8-3848] Net data_address in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/riskow.v:32] WARNING: [Synth 8-3848] Net data_write in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/riskow.v:32] WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2129.910 ; gain = 504.684 ; free physical = 1110 ; free virtual = 25485 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2147.723 ; gain = 522.496 ; free physical = 1107 ; free virtual = 25482 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2147.723 ; gain = 522.496 ; free physical = 1107 ; free virtual = 25482 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2147.723 ; gain = 0.000 ; free physical = 1098 ; free virtual = 25473 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc] Finished Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2298.473 ; gain = 0.000 ; free physical = 1095 ; free virtual = 25470 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2298.508 ; gain = 0.000 ; free physical = 1089 ; free virtual = 25464 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1089 ; free virtual = 25462 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1088 ; free virtual = 25461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1087 ; free virtual = 25459 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 READ | 001 | 0001 COPY_READ_BUFFER | 010 | 0100 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 COPY_WRITE_BUFFER | 001 | 0100 WRITE | 010 | 0001 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 0001 | 00 iSTATE0 | 0010 | 01 iSTATE1 | 0100 | 10 iSTATE2 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART' WARNING: [Synth 8-327] inferring latch for variable 'result_reg' [/var/lib/jenkins/workspace/riskow/riskow/cpu/alu.v:30] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RESET_COUNTER | 00 | 01 IDLE | 01 | 10 INIT | 10 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1087 ; free virtual = 25457 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 2 2 Input 32 Bit Adders := 11 3 Input 32 Bit Adders := 2 2 Input 24 Bit Adders := 2 2 Input 10 Bit Adders := 2 2 Input 8 Bit Adders := 1 2 Input 6 Bit Adders := 4 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---XORs : 2 Input 32 Bit XORs := 1 +---Registers : 64 Bit Registers := 2 32 Bit Registers := 37 24 Bit Registers := 5 12 Bit Registers := 1 10 Bit Registers := 2 8 Bit Registers := 11 7 Bit Registers := 2 6 Bit Registers := 1 4 Bit Registers := 6 3 Bit Registers := 3 1 Bit Registers := 36 +---RAMs : 32K Bit (1024 X 32 bit) RAMs := 2 64 Bit (8 X 8 bit) RAMs := 2 +---Muxes : 4 Input 64 Bit Muxes := 1 2 Input 64 Bit Muxes := 1 48 Input 64 Bit Muxes := 2 2 Input 32 Bit Muxes := 38 5 Input 32 Bit Muxes := 3 4 Input 32 Bit Muxes := 8 3 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 48 Input 24 Bit Muxes := 1 48 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 4 24 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 2 2 Input 6 Bit Muxes := 4 3 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 10 9 Input 4 Bit Muxes := 2 7 Input 4 Bit Muxes := 1 4 Input 4 Bit Muxes := 2 3 Input 4 Bit Muxes := 2 5 Input 4 Bit Muxes := 2 10 Input 4 Bit Muxes := 1 5 Input 3 Bit Muxes := 4 2 Input 3 Bit Muxes := 6 10 Input 3 Bit Muxes := 3 9 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 16 48 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 4 3 Input 2 Bit Muxes := 2 6 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 144 48 Input 1 Bit Muxes := 22 3 Input 1 Bit Muxes := 29 4 Input 1 Bit Muxes := 15 5 Input 1 Bit Muxes := 31 16 Input 1 Bit Muxes := 1 7 Input 1 Bit Muxes := 4 10 Input 1 Bit Muxes := 8 6 Input 1 Bit Muxes := 5 8 Input 1 Bit Muxes := 4 9 Input 1 Bit Muxes := 2 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:02:07 ; elapsed = 00:02:07 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1044 ; free virtual = 25422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------+---------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+---------------------+---------------+----------------+ |Interpreter | memory_mux_selector | 256x1 | LUT | |Interpreter | memory_mux_selector | 256x1 | LUT | +------------+---------------------+---------------+----------------+ Distributed RAM: Preliminary Mapping Report (see note below) +------------+-------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-------------------------+-----------+----------------------+------------------+ |Controller | Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |Controller | Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | +------------+-------------------------+-----------+----------------------+------------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:17 ; elapsed = 00:02:18 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1043 ; free virtual = 25421 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:02:35 ; elapsed = 00:02:36 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1037 ; free virtual = 25415 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------+-------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-------------------------+-----------+----------------------+------------------+ |Controller | Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |Controller | Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | +------------+-------------------------+-----------+----------------------+------------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:02:41 ; elapsed = 00:02:42 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1028 ; free virtual = 25406 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:02:49 ; elapsed = 00:02:50 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1026 ; free virtual = 25404 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:02:49 ; elapsed = 00:02:50 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1026 ; free virtual = 25404 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:51 ; elapsed = 00:02:52 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1027 ; free virtual = 25405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:02:51 ; elapsed = 00:02:52 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1027 ; free virtual = 25405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:02:51 ; elapsed = 00:02:52 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1021 ; free virtual = 25399 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:02:51 ; elapsed = 00:02:52 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1020 ; free virtual = 25398 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 3| |2 |CARRY4 | 155| |3 |LUT1 | 96| |4 |LUT2 | 294| |5 |LUT3 | 508| |6 |LUT4 | 275| |7 |LUT5 | 411| |8 |LUT6 | 1134| |9 |MUXF7 | 116| |10 |MUXF8 | 48| |11 |RAM256X1S | 256| |12 |RAM32M | 2| |13 |RAM32X1D | 4| |14 |FDRE | 1465| |15 |FDSE | 9| |16 |LD | 32| |17 |IBUF | 2| |18 |OBUF | 1| |19 |OBUFT | 2| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:02:51 ; elapsed = 00:02:52 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1019 ; free virtual = 25398 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 34 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:02:46 ; elapsed = 00:02:47 . Memory (MB): peak = 2298.508 ; gain = 522.496 ; free physical = 1024 ; free virtual = 25402 Synthesis Optimization Complete : Time (s): cpu = 00:02:52 ; elapsed = 00:02:53 . Memory (MB): peak = 2298.508 ; gain = 673.281 ; free physical = 1023 ; free virtual = 25401 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2298.508 ; gain = 0.000 ; free physical = 1270 ; free virtual = 25648 INFO: [Netlist 29-17] Analyzing 613 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc] Finished Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2370.504 ; gain = 0.000 ; free physical = 1267 ; free virtual = 25645 INFO: [Project 1-111] Unisim Transformation Summary: A total of 294 instances were transformed. LD => LDCE: 32 instances RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances Synth Design complete | Checksum: dc9bfcae INFO: [Common 17-83] Releasing license: Synthesis 79 Infos, 103 Warnings, 2 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:03:09 ; elapsed = 00:03:06 . Memory (MB): peak = 2370.539 ; gain = 1066.352 ; free physical = 1267 ; free virtual = 25646 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2033.348; main = 1779.532; forked = 397.548 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3244.113; main = 2370.508; forked = 969.652 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2434.535 ; gain = 63.996 ; free physical = 1269 ; free virtual = 25647 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 21f36e8c1 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2529.348 ; gain = 94.812 ; free physical = 1231 ; free virtual = 25609 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 21f36e8c1 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2773.316 ; gain = 0.000 ; free physical = 969 ; free virtual = 25347 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 21f36e8c1 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2773.316 ; gain = 0.000 ; free physical = 968 ; free virtual = 25346 Phase 1 Initialization | Checksum: 21f36e8c1 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2773.316 ; gain = 0.000 ; free physical = 968 ; free virtual = 25346 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 21f36e8c1 Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2773.316 ; gain = 0.000 ; free physical = 971 ; free virtual = 25350 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 21f36e8c1 Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2773.316 ; gain = 0.000 ; free physical = 971 ; free virtual = 25350 Phase 2 Timer Update And Timing Data Collection | Checksum: 21f36e8c1 Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2773.316 ; gain = 0.000 ; free physical = 971 ; free virtual = 25350 Phase 3 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 21f36e8c1 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2773.316 ; gain = 0.000 ; free physical = 967 ; free virtual = 25345 Retarget | Checksum: 21f36e8c1 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 1b4dc8876 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.75 . Memory (MB): peak = 2773.316 ; gain = 0.000 ; free physical = 966 ; free virtual = 25344 Constant propagation | Checksum: 1b4dc8876 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 14a34e8c6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.91 . Memory (MB): peak = 2773.316 ; gain = 0.000 ; free physical = 970 ; free virtual = 25348 Sweep | Checksum: 14a34e8c6 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 14a34e8c6 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2805.332 ; gain = 32.016 ; free physical = 970 ; free virtual = 25348 BUFG optimization | Checksum: 14a34e8c6 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 14a34e8c6 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2805.332 ; gain = 32.016 ; free physical = 970 ; free virtual = 25348 Shift Register Optimization | Checksum: 14a34e8c6 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 14a34e8c6 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2805.332 ; gain = 32.016 ; free physical = 970 ; free virtual = 25348 Post Processing Netlist | Checksum: 14a34e8c6 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1201489a5 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2805.332 ; gain = 32.016 ; free physical = 970 ; free virtual = 25348 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2805.332 ; gain = 0.000 ; free physical = 970 ; free virtual = 25348 Phase 9.2 Verifying Netlist Connectivity | Checksum: 1201489a5 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2805.332 ; gain = 32.016 ; free physical = 970 ; free virtual = 25348 Phase 9 Finalization | Checksum: 1201489a5 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2805.332 ; gain = 32.016 ; free physical = 970 ; free virtual = 25348 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 0 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 1201489a5 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2805.332 ; gain = 32.016 ; free physical = 970 ; free virtual = 25348 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2805.332 ; gain = 0.000 ; free physical = 970 ; free virtual = 25348 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 1201489a5 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2805.332 ; gain = 0.000 ; free physical = 970 ; free virtual = 25348 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 1201489a5 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2805.332 ; gain = 0.000 ; free physical = 970 ; free virtual = 25348 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2805.332 ; gain = 0.000 ; free physical = 970 ; free virtual = 25348 Ending Netlist Obfuscation Task | Checksum: 1201489a5 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2805.332 ; gain = 0.000 ; free physical = 970 ; free virtual = 25348 INFO: [Common 17-83] Releasing license: Implementation 18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 2805.332 ; gain = 434.793 ; free physical = 970 ; free virtual = 25348 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2837.348 ; gain = 0.000 ; free physical = 969 ; free virtual = 25348 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: ddc02975 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2837.348 ; gain = 0.000 ; free physical = 969 ; free virtual = 25348 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2837.348 ; gain = 0.000 ; free physical = 969 ; free virtual = 25348 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f82aedd1 Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2837.348 ; gain = 0.000 ; free physical = 969 ; free virtual = 25347 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 12d8f518d Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 965 ; free virtual = 25343 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 12d8f518d Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 970 ; free virtual = 25348 Phase 1 Placer Initialization | Checksum: 12d8f518d Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 970 ; free virtual = 25348 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 10530c2ce Time (s): cpu = 00:00:14 ; elapsed = 00:00:08 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 967 ; free virtual = 25345 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1da2e8a46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 966 ; free virtual = 25345 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1da2e8a46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 966 ; free virtual = 25345 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1d7640daa Time (s): cpu = 00:00:34 ; elapsed = 00:00:17 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 962 ; free virtual = 25340 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 147 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 71 nets or LUTs. Breaked 0 LUT, combined 71 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2844.375 ; gain = 0.000 ; free physical = 952 ; free virtual = 25331 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 71 | 71 | 0 | 1 | 00:00:01 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 71 | 71 | 0 | 4 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 23dda08a4 Time (s): cpu = 00:00:37 ; elapsed = 00:00:19 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 960 ; free virtual = 25338 Phase 2.4 Global Placement Core | Checksum: 19bf612bc Time (s): cpu = 00:00:44 ; elapsed = 00:00:21 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 956 ; free virtual = 25334 Phase 2 Global Placement | Checksum: 19bf612bc Time (s): cpu = 00:00:44 ; elapsed = 00:00:21 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 956 ; free virtual = 25334 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1d211a3f9 Time (s): cpu = 00:00:47 ; elapsed = 00:00:22 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 960 ; free virtual = 25338 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1232fae5c Time (s): cpu = 00:00:51 ; elapsed = 00:00:25 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 958 ; free virtual = 25336 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1908fbdbb Time (s): cpu = 00:00:52 ; elapsed = 00:00:25 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 960 ; free virtual = 25338 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1ca9c4012 Time (s): cpu = 00:00:52 ; elapsed = 00:00:25 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 960 ; free virtual = 25338 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 1984f817a Time (s): cpu = 00:00:58 ; elapsed = 00:00:27 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 949 ; free virtual = 25327 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 1d086df6d Time (s): cpu = 00:01:01 ; elapsed = 00:00:30 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 969 ; free virtual = 25347 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 212dde5f4 Time (s): cpu = 00:01:01 ; elapsed = 00:00:31 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 959 ; free virtual = 25337 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 273802b35 Time (s): cpu = 00:01:01 ; elapsed = 00:00:31 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 953 ; free virtual = 25331 Phase 3 Detail Placement | Checksum: 273802b35 Time (s): cpu = 00:01:01 ; elapsed = 00:00:31 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 963 ; free virtual = 25341 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 223b60205 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.558 | TNS=-22.126 | Phase 1 Physical Synthesis Initialization | Checksum: 19d647f0d Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2844.375 ; gain = 0.000 ; free physical = 967 ; free virtual = 25345 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 19d647f0d Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2844.375 ; gain = 0.000 ; free physical = 967 ; free virtual = 25345 Phase 4.1.1.1 BUFG Insertion | Checksum: 223b60205 Time (s): cpu = 00:01:11 ; elapsed = 00:00:36 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 967 ; free virtual = 25345 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=0.605. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1bd95c7b8 Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 966 ; free virtual = 25345 Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 966 ; free virtual = 25345 Phase 4.1 Post Commit Optimization | Checksum: 1bd95c7b8 Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 967 ; free virtual = 25345 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1bd95c7b8 Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 963 ; free virtual = 25341 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1bd95c7b8 Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 966 ; free virtual = 25345 Phase 4.3 Placer Reporting | Checksum: 1bd95c7b8 Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 967 ; free virtual = 25345 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2844.375 ; gain = 0.000 ; free physical = 967 ; free virtual = 25345 Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 967 ; free virtual = 25345 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c617a5f0 Time (s): cpu = 00:01:20 ; elapsed = 00:00:45 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 965 ; free virtual = 25343 Ending Placer Task | Checksum: 16d0ef373 Time (s): cpu = 00:01:21 ; elapsed = 00:00:45 . Memory (MB): peak = 2844.375 ; gain = 7.027 ; free physical = 966 ; free virtual = 25344 29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:01:23 ; elapsed = 00:00:46 . Memory (MB): peak = 2844.375 ; gain = 39.043 ; free physical = 966 ; free virtual = 25344 # report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt # report_utilization -file digilent_nexys4ddr_utilization_place.rpt # report_io -file digilent_nexys4ddr_io.rpt report_io: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2844.375 ; gain = 0.000 ; free physical = 965 ; free virtual = 25343 # report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2844.375 ; gain = 0.000 ; free physical = 964 ; free virtual = 25343 # report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: cddde0b8 ConstDB: 0 ShapeSum: 9f3112bb RouteDB: 0 Post Restoration Checksum: NetGraph: 8a638454 | NumContArr: aa9f6cbf | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 2ba54e64d Time (s): cpu = 00:01:19 ; elapsed = 00:01:06 . Memory (MB): peak = 2844.375 ; gain = 0.000 ; free physical = 938 ; free virtual = 25317 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 2ba54e64d Time (s): cpu = 00:01:19 ; elapsed = 00:01:06 . Memory (MB): peak = 2844.375 ; gain = 0.000 ; free physical = 938 ; free virtual = 25317 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 2ba54e64d Time (s): cpu = 00:01:19 ; elapsed = 00:01:07 . Memory (MB): peak = 2844.375 ; gain = 0.000 ; free physical = 938 ; free virtual = 25317 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2535189cf Time (s): cpu = 00:01:31 ; elapsed = 00:01:13 . Memory (MB): peak = 2844.375 ; gain = 0.000 ; free physical = 911 ; free virtual = 25289 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.763 | TNS=0.000 | WHS=-0.818 | THS=-337.767| Router Utilization Summary Global Vertical Routing Utilization = 0.0268965 % Global Horizontal Routing Utilization = 0.0117221 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 3610 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 3570 Number of Partially Routed Nets = 40 Number of Node Overlaps = 34 Phase 2 Router Initialization | Checksum: 26c2d3139 Time (s): cpu = 00:01:36 ; elapsed = 00:01:14 . Memory (MB): peak = 2844.375 ; gain = 0.000 ; free physical = 904 ; free virtual = 25283 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 26c2d3139 Time (s): cpu = 00:01:36 ; elapsed = 00:01:14 . Memory (MB): peak = 2844.375 ; gain = 0.000 ; free physical = 904 ; free virtual = 25283 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 2033a2f5c Time (s): cpu = 00:02:13 ; elapsed = 00:01:25 . Memory (MB): peak = 2944.359 ; gain = 99.984 ; free physical = 779 ; free virtual = 25158 Phase 3 Initial Routing | Checksum: 2033a2f5c Time (s): cpu = 00:02:13 ; elapsed = 00:01:25 . Memory (MB): peak = 2944.359 ; gain = 99.984 ; free physical = 779 ; free virtual = 25158 INFO: [Route 35-580] Design has 28 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +====================+===================+==================================+ | Launch Setup Clock | Launch Hold Clock | Pin | +====================+===================+==================================+ | sys_clk_pin | sys_clk_pin | Riskow/ins/imm_reg[14]/D | | sys_clk_pin | sys_clk_pin | Riskow/ins/imm_reg[30]/D | | sys_clk_pin | sys_clk_pin | Riskow/ins/imm_reg[18]/D | | sys_clk_pin | sys_clk_pin | Riskow/ins/currentState_reg[2]/D | | sys_clk_pin | sys_clk_pin | Riskow/ins/currentState_reg[0]/D | +--------------------+-------------------+----------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 654 Number of Nodes with overlaps = 121 Number of Nodes with overlaps = 66 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 21 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.818 | TNS=-10.496| WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 2c54b7bb2 Time (s): cpu = 00:03:32 ; elapsed = 00:02:15 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 714 ; free virtual = 25093 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 33 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.439 | TNS=-2.465 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 27564d9a0 Time (s): cpu = 00:03:47 ; elapsed = 00:02:28 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 716 ; free virtual = 25094 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 61 Number of Nodes with overlaps = 42 Number of Nodes with overlaps = 20 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.665 | TNS=-3.227 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 10a5f72bb Time (s): cpu = 00:04:30 ; elapsed = 00:03:07 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 713 ; free virtual = 25092 Phase 4 Rip-up And Reroute | Checksum: 10a5f72bb Time (s): cpu = 00:04:30 ; elapsed = 00:03:07 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 713 ; free virtual = 25092 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 1ba1aa545 Time (s): cpu = 00:04:32 ; elapsed = 00:03:08 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 712 ; free virtual = 25090 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.431 | TNS=-2.328 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 16fd2dec0 Time (s): cpu = 00:04:32 ; elapsed = 00:03:08 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 712 ; free virtual = 25090 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 16fd2dec0 Time (s): cpu = 00:04:32 ; elapsed = 00:03:08 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 712 ; free virtual = 25090 Phase 5 Delay and Skew Optimization | Checksum: 16fd2dec0 Time (s): cpu = 00:04:32 ; elapsed = 00:03:08 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 712 ; free virtual = 25090 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 17452a541 Time (s): cpu = 00:04:35 ; elapsed = 00:03:10 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 706 ; free virtual = 25084 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.431 | TNS=-2.328 | WHS=0.035 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 10f753596 Time (s): cpu = 00:04:35 ; elapsed = 00:03:10 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 705 ; free virtual = 25084 Phase 6 Post Hold Fix | Checksum: 10f753596 Time (s): cpu = 00:04:35 ; elapsed = 00:03:10 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 705 ; free virtual = 25083 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.968795 % Global Horizontal Routing Utilization = 1.32829 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report North Dir 1x1 Area, Max Cong = 50.4505%, No Congested Regions. South Dir 1x1 Area, Max Cong = 54.0541%, No Congested Regions. East Dir 1x1 Area, Max Cong = 57.3529%, No Congested Regions. West Dir 1x1 Area, Max Cong = 61.7647%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 7 Route finalize | Checksum: 10f753596 Time (s): cpu = 00:04:35 ; elapsed = 00:03:10 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 712 ; free virtual = 25090 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10f753596 Time (s): cpu = 00:04:35 ; elapsed = 00:03:10 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 711 ; free virtual = 25090 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1c5cf9288 Time (s): cpu = 00:04:37 ; elapsed = 00:03:11 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 711 ; free virtual = 25090 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.431 | TNS=-2.328 | WHS=0.035 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 10 Post Router Timing | Checksum: 1c5cf9288 Time (s): cpu = 00:04:39 ; elapsed = 00:03:12 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 711 ; free virtual = 25090 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: e376ae24 Time (s): cpu = 00:04:39 ; elapsed = 00:03:13 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 691 ; free virtual = 25070 Ending Routing Task | Checksum: e376ae24 Time (s): cpu = 00:04:40 ; elapsed = 00:03:13 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 701 ; free virtual = 25080 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 15 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:04:43 ; elapsed = 00:03:14 . Memory (MB): peak = 3007.359 ; gain = 162.984 ; free physical = 704 ; free virtual = 25082 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (128) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (32) 5. checking no_input_delay (1) 6. checking no_output_delay (1) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (128) -------------------------- There are 32 register/latch pins with no clock driven by root clock pin: Riskow/ins/aluOp_reg[0]/Q (HIGH) There are 32 register/latch pins with no clock driven by root clock pin: Riskow/ins/aluOp_reg[1]/Q (HIGH) There are 32 register/latch pins with no clock driven by root clock pin: Riskow/ins/aluOp_reg[2]/Q (HIGH) There are 32 register/latch pins with no clock driven by root clock pin: Riskow/ins/aluOp_reg[3]/Q (HIGH) 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (32) ------------------------------------------------- There are 32 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (1) ------------------------------ There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (1) ------------------------------- There is 1 port with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -0.401 -2.145 6 13965 0.037 0.000 0 13965 3.750 0.000 0 2524 Timing constraints are not met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin -0.401 -2.145 6 13965 0.037 0.000 0 13965 3.750 0.000 0 2524 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_nexys4ddr_route_status.rpt # report_drc -file digilent_nexys4ddr_drc.rpt Command: report_drc -file digilent_nexys4ddr_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/riskow/riskow/digilent_nexys4ddr_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_nexys4ddr_power.rpt Command: report_power -file digilent_nexys4ddr_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "digilent_nexys4_ddr.bit" Command: write_bitstream -force digilent_nexys4_ddr.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./digilent_nexys4_ddr.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 3167.039 ; gain = 103.652 ; free physical = 570 ; free virtual = 24952 INFO: [Common 17-206] Exiting Vivado at Tue Oct 8 01:12:31 2024... [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_nexys4_ddr) [Pipeline] dir Running in /var/lib/jenkins/workspace/riskow/riskow [Pipeline] { [Pipeline] echo FPGA digilent_nexys4_ddr bloqueada para flash. [Pipeline] sh + python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b digilent_nexys4_ddr -l Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/riskow/riskow/build_digilent_nexys4_ddr.tcl Makefile executado com sucesso. Sa��da do Makefile: Flashing the FPGA... /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 digilent_nexys4_ddr.bit empty Jtag frequency : requested 6.00MHz -> real 6.00MHz Open file DONE Parse file DONE load program Load SRAM: [========= ] 18.00% Load SRAM: [=================== ] 38.00% Load SRAM: [============================= ] 58.00% Load SRAM: [======================================= ] 78.00% Load SRAM: [================================================= ] 98.00% Load SRAM: [===================================================] 100.00% Done Shift IR 35 ir: 1 isc_done 1 isc_ena 0 init 1 done 1 [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Teste digilent_nexys4_ddr) [Pipeline] echo Testando FPGA digilent_nexys4_ddr. [Pipeline] dir Running in /var/lib/jenkins/workspace/riskow/riskow [Pipeline] { [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_nexys4_ddr] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] dir Running in /var/lib/jenkins/workspace/riskow/riskow [Pipeline] { [Pipeline] sh + rm -rf LICENSE Makefile README.md arch.svg build_colorlight_i9.tcl build_digilent_nexys4_ddr.tcl clockInfo.txt colorlight_i9.json constraints cpu devices digilent_nexys4_ddr.bit digilent_nexys4ddr_clock_utilization.rpt digilent_nexys4ddr_control_sets.rpt digilent_nexys4ddr_drc.rpt digilent_nexys4ddr_io.rpt digilent_nexys4ddr_power.rpt digilent_nexys4ddr_route_status.rpt digilent_nexys4ddr_timing.rpt digilent_nexys4ddr_utilization_hierarchical_place.rpt digilent_nexys4ddr_utilization_place.rpt gcc gtkwave openocd simulation.out testdata tight_setup_hold_pins.txt top.v top_tb.v xise [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE