Skip to content

Workspace

/ riscv /
.git
.Xil
core/riscv
doc
isa_sim
top_cache_axi
top_tcm_axi
top_tcm_wrapper
build_digilent_arty_a7_100t.tclMay 1, 2025, 4:57:42 AM3.61 KiB
clockInfo.txtMay 1, 2025, 4:58:39 AM375 B
digilent_arty_a7_100t.bitMay 1, 2025, 4:59:33 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptMay 1, 2025, 4:58:43 AM16.56 KiB
digilent_arty_a7_control_sets.rptMay 1, 2025, 4:58:42 AM12.48 KiB
digilent_arty_a7_drc.rptMay 1, 2025, 4:59:14 AM2.36 KiB
digilent_arty_a7_io.rptMay 1, 2025, 4:58:42 AM96.82 KiB
digilent_arty_a7_power.rptMay 1, 2025, 4:59:15 AM8.55 KiB
digilent_arty_a7_route_status.rptMay 1, 2025, 4:59:14 AM651 B
digilent_arty_a7_timing.rptMay 1, 2025, 4:59:15 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptMay 1, 2025, 4:58:42 AM3.09 KiB
digilent_arty_a7_utilization_place.rptMay 1, 2025, 4:58:42 AM10.57 KiB
LICENSEMay 1, 2025, 4:57:35 AM1.46 KiB
processor_ci_defines.vhMay 1, 2025, 4:57:42 AM300 B
README.mdMay 1, 2025, 4:57:35 AM6.48 KiB
simulation.outMay 1, 2025, 4:57:37 AM469.20 KiB