| .git |
| .Xil |
| core/riscv |
| doc |
| isa_sim |
| top_cache_axi |
| top_tcm_axi |
| top_tcm_wrapper |
| build_digilent_arty_a7_100t.tcl | May 1, 2025, 4:57:42 AM | 3.61 KiB | |
| clockInfo.txt | May 1, 2025, 4:58:39 AM | 375 B | |
| digilent_arty_a7_100t.bit | May 1, 2025, 4:59:33 AM | 3.65 MiB | |
| digilent_arty_a7_clock_utilization.rpt | May 1, 2025, 4:58:43 AM | 16.56 KiB | |
| digilent_arty_a7_control_sets.rpt | May 1, 2025, 4:58:42 AM | 12.48 KiB | |
| digilent_arty_a7_drc.rpt | May 1, 2025, 4:59:14 AM | 2.36 KiB | |
| digilent_arty_a7_io.rpt | May 1, 2025, 4:58:42 AM | 96.82 KiB | |
| digilent_arty_a7_power.rpt | May 1, 2025, 4:59:15 AM | 8.55 KiB | |
| digilent_arty_a7_route_status.rpt | May 1, 2025, 4:59:14 AM | 651 B | |
| digilent_arty_a7_timing.rpt | May 1, 2025, 4:59:15 AM | 18.47 KiB | |
| digilent_arty_a7_utilization_hierarchical_place.rpt | May 1, 2025, 4:58:42 AM | 3.09 KiB | |
| digilent_arty_a7_utilization_place.rpt | May 1, 2025, 4:58:42 AM | 10.57 KiB | |
| LICENSE | May 1, 2025, 4:57:35 AM | 1.46 KiB | |
| processor_ci_defines.vh | May 1, 2025, 4:57:42 AM | 300 B | |
| README.md | May 1, 2025, 4:57:35 AM | 6.48 KiB | |
| simulation.out | May 1, 2025, 4:57:37 AM | 469.20 KiB | |
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