![[Jenkins]](/jenkins/static/d05f6cb3/images/svgs/logo.svg){kind=logo}
Started by timer [Pipeline] Start of Pipeline [Pipeline] node Still waiting to schedule task Waiting for next available executor Running on Jenkins in /var/jenkins_home/workspace/riscado-v [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf riscado-v [Pipeline] sh + git clone --recursive --depth=1 https://github.com/zxmarcos/riscado-v riscado-v Cloning into 'riscado-v'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/riscado-v/riscado-v [Pipeline] { [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s RISCV alu.v control_unit.v program_counter.v register_file.v riscv.v load_store.v [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/riscado-v/riscado-v [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/riscado-v/riscado-v -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels Trying to read file: /var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v Results saved to /jenkins/processor_ci_utils/labels/riscado-v.json [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] Resource [colorlight_i9] did not exist. Created. Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] The resource [digilent_arty_a7_100t] is locked by build Cores-VeeR-EH2 #178 #178 since Apr 5, 2025, 3:02 AM. [Resource: digilent_arty_a7_100t] is not free, waiting for execution ... [Required resources: [digilent_arty_a7_100t]] added into queue at position 0 [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/riscado-v/riscado-v [Pipeline] { [Pipeline] echo Starting synthesis for FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b colorlight_i9 Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/riscado-v/riscado-v [Pipeline] { [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b digilent_arty_a7_100t Final configuration file generated at /var/jenkins_home/workspace/riscado-v/riscado-v/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/synlig -c /var/jenkins_home/workspace/riscado-v/riscado-v/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096 -- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' -- 1. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/riscado-v/riscado-v/alu.v Parsing Verilog input from `/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v' to AST representation. Generating RTLIL representation for module `\ALU'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v Parsing Verilog input from `/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v' to AST representation. Generating RTLIL representation for module `\ControlUnit'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v Parsing Verilog input from `/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v' to AST representation. Generating RTLIL representation for module `\ProgramCounter'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v Parsing Verilog input from `/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v' to AST representation. Generating RTLIL representation for module `\RegisterFile'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v Parsing Verilog input from `/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v' to AST representation. Generating RTLIL representation for module `\RISCV'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v Parsing Verilog input from `/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v' to AST representation. Lexer warning: The SystemVerilog keyword `byte' (at /var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:14) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `byte' (at /var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:18) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `byte' (at /var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:18) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `byte' (at /var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:18) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\ByteReader'. Generating RTLIL representation for module `\HalfReader'. Generating RTLIL representation for module `\ByteWriter'. Generating RTLIL representation for module `\HalfWriter'. Generating RTLIL representation for module `\LoadStore'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: /eda/processor_ci/rtl/riscado-v.v Parsing Verilog input from `/eda/processor_ci/rtl/riscado-v.v' to AST representation. Generating RTLIL representation for module `\processorci_top'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation. Generating RTLIL representation for module `\ClkDivider'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation. Generating RTLIL representation for module `\Interpreter'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation. Generating RTLIL representation for module `\Controller'. Successfully finished Verilog frontend. 17. Executing SYNTH_ECP5 pass. 17.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_sim.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 17.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_bb.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 17.3. Executing HIERARCHY pass (managing design hierarchy). 17.3.1. Analyzing design hierarchy.. Top module: \processorci_top Used module: \ResetBootSystem Used module: \RISCV Used module: \ALU Used module: \ProgramCounter Used module: \RegisterFile Used module: \LoadStore Used module: \HalfReader Used module: \ByteReader Used module: \HalfWriter Used module: \ByteWriter Used module: \ControlUnit Used module: \Controller Used module: \Memory Used module: \UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \CYCLES = 20 17.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 17.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 17.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 17.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 17.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 17.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 17.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 17.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 17.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 17.3.11. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \RISCV Used module: \ALU Used module: \ProgramCounter Used module: \RegisterFile Used module: \LoadStore Used module: \HalfReader Used module: \ByteReader Used module: \HalfWriter Used module: \ByteWriter Used module: \ControlUnit Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: \Memory Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 17.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 17.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 17.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'. 17.3.15. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \RISCV Used module: \ALU Used module: \ProgramCounter Used module: \RegisterFile Used module: \LoadStore Used module: \HalfReader Used module: \ByteReader Used module: \HalfWriter Used module: \ByteWriter Used module: \ControlUnit Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 17.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 17.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 17.3.18. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \RISCV Used module: \ALU Used module: \ProgramCounter Used module: \RegisterFile Used module: \LoadStore Used module: \HalfReader Used module: \ByteReader Used module: \HalfWriter Used module: \ByteWriter Used module: \ControlUnit Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider 17.3.19. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \RISCV Used module: \ALU Used module: \ProgramCounter Used module: \RegisterFile Used module: \LoadStore Used module: \HalfReader Used module: \ByteReader Used module: \HalfWriter Used module: \ByteWriter Used module: \ControlUnit Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'. Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'. Removing unused module `\Controller'. Removing unused module `\Interpreter'. Removing unused module `\Memory'. Removing unused module `\ClkDivider'. Removing unused module `\ResetBootSystem'. Removing unused module `\FIFO'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\UART'. Removed 14 unused modules. Module processorci_top directly or indirectly displays text -> setting "keep" attribute. Module RISCV directly or indirectly displays text -> setting "keep" attribute. Module ControlUnit directly or indirectly displays text -> setting "keep" attribute. 17.4. Executing PROC pass (convert processes to netlists). 17.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$634'. Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$816'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$816'. Cleaned up 2 empty switches. 17.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$741 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$693 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$635 in module TRELLIS_DPR16X4. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$996 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$988 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1189 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1187 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1179 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1176 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1170 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1165 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1160 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1151 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1138 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1136 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1128 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1114 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1108 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1103 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1090 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1081 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1045 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1037 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1037 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1032 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1027 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$1022 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$805 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$794 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$744 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100 in module RegisterFile. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:17$63 in module ProgramCounter. Marked 25 switch rules as full_case in process $proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16 in module ControlUnit. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:16$1 in module ALU. Removed a total of 1 dead cases. 17.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 4 redundant assignments. Promoted 124 assignments to connections. 17.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$742'. Set init value: \Q = 1'0 Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1021'. Set init value: \read_ptr = 6'000000 Set init value: \write_ptr = 6'000000 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1191'. Set init value: \i = 0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1144'. Set init value: \i = 0 Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1096'. Set init value: \clk_o_auto = 1'0 Set init value: \clk_counter = 0 Set init value: \pulse_counter = 0 Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1074'. Set init value: \state = 8'00000000 Set init value: \counter = 8'00000000 Set init value: \read_buffer = 0 Set init value: \timeout = 0 Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000 Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1044'. Set init value: \read_response = 1'0 Set init value: \write_response = 1'0 Set init value: \read_data = 0 Set init value: \uart_tx_en = 1'0 Set init value: \tx_fifo_read = 1'0 Set init value: \tx_fifo_write = 1'0 Set init value: \rx_fifo_read = 1'0 Set init value: \rx_fifo_write = 1'0 Set init value: \uart_tx_data = 8'00000000 Set init value: \tx_fifo_write_data = 8'00000000 Set init value: \rx_fifo_write_data = 8'00000000 Set init value: \counter_write = 3'000 Set init value: \counter_read = 3'000 Set init value: \state_read = 4'0000 Set init value: \state_write = 4'0000 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$751'. Set init value: \state = 2'01 Set init value: \reset_o = 1'0 Set init value: \counter = 6'000000 Found init rule in `\RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:16$206'. Set init value: \ir = 0 Found init rule in `\ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:15$65'. Set init value: \pc = 0 Found init rule in `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:41$62'. Set init value: \branchTestTrue = 1'0 17.4.5. Executing PROC_ARST pass (detect async resets in processes). 17.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~129 debug messages> 17.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$742'. Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$741'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$693'. 1/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$692_EN[3:0]$699 2/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$692_DATA[3:0]$698 3/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$692_ADDR[3:0]$697 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$635'. 1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$633_EN[3:0]$641 2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$633_DATA[3:0]$640 3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$633_ADDR[3:0]$639 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$634'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1021'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'. 1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$1008 2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_DATA[7:0]$1007 3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR[5:0]$1006 4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$1002 5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_DATA[7:0]$1001 6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR[5:0]$1000 7/7: $0\write_ptr[5:0] Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$988'. 1/2: $0\read_ptr[5:0] 2/2: $0\read_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1191'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1189'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1187'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1179'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1176'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1170'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1165'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1160'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1151'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1144'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1138'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1136'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1128'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1114'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1108'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1103'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1096'. Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1090'. 1/1: $0\pulse_counter[31:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1081'. 1/2: $0\clk_counter[31:0] 2/2: $0\clk_o_auto[0:0] Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1074'. Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. 1/28: $0\state[7:0] 2/28: $0\reset_bus[0:0] 3/28: $0\memory_write[0:0] 4/28: $0\memory_read[0:0] 5/28: $0\write_pulse[0:0] 6/28: $0\core_reset[0:0] 7/28: $0\communication_write[0:0] 8/28: $0\communication_read[0:0] 9/28: $0\temp_buffer[63:0] 10/28: $0\accumulator[63:0] 11/28: $0\timeout_counter[31:0] 12/28: $0\timeout[31:0] 13/28: $0\read_buffer[31:0] 14/28: $0\communication_buffer[31:0] 15/28: $0\num_of_positions[23:0] 16/28: $0\num_of_pages[23:0] 17/28: $0\return_state[7:0] 18/28: $0\memory_page_number[23:0] 19/28: $0\memory_mux_selector[0:0] 20/28: $0\end_position[31:0] 21/28: $0\memory_page_size[23:0] 22/28: $0\bus_mode[0:0] 23/28: $0\num_of_cycles_to_pulse[31:0] 24/28: $0\core_clk_enable[0:0] 25/28: $0\communication_write_data[31:0] 26/28: $0\counter[7:0] 27/28: $0\write_data[31:0] 28/28: $0\address[31:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1044'. Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'. 1/4: $0\tx_fifo_read[0:0] 2/4: $0\uart_tx_en[0:0] 3/4: $0\tx_fifo_read_state[1:0] 4/4: $0\uart_tx_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1032'. 1/2: $0\rx_fifo_write[0:0] 2/2: $0\rx_fifo_write_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'. 1/6: $0\tx_fifo_write[0:0] 2/6: $0\write_response[0:0] 3/6: $0\state_write[3:0] 4/6: $0\counter_write[2:0] 5/6: $0\write_data_buffer[31:0] 6/6: $0\tx_fifo_write_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'. 1/5: $0\read_response[0:0] 2/5: $0\rx_fifo_read[0:0] 3/5: $0\state_read[3:0] 4/5: $0\counter_read[2:0] 5/5: $0\read_data[31:0] Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$815'. Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'. 1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$814 2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_DATA[31:0]$813 3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_ADDR[31:0]$812 4/4: $0\read_sync[31:0] Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$794'. 1/1: $0\finish_execution[0:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$751'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$744'. 1/3: $0\counter[5:0] 2/3: $0\reset_o[0:0] 3/3: $0\state[1:0] Creating decoders for process `\RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:16$206'. Creating decoders for process `\RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:40$181'. 1/1: $0\ir[31:0] Creating decoders for process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. Creating decoders for process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100'. 1/3: $1$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$108 2/3: $1$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_DATA[31:0]$107 3/3: $1$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_ADDR[4:0]$106 Creating decoders for process `\ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:15$65'. Creating decoders for process `\ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:17$63'. 1/2: $0\pc[31:0] 2/2: $0\prevPc[31:0] Creating decoders for process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:41$62'. Creating decoders for process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. 1/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:317$61_EN 2/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:221$50_EN 3/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:198$47_EN 4/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:154$37_EN 5/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:135$31_EN 6/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:116$27_EN 7/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:104$25_EN 8/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:94$23_EN 9/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:90$21_EN 10/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:83$20_EN 11/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:63$18_EN 12/26: $0\branchTestTrue[0:0] 13/26: $0\state[2:0] 14/26: $0\readSignExtend[0:0] 15/26: $0\writeLen[1:0] 16/26: $0\readLen[1:0] 17/26: $0\aluOperation[3:0] 18/26: $0\aluSrcB[2:0] 19/26: $0\aluSrcA[1:0] 20/26: $0\pcWriteEnable[0:0] 21/26: $0\regWriteEnable[0:0] 22/26: $0\regDataSrc[1:0] 23/26: $0\incrementPc[0:0] 24/26: $0\addressIsPc[0:0] 25/26: $0\irWriteEnable[0:0] 26/26: $0\writeEnable[0:0] Creating decoders for process `\ALU.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:16$1'. 1/1: $1\res[31:0] 17.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1160'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1103'. No latch inferred for signal `\RegisterFile.\i' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$67_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$68_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$69_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$70_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$71_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$72_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$73_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$74_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$75_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$76_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$77_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$78_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$79_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$80_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$81_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$82_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$83_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$84_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$85_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$86_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$87_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$88_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$89_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$90_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$91_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$92_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$93_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$94_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$95_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$96_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$97_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$98_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. No latch inferred for signal `\ALU.\res' from process `\ALU.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:16$1'. 17.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$741'. created $dff cell `$procdff$3477' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$677_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$678_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$679_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$680_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$681_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$682_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$683_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$684_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$685_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$686_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$687_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$688_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$689_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$690_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$691_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$692_ADDR' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$693'. created $dff cell `$procdff$3478' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$692_DATA' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$693'. created $dff cell `$procdff$3479' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$692_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$693'. created $dff cell `$procdff$3480' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$617_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$618_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$619_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$620_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$621_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$622_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$623_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$624_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$625_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$626_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$627_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$628_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$629_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$630_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$631_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$632_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$633_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$635'. created $dff cell `$procdff$3481' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$633_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$635'. created $dff cell `$procdff$3482' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$633_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$635'. created $dff cell `$procdff$3483' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$634'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'. created $dff cell `$procdff$3484' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'. created $dff cell `$procdff$3485' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'. created $dff cell `$procdff$3486' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'. created $dff cell `$procdff$3487' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$988'. created $dff cell `$procdff$3488' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$988'. created $dff cell `$procdff$3489' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1189'. created $dff cell `$procdff$3490' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1189'. created $dff cell `$procdff$3491' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1187'. created $dff cell `$procdff$3492' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1179'. created $dff cell `$procdff$3493' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1176'. created $dff cell `$procdff$3494' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1170'. created $dff cell `$procdff$3495' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1165'. created $dff cell `$procdff$3496' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1165'. created $dff cell `$procdff$3497' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1151'. created $dff cell `$procdff$3498' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1138'. created $dff cell `$procdff$3499' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1136'. created $dff cell `$procdff$3500' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1128'. created $dff cell `$procdff$3501' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1114'. created $dff cell `$procdff$3502' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1108'. created $dff cell `$procdff$3503' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1108'. created $dff cell `$procdff$3504' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1090'. created $dff cell `$procdff$3505' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1081'. created $dff cell `$procdff$3506' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1081'. created $dff cell `$procdff$3507' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3508' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3509' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3510' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3511' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3512' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3513' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3514' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3515' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3516' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3517' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3518' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3519' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3520' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3521' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3522' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3523' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3524' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3525' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3526' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3527' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3528' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3529' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3530' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3531' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3532' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3533' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3534' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. created $dff cell `$procdff$3535' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'. created $dff cell `$procdff$3536' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'. created $dff cell `$procdff$3537' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'. created $dff cell `$procdff$3538' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'. created $dff cell `$procdff$3539' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1032'. created $dff cell `$procdff$3540' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1032'. created $dff cell `$procdff$3541' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'. created $dff cell `$procdff$3542' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'. created $dff cell `$procdff$3543' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'. created $dff cell `$procdff$3544' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'. created $dff cell `$procdff$3545' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'. created $dff cell `$procdff$3546' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'. created $dff cell `$procdff$3547' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'. created $dff cell `$procdff$3548' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'. created $dff cell `$procdff$3549' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'. created $dff cell `$procdff$3550' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'. created $dff cell `$procdff$3551' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'. created $dff cell `$procdff$3552' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$815'. created $dff cell `$procdff$3553' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$815'. created $dff cell `$procdff$3554' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'. created $dff cell `$procdff$3555' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'. created $dff cell `$procdff$3556' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'. created $dff cell `$procdff$3557' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'. created $dff cell `$procdff$3558' with positive edge clock. Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$794'. created $dff cell `$procdff$3559' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$744'. created $dff cell `$procdff$3560' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$744'. created $dff cell `$procdff$3561' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$744'. created $dff cell `$procdff$3562' with positive edge clock. Creating register for signal `\RISCV.\ir' using process `\RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:40$181'. created $dff cell `$procdff$3563' with positive edge clock. Creating register for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_ADDR' using process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100'. created $dff cell `$procdff$3564' with positive edge clock. Creating register for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_DATA' using process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100'. created $dff cell `$procdff$3565' with positive edge clock. Creating register for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN' using process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100'. created $dff cell `$procdff$3566' with positive edge clock. Creating register for signal `\ProgramCounter.\prevPc' using process `\ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:17$63'. created $dff cell `$procdff$3567' with positive edge clock. Creating register for signal `\ProgramCounter.\pc' using process `\ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:17$63'. created $dff cell `$procdff$3568' with positive edge clock. Creating register for signal `\ControlUnit.\writeEnable' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3569' with positive edge clock. Creating register for signal `\ControlUnit.\irWriteEnable' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3570' with positive edge clock. Creating register for signal `\ControlUnit.\addressIsPc' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3571' with positive edge clock. Creating register for signal `\ControlUnit.\incrementPc' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3572' with positive edge clock. Creating register for signal `\ControlUnit.\regDataSrc' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3573' with positive edge clock. Creating register for signal `\ControlUnit.\regWriteEnable' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3574' with positive edge clock. Creating register for signal `\ControlUnit.\pcWriteEnable' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3575' with positive edge clock. Creating register for signal `\ControlUnit.\aluSrcA' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3576' with positive edge clock. Creating register for signal `\ControlUnit.\aluSrcB' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3577' with positive edge clock. Creating register for signal `\ControlUnit.\aluOperation' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3578' with positive edge clock. Creating register for signal `\ControlUnit.\readLen' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3579' with positive edge clock. Creating register for signal `\ControlUnit.\writeLen' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3580' with positive edge clock. Creating register for signal `\ControlUnit.\readSignExtend' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3581' with positive edge clock. Creating register for signal `\ControlUnit.\state' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3582' with positive edge clock. Creating register for signal `\ControlUnit.\branchTestTrue' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. created $dff cell `$procdff$3583' with positive edge clock. 17.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 17.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$742'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$741'. Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$741'. Removing empty process `DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$716'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$693'. Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$659'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$635'. Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$634'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1021'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$988'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$988'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1191'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1189'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1189'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1187'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1187'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1179'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1179'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1176'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1176'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1170'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1170'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1165'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1165'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1160'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1160'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1151'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1151'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1144'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1138'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1138'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1136'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1136'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1128'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1128'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1114'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1114'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1108'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1108'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1103'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1103'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1096'. Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1090'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1090'. Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1081'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1081'. Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1074'. Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1044'. Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'. Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1032'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1032'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$815'. Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'. Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$794'. Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$794'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$751'. Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$744'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$744'. Removing empty process `RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:16$206'. Found and cleaned up 1 empty switch in `\RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:40$181'. Removing empty process `RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:40$181'. Removing empty process `RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'. Found and cleaned up 1 empty switch in `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100'. Removing empty process `RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100'. Removing empty process `ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:15$65'. Found and cleaned up 3 empty switches in `\ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:17$63'. Removing empty process `ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:17$63'. Removing empty process `ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:41$62'. Found and cleaned up 30 empty switches in `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. Removing empty process `ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'. Found and cleaned up 1 empty switch in `\ALU.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:16$1'. Removing empty process `ALU.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:16$1'. Cleaned up 129 empty switches. 17.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. <suppressed ~5 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. <suppressed ~21 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. <suppressed ~19 debug messages> Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. <suppressed ~9 debug messages> Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. <suppressed ~15 debug messages> Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. <suppressed ~24 debug messages> Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. <suppressed ~3 debug messages> Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. <suppressed ~26 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~8 debug messages> Optimizing module processorci_top. Optimizing module LoadStore. <suppressed ~2 debug messages> Optimizing module HalfWriter. <suppressed ~1 debug messages> Optimizing module ByteWriter. <suppressed ~1 debug messages> Optimizing module HalfReader. <suppressed ~1 debug messages> Optimizing module ByteReader. <suppressed ~1 debug messages> Optimizing module RISCV. <suppressed ~3 debug messages> Optimizing module RegisterFile. <suppressed ~3 debug messages> Optimizing module ProgramCounter. Optimizing module ControlUnit. <suppressed ~7 debug messages> Optimizing module ALU. <suppressed ~1 debug messages> 17.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module LoadStore. Deleting now unused module HalfWriter. Deleting now unused module ByteWriter. Deleting now unused module HalfReader. Deleting now unused module ByteReader. Deleting now unused module RISCV. Deleting now unused module RegisterFile. Deleting now unused module ProgramCounter. Deleting now unused module ControlUnit. Deleting now unused module ALU. <suppressed ~21 debug messages> 17.6. Executing TRIBUF pass. 17.7. Executing DEMINOUT pass (demote inout ports to input or output). 17.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~50 debug messages> 17.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 82 unused cells and 1002 unused wires. <suppressed ~102 debug messages> 17.10. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Warning: Wire processorci_top.\miso is used but has no driver. Warning: Wire processorci_top.\intr is used but has no driver. Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [31] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [30] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [29] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [28] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [27] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [26] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [25] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [24] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [23] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [22] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [21] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [20] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [19] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [18] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [17] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [16] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [15] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [14] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [13] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [12] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [11] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [10] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [9] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [8] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [7] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [6] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [5] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [4] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [3] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [2] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [1] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [0] is used but has no driver. Found and reported 35 problems. 17.11. Executing OPT pass (performing simple optimizations). 17.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~567 debug messages> Removed a total of 189 cells. 17.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1219. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1225. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1231. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1219. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1225. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1231. Removed 6 multiplexer ports. <suppressed ~148 debug messages> 17.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1880: { $auto$opt_reduce.cc:137:opt_pmux$3611 $auto$opt_reduce.cc:137:opt_pmux$3609 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1949: $auto$opt_reduce.cc:137:opt_pmux$3613 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1974: { $flatten\Controller.\Interpreter.$procmux$1595_CMP $auto$opt_reduce.cc:137:opt_pmux$3615 $flatten\Controller.\Interpreter.$procmux$1585_CMP } Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2465: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2002: { $flatten\Controller.\Interpreter.$procmux$1581_CMP $flatten\Controller.\Interpreter.$procmux$1574_CMP $flatten\Controller.\Interpreter.$procmux$1563_CMP $flatten\Controller.\Interpreter.$procmux$1557_CMP $auto$opt_reduce.cc:137:opt_pmux$3617 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2034: { $auto$opt_reduce.cc:137:opt_pmux$3621 $auto$opt_reduce.cc:137:opt_pmux$3619 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2116: { $flatten\Controller.\Interpreter.$procmux$1575_CMP $auto$opt_reduce.cc:137:opt_pmux$3623 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2127: { $flatten\Controller.\Interpreter.$procmux$1716_CMP $flatten\Controller.\Interpreter.$procmux$1615_CMP $auto$opt_reduce.cc:137:opt_pmux$3625 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2137: { $flatten\Controller.\Interpreter.$procmux$1614_CMP $auto$opt_reduce.cc:137:opt_pmux$3629 $auto$opt_reduce.cc:137:opt_pmux$3627 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2213: { $auto$opt_reduce.cc:137:opt_pmux$3631 $flatten\Controller.\Interpreter.$procmux$1614_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1555: { $flatten\Controller.\Interpreter.$procmux$1649_CMP $flatten\Controller.\Interpreter.$procmux$1645_CMP $flatten\Controller.\Interpreter.$procmux$1641_CMP $flatten\Controller.\Interpreter.$procmux$1615_CMP $flatten\Controller.\Interpreter.$procmux$1614_CMP $flatten\Controller.\Interpreter.$procmux$1610_CMP $flatten\Controller.\Interpreter.$procmux$1609_CMP $flatten\Controller.\Interpreter.$procmux$1605_CMP $flatten\Controller.\Interpreter.$procmux$1595_CMP $flatten\Controller.\Interpreter.$procmux$1591_CMP $auto$opt_reduce.cc:137:opt_pmux$3639 $flatten\Controller.\Interpreter.$procmux$1586_CMP $flatten\Controller.\Interpreter.$procmux$1585_CMP $auto$opt_reduce.cc:137:opt_pmux$3637 $flatten\Controller.\Interpreter.$procmux$1580_CMP $flatten\Controller.\Interpreter.$procmux$1579_CMP $flatten\Controller.\Interpreter.$procmux$1574_CMP $flatten\Controller.\Interpreter.$procmux$1570_CMP $flatten\Controller.\Interpreter.$procmux$1569_CMP $auto$opt_reduce.cc:137:opt_pmux$3635 $flatten\Controller.\Interpreter.$procmux$1563_CMP $flatten\Controller.\Interpreter.$procmux$1562_CMP $flatten\Controller.\Interpreter.$procmux$1561_CMP $auto$opt_reduce.cc:137:opt_pmux$3633 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2237: { $flatten\Controller.\Interpreter.$procmux$1682_CMP $flatten\Controller.\Interpreter.$procmux$1681_CMP $auto$opt_reduce.cc:137:opt_pmux$3641 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2263: { $auto$opt_reduce.cc:137:opt_pmux$3643 $flatten\Controller.\Interpreter.$procmux$1681_CMP $flatten\Controller.\Interpreter.$procmux$1600_CMP $flatten\Controller.\Interpreter.$procmux$1595_CMP $flatten\Controller.\Interpreter.$procmux$1585_CMP } Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2465: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] } New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2333: $auto$opt_reduce.cc:137:opt_pmux$3645 New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2397: $auto$opt_reduce.cc:137:opt_pmux$3647 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1827: { $flatten\Controller.\Interpreter.$procmux$1595_CMP $auto$opt_reduce.cc:137:opt_pmux$3649 $flatten\Controller.\Interpreter.$procmux$1585_CMP } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1655: $auto$opt_reduce.cc:137:opt_pmux$3651 New ctrl vector for $pmux cell $flatten\Riscado_V.\ctrlUnit.$procmux$2763: $auto$opt_reduce.cc:137:opt_pmux$3653 New ctrl vector for $pmux cell $flatten\Riscado_V.\ctrlUnit.$procmux$2875: $auto$opt_reduce.cc:137:opt_pmux$3655 New ctrl vector for $pmux cell $flatten\Riscado_V.\ctrlUnit.$procmux$2972: { $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP $auto$opt_reduce.cc:137:opt_pmux$3659 $auto$opt_reduce.cc:137:opt_pmux$3657 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1679: $auto$opt_reduce.cc:137:opt_pmux$3661 New ctrl vector for $pmux cell $flatten\Riscado_V.\ctrlUnit.$procmux$3045: { $auto$opt_reduce.cc:137:opt_pmux$3665 $auto$opt_reduce.cc:137:opt_pmux$3663 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1701: $auto$opt_reduce.cc:137:opt_pmux$3667 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1712: $auto$opt_reduce.cc:137:opt_pmux$3669 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1760: $auto$opt_reduce.cc:137:opt_pmux$3671 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1802: $auto$opt_reduce.cc:137:opt_pmux$3673 Consolidated identical input bits for $mux cell $flatten\Riscado_V.\registerFile.$procmux$2528: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 New ports: A=1'0, B=1'1, Y=$flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] New connections: $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [31:1] = { $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] } Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1234: Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$1008, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1234: Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$1008, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] } Optimizing cells in module \processorci_top. Performed a total of 32 changes. 17.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~60 debug messages> Removed a total of 20 cells. 17.11.6. Executing OPT_DFF pass (perform DFF optimizations). 17.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 227 unused wires. <suppressed ~13 debug messages> 17.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.11.9. Rerunning OPT passes. (Maybe there is more to do..) 17.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~157 debug messages> 17.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1827: { $auto$opt_reduce.cc:137:opt_pmux$3615 $auto$opt_reduce.cc:137:opt_pmux$3675 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1974: { $auto$opt_reduce.cc:137:opt_pmux$3615 $auto$opt_reduce.cc:137:opt_pmux$3677 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2263: { $auto$opt_reduce.cc:137:opt_pmux$3643 $flatten\Controller.\Interpreter.$procmux$1681_CMP $flatten\Controller.\Interpreter.$procmux$1600_CMP $auto$opt_reduce.cc:137:opt_pmux$3679 } Optimizing cells in module \processorci_top. Performed a total of 3 changes. 17.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 17.11.13. Executing OPT_DFF pass (perform DFF optimizations). 17.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 2 unused wires. <suppressed ~1 debug messages> 17.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.11.16. Rerunning OPT passes. (Maybe there is more to do..) 17.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~157 debug messages> 17.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 17.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.11.20. Executing OPT_DFF pass (perform DFF optimizations). 17.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 17.11.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.11.23. Finished OPT passes. (There is nothing left to do.) 17.12. Executing FSM pass (extract and optimize FSM). 17.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking processorci_top.Controller.Interpreter.return_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state. Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking processorci_top.Controller.Uart.state_read as FSM state register: Register has an initialization value. Not marking processorci_top.Controller.Uart.state_write as FSM state register: Register has an initialization value. Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state. Not marking processorci_top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. Found FSM state register processorci_top.Riscado_V.ctrlUnit.aluOperation. Found FSM state register processorci_top.Riscado_V.ctrlUnit.aluSrcA. Found FSM state register processorci_top.Riscado_V.ctrlUnit.aluSrcB. Found FSM state register processorci_top.Riscado_V.ctrlUnit.readLen. Found FSM state register processorci_top.Riscado_V.ctrlUnit.regDataSrc. Found FSM state register processorci_top.Riscado_V.ctrlUnit.state. Found FSM state register processorci_top.Riscado_V.ctrlUnit.writeLen. 17.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$3492 root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1155_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1168_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1181_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1167_Y found state code: 3'000 found ctrl input: \Controller.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \Controller.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1181_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1172_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1168_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1167_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1155_Y ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done } ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1155_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1167_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1168_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1172_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1181_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'00-- -> 3'001 8'01010001 transition: 3'000 4'01-- -> 3'000 8'01010000 transition: 3'000 4'1--- -> 3'000 8'01010000 transition: 3'010 4'0--0 -> 3'010 8'00100010 transition: 3'010 4'0--1 -> 3'011 8'00100011 transition: 3'010 4'1--- -> 3'000 8'00100000 transition: 3'001 4'0-0- -> 3'001 8'00011001 transition: 3'001 4'0-1- -> 3'010 8'00011010 transition: 3'001 4'1--- -> 3'000 8'00011000 transition: 3'011 4'0-0- -> 3'011 8'10010011 transition: 3'011 4'0-1- -> 3'000 8'10010000 transition: 3'011 4'1--- -> 3'000 8'10010000 Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Controller.\Uart.$procdff$3539 root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\Controller.\Uart.$procmux$2294_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2289_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2296_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2283_CMP found state code: 2'00 found state code: 2'11 found state code: 2'10 found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1041_Y found state code: 2'01 found ctrl output: $flatten\Controller.\Uart.$procmux$2283_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2289_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2294_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2296_CMP ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1041_Y } ctrl outputs: { $flatten\Controller.\Uart.$procmux$2296_CMP $flatten\Controller.\Uart.$procmux$2294_CMP $flatten\Controller.\Uart.$procmux$2289_CMP $flatten\Controller.\Uart.$procmux$2283_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] } transition: 2'00 2'00 -> 2'00 6'000100 transition: 2'00 2'01 -> 2'01 6'000101 transition: 2'00 2'1- -> 2'00 6'000100 transition: 2'10 2'0- -> 2'11 6'001011 transition: 2'10 2'1- -> 2'00 6'001000 transition: 2'01 2'0- -> 2'10 6'100010 transition: 2'01 2'1- -> 2'00 6'100000 transition: 2'11 2'0- -> 2'00 6'010000 transition: 2'11 2'1- -> 2'00 6'010000 Extracting FSM `\Riscado_V.ctrlUnit.aluOperation' from module `\processorci_top'. found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3578 root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\aluOperation[3:0] found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y found state code: 4'0000 found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$3663 found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$3665 found state code: 4'1100 found state code: 4'0011 found state code: 4'0010 found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$3046_CMP found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2764_CMP found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2973_CMP found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2765_CMP found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$3060_CMP found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2766_CMP found state code: 4'0111 found state code: 4'0110 found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:123$28_Y found state code: 4'0101 found state code: 4'1101 found state code: 4'0100 found state code: 4'0001 found state code: 4'1000 found state code: 4'1010 found state code: 4'1001 found ctrl output: $flatten\Riscado_V.\alu.$procmux$3465_CMP found ctrl output: $flatten\Riscado_V.\alu.$procmux$3466_CMP found ctrl output: $flatten\Riscado_V.\alu.$procmux$3467_CMP found ctrl output: $flatten\Riscado_V.\alu.$procmux$3468_CMP found ctrl output: $flatten\Riscado_V.\alu.$procmux$3469_CMP found ctrl output: $flatten\Riscado_V.\alu.$procmux$3470_CMP found ctrl output: $flatten\Riscado_V.\alu.$procmux$3471_CMP found ctrl output: $flatten\Riscado_V.\alu.$procmux$3472_CMP found ctrl output: $flatten\Riscado_V.\alu.$procmux$3473_CMP found ctrl output: $flatten\Riscado_V.\alu.$procmux$3474_CMP found ctrl output: $flatten\Riscado_V.\alu.$procmux$3475_CMP found ctrl output: $flatten\Riscado_V.\alu.$procmux$3476_CMP ctrl inputs: { $flatten\Riscado_V.\ctrlUnit.$procmux$3060_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$3046_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2973_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2766_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2765_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2764_CMP $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:123$28_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y $auto$opt_reduce.cc:137:opt_pmux$3665 $auto$opt_reduce.cc:137:opt_pmux$3663 \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\Riscado_V.\ctrlUnit.$0\aluOperation[3:0] $flatten\Riscado_V.\alu.$procmux$3476_CMP $flatten\Riscado_V.\alu.$procmux$3475_CMP $flatten\Riscado_V.\alu.$procmux$3474_CMP $flatten\Riscado_V.\alu.$procmux$3473_CMP $flatten\Riscado_V.\alu.$procmux$3472_CMP $flatten\Riscado_V.\alu.$procmux$3471_CMP $flatten\Riscado_V.\alu.$procmux$3470_CMP $flatten\Riscado_V.\alu.$procmux$3469_CMP $flatten\Riscado_V.\alu.$procmux$3465_CMP $flatten\Riscado_V.\alu.$procmux$3466_CMP $flatten\Riscado_V.\alu.$procmux$3467_CMP $flatten\Riscado_V.\alu.$procmux$3468_CMP } transition: 4'0000 25'--------0000--00-00000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'--------1000-000-00000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'--------1000-100-00000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'---------100-000-00000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'---------100-100-00000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'----------10-000-00000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'----------10-100-00000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'-----------1-000-00000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'-----------1-100-00000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'------------0010-00000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'------------1010-00000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'-------------110-00000000 -> 4'1100 16'1100100000000000 transition: 4'0000 25'-------------110-000001-0 -> 4'0010 16'0010100000000000 transition: 4'0000 25'-------------110-00000-10 -> 4'0011 16'0011100000000000 transition: 4'0000 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx100000000000 <ignored invalid transition!> transition: 4'0000 25'-----1---------1000000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'-----1---------1100000--0 -> 4'1000 16'1000100000000000 transition: 4'0000 25'----1----------1-00000--0 -> 4'0001 16'0001100000000000 transition: 4'0000 25'---1-----------1-00000--0 -> 4'0010 16'0010100000000000 transition: 4'0000 25'1--------------1-00000--0 -> 4'0011 16'0011100000000000 transition: 4'0000 25'------1--------1-00000--0 -> 4'0100 16'0100100000000000 transition: 4'0000 25'--1------------1000000--0 -> 4'0101 16'0101100000000000 transition: 4'0000 25'--1------------1100000--0 -> 4'1101 16'1101100000000000 transition: 4'0000 25'-------1-------1-00000--0 -> 4'0110 16'0110100000000000 transition: 4'0000 25'-1-------------1-00000--0 -> 4'0111 16'0111100000000000 transition: 4'0000 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx100000000000 <ignored invalid transition!> transition: 4'0000 25'-----1-----------10000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'----1------------10000--0 -> 4'0001 16'0001100000000000 transition: 4'0000 25'---1-------------10000--0 -> 4'0010 16'0010100000000000 transition: 4'0000 25'1----------------10000--0 -> 4'0011 16'0011100000000000 transition: 4'0000 25'------1----------10000--0 -> 4'0100 16'0100100000000000 transition: 4'0000 25'--1-------------010000--0 -> 4'0101 16'0101100000000000 transition: 4'0000 25'--1-------------110000--0 -> 4'1101 16'1101100000000000 transition: 4'0000 25'-------1---------10000--0 -> 4'0110 16'0110100000000000 transition: 4'0000 25'-1---------------10000--0 -> 4'0111 16'0111100000000000 transition: 4'0000 25'------------------1000--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'-------------------100--0 -> 4'1010 16'1010100000000000 transition: 4'0000 25'--------------------10--0 -> 4'0000 16'0000100000000000 transition: 4'0000 25'---------------------1--0 -> 4'1001 16'1001100000000000 transition: 4'0000 25'------------------------1 -> 4'0000 16'0000100000000000 transition: 4'1000 25'--------0000--00-00000--0 -> 4'1000 16'1000000000000001 transition: 4'1000 25'--------1000-000-00000--0 -> 4'1000 16'1000000000000001 transition: 4'1000 25'--------1000-100-00000--0 -> 4'0000 16'0000000000000001 transition: 4'1000 25'---------100-000-00000--0 -> 4'1000 16'1000000000000001 transition: 4'1000 25'---------100-100-00000--0 -> 4'0000 16'0000000000000001 transition: 4'1000 25'----------10-000-00000--0 -> 4'1000 16'1000000000000001 transition: 4'1000 25'----------10-100-00000--0 -> 4'0000 16'0000000000000001 transition: 4'1000 25'-----------1-000-00000--0 -> 4'1000 16'1000000000000001 transition: 4'1000 25'-----------1-100-00000--0 -> 4'0000 16'0000000000000001 transition: 4'1000 25'------------0010-00000--0 -> 4'1000 16'1000000000000001 transition: 4'1000 25'------------1010-00000--0 -> 4'0000 16'0000000000000001 transition: 4'1000 25'-------------110-00000000 -> 4'1100 16'1100000000000001 transition: 4'1000 25'-------------110-000001-0 -> 4'0010 16'0010000000000001 transition: 4'1000 25'-------------110-00000-10 -> 4'0011 16'0011000000000001 transition: 4'1000 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000000001 <ignored invalid transition!> transition: 4'1000 25'-----1---------1000000--0 -> 4'0000 16'0000000000000001 transition: 4'1000 25'-----1---------1100000--0 -> 4'1000 16'1000000000000001 transition: 4'1000 25'----1----------1-00000--0 -> 4'0001 16'0001000000000001 transition: 4'1000 25'---1-----------1-00000--0 -> 4'0010 16'0010000000000001 transition: 4'1000 25'1--------------1-00000--0 -> 4'0011 16'0011000000000001 transition: 4'1000 25'------1--------1-00000--0 -> 4'0100 16'0100000000000001 transition: 4'1000 25'--1------------1000000--0 -> 4'0101 16'0101000000000001 transition: 4'1000 25'--1------------1100000--0 -> 4'1101 16'1101000000000001 transition: 4'1000 25'-------1-------1-00000--0 -> 4'0110 16'0110000000000001 transition: 4'1000 25'-1-------------1-00000--0 -> 4'0111 16'0111000000000001 transition: 4'1000 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000000001 <ignored invalid transition!> transition: 4'1000 25'-----1-----------10000--0 -> 4'0000 16'0000000000000001 transition: 4'1000 25'----1------------10000--0 -> 4'0001 16'0001000000000001 transition: 4'1000 25'---1-------------10000--0 -> 4'0010 16'0010000000000001 transition: 4'1000 25'1----------------10000--0 -> 4'0011 16'0011000000000001 transition: 4'1000 25'------1----------10000--0 -> 4'0100 16'0100000000000001 transition: 4'1000 25'--1-------------010000--0 -> 4'0101 16'0101000000000001 transition: 4'1000 25'--1-------------110000--0 -> 4'1101 16'1101000000000001 transition: 4'1000 25'-------1---------10000--0 -> 4'0110 16'0110000000000001 transition: 4'1000 25'-1---------------10000--0 -> 4'0111 16'0111000000000001 transition: 4'1000 25'------------------1000--0 -> 4'0000 16'0000000000000001 transition: 4'1000 25'-------------------100--0 -> 4'1010 16'1010000000000001 transition: 4'1000 25'--------------------10--0 -> 4'1000 16'1000000000000001 transition: 4'1000 25'---------------------1--0 -> 4'1001 16'1001000000000001 transition: 4'1000 25'------------------------1 -> 4'1000 16'1000000000000001 transition: 4'0100 25'--------0000--00-00000--0 -> 4'0100 16'0100000010000000 transition: 4'0100 25'--------1000-000-00000--0 -> 4'0100 16'0100000010000000 transition: 4'0100 25'--------1000-100-00000--0 -> 4'0000 16'0000000010000000 transition: 4'0100 25'---------100-000-00000--0 -> 4'0100 16'0100000010000000 transition: 4'0100 25'---------100-100-00000--0 -> 4'0000 16'0000000010000000 transition: 4'0100 25'----------10-000-00000--0 -> 4'0100 16'0100000010000000 transition: 4'0100 25'----------10-100-00000--0 -> 4'0000 16'0000000010000000 transition: 4'0100 25'-----------1-000-00000--0 -> 4'0100 16'0100000010000000 transition: 4'0100 25'-----------1-100-00000--0 -> 4'0000 16'0000000010000000 transition: 4'0100 25'------------0010-00000--0 -> 4'0100 16'0100000010000000 transition: 4'0100 25'------------1010-00000--0 -> 4'0000 16'0000000010000000 transition: 4'0100 25'-------------110-00000000 -> 4'1100 16'1100000010000000 transition: 4'0100 25'-------------110-000001-0 -> 4'0010 16'0010000010000000 transition: 4'0100 25'-------------110-00000-10 -> 4'0011 16'0011000010000000 transition: 4'0100 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000010000000 <ignored invalid transition!> transition: 4'0100 25'-----1---------1000000--0 -> 4'0000 16'0000000010000000 transition: 4'0100 25'-----1---------1100000--0 -> 4'1000 16'1000000010000000 transition: 4'0100 25'----1----------1-00000--0 -> 4'0001 16'0001000010000000 transition: 4'0100 25'---1-----------1-00000--0 -> 4'0010 16'0010000010000000 transition: 4'0100 25'1--------------1-00000--0 -> 4'0011 16'0011000010000000 transition: 4'0100 25'------1--------1-00000--0 -> 4'0100 16'0100000010000000 transition: 4'0100 25'--1------------1000000--0 -> 4'0101 16'0101000010000000 transition: 4'0100 25'--1------------1100000--0 -> 4'1101 16'1101000010000000 transition: 4'0100 25'-------1-------1-00000--0 -> 4'0110 16'0110000010000000 transition: 4'0100 25'-1-------------1-00000--0 -> 4'0111 16'0111000010000000 transition: 4'0100 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000010000000 <ignored invalid transition!> transition: 4'0100 25'-----1-----------10000--0 -> 4'0000 16'0000000010000000 transition: 4'0100 25'----1------------10000--0 -> 4'0001 16'0001000010000000 transition: 4'0100 25'---1-------------10000--0 -> 4'0010 16'0010000010000000 transition: 4'0100 25'1----------------10000--0 -> 4'0011 16'0011000010000000 transition: 4'0100 25'------1----------10000--0 -> 4'0100 16'0100000010000000 transition: 4'0100 25'--1-------------010000--0 -> 4'0101 16'0101000010000000 transition: 4'0100 25'--1-------------110000--0 -> 4'1101 16'1101000010000000 transition: 4'0100 25'-------1---------10000--0 -> 4'0110 16'0110000010000000 transition: 4'0100 25'-1---------------10000--0 -> 4'0111 16'0111000010000000 transition: 4'0100 25'------------------1000--0 -> 4'0000 16'0000000010000000 transition: 4'0100 25'-------------------100--0 -> 4'1010 16'1010000010000000 transition: 4'0100 25'--------------------10--0 -> 4'0100 16'0100000010000000 transition: 4'0100 25'---------------------1--0 -> 4'1001 16'1001000010000000 transition: 4'0100 25'------------------------1 -> 4'0100 16'0100000010000000 transition: 4'1100 25'--------0000--00-00000--0 -> 4'1100 16'1100000000001000 transition: 4'1100 25'--------1000-000-00000--0 -> 4'1100 16'1100000000001000 transition: 4'1100 25'--------1000-100-00000--0 -> 4'0000 16'0000000000001000 transition: 4'1100 25'---------100-000-00000--0 -> 4'1100 16'1100000000001000 transition: 4'1100 25'---------100-100-00000--0 -> 4'0000 16'0000000000001000 transition: 4'1100 25'----------10-000-00000--0 -> 4'1100 16'1100000000001000 transition: 4'1100 25'----------10-100-00000--0 -> 4'0000 16'0000000000001000 transition: 4'1100 25'-----------1-000-00000--0 -> 4'1100 16'1100000000001000 transition: 4'1100 25'-----------1-100-00000--0 -> 4'0000 16'0000000000001000 transition: 4'1100 25'------------0010-00000--0 -> 4'1100 16'1100000000001000 transition: 4'1100 25'------------1010-00000--0 -> 4'0000 16'0000000000001000 transition: 4'1100 25'-------------110-00000000 -> 4'1100 16'1100000000001000 transition: 4'1100 25'-------------110-000001-0 -> 4'0010 16'0010000000001000 transition: 4'1100 25'-------------110-00000-10 -> 4'0011 16'0011000000001000 transition: 4'1100 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000001000 <ignored invalid transition!> transition: 4'1100 25'-----1---------1000000--0 -> 4'0000 16'0000000000001000 transition: 4'1100 25'-----1---------1100000--0 -> 4'1000 16'1000000000001000 transition: 4'1100 25'----1----------1-00000--0 -> 4'0001 16'0001000000001000 transition: 4'1100 25'---1-----------1-00000--0 -> 4'0010 16'0010000000001000 transition: 4'1100 25'1--------------1-00000--0 -> 4'0011 16'0011000000001000 transition: 4'1100 25'------1--------1-00000--0 -> 4'0100 16'0100000000001000 transition: 4'1100 25'--1------------1000000--0 -> 4'0101 16'0101000000001000 transition: 4'1100 25'--1------------1100000--0 -> 4'1101 16'1101000000001000 transition: 4'1100 25'-------1-------1-00000--0 -> 4'0110 16'0110000000001000 transition: 4'1100 25'-1-------------1-00000--0 -> 4'0111 16'0111000000001000 transition: 4'1100 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000001000 <ignored invalid transition!> transition: 4'1100 25'-----1-----------10000--0 -> 4'0000 16'0000000000001000 transition: 4'1100 25'----1------------10000--0 -> 4'0001 16'0001000000001000 transition: 4'1100 25'---1-------------10000--0 -> 4'0010 16'0010000000001000 transition: 4'1100 25'1----------------10000--0 -> 4'0011 16'0011000000001000 transition: 4'1100 25'------1----------10000--0 -> 4'0100 16'0100000000001000 transition: 4'1100 25'--1-------------010000--0 -> 4'0101 16'0101000000001000 transition: 4'1100 25'--1-------------110000--0 -> 4'1101 16'1101000000001000 transition: 4'1100 25'-------1---------10000--0 -> 4'0110 16'0110000000001000 transition: 4'1100 25'-1---------------10000--0 -> 4'0111 16'0111000000001000 transition: 4'1100 25'------------------1000--0 -> 4'0000 16'0000000000001000 transition: 4'1100 25'-------------------100--0 -> 4'1010 16'1010000000001000 transition: 4'1100 25'--------------------10--0 -> 4'1100 16'1100000000001000 transition: 4'1100 25'---------------------1--0 -> 4'1001 16'1001000000001000 transition: 4'1100 25'------------------------1 -> 4'1100 16'1100000000001000 transition: 4'0010 25'--------0000--00-00000--0 -> 4'0010 16'0010001000000000 transition: 4'0010 25'--------1000-000-00000--0 -> 4'0010 16'0010001000000000 transition: 4'0010 25'--------1000-100-00000--0 -> 4'0000 16'0000001000000000 transition: 4'0010 25'---------100-000-00000--0 -> 4'0010 16'0010001000000000 transition: 4'0010 25'---------100-100-00000--0 -> 4'0000 16'0000001000000000 transition: 4'0010 25'----------10-000-00000--0 -> 4'0010 16'0010001000000000 transition: 4'0010 25'----------10-100-00000--0 -> 4'0000 16'0000001000000000 transition: 4'0010 25'-----------1-000-00000--0 -> 4'0010 16'0010001000000000 transition: 4'0010 25'-----------1-100-00000--0 -> 4'0000 16'0000001000000000 transition: 4'0010 25'------------0010-00000--0 -> 4'0010 16'0010001000000000 transition: 4'0010 25'------------1010-00000--0 -> 4'0000 16'0000001000000000 transition: 4'0010 25'-------------110-00000000 -> 4'1100 16'1100001000000000 transition: 4'0010 25'-------------110-000001-0 -> 4'0010 16'0010001000000000 transition: 4'0010 25'-------------110-00000-10 -> 4'0011 16'0011001000000000 transition: 4'0010 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx001000000000 <ignored invalid transition!> transition: 4'0010 25'-----1---------1000000--0 -> 4'0000 16'0000001000000000 transition: 4'0010 25'-----1---------1100000--0 -> 4'1000 16'1000001000000000 transition: 4'0010 25'----1----------1-00000--0 -> 4'0001 16'0001001000000000 transition: 4'0010 25'---1-----------1-00000--0 -> 4'0010 16'0010001000000000 transition: 4'0010 25'1--------------1-00000--0 -> 4'0011 16'0011001000000000 transition: 4'0010 25'------1--------1-00000--0 -> 4'0100 16'0100001000000000 transition: 4'0010 25'--1------------1000000--0 -> 4'0101 16'0101001000000000 transition: 4'0010 25'--1------------1100000--0 -> 4'1101 16'1101001000000000 transition: 4'0010 25'-------1-------1-00000--0 -> 4'0110 16'0110001000000000 transition: 4'0010 25'-1-------------1-00000--0 -> 4'0111 16'0111001000000000 transition: 4'0010 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx001000000000 <ignored invalid transition!> transition: 4'0010 25'-----1-----------10000--0 -> 4'0000 16'0000001000000000 transition: 4'0010 25'----1------------10000--0 -> 4'0001 16'0001001000000000 transition: 4'0010 25'---1-------------10000--0 -> 4'0010 16'0010001000000000 transition: 4'0010 25'1----------------10000--0 -> 4'0011 16'0011001000000000 transition: 4'0010 25'------1----------10000--0 -> 4'0100 16'0100001000000000 transition: 4'0010 25'--1-------------010000--0 -> 4'0101 16'0101001000000000 transition: 4'0010 25'--1-------------110000--0 -> 4'1101 16'1101001000000000 transition: 4'0010 25'-------1---------10000--0 -> 4'0110 16'0110001000000000 transition: 4'0010 25'-1---------------10000--0 -> 4'0111 16'0111001000000000 transition: 4'0010 25'------------------1000--0 -> 4'0000 16'0000001000000000 transition: 4'0010 25'-------------------100--0 -> 4'1010 16'1010001000000000 transition: 4'0010 25'--------------------10--0 -> 4'0010 16'0010001000000000 transition: 4'0010 25'---------------------1--0 -> 4'1001 16'1001001000000000 transition: 4'0010 25'------------------------1 -> 4'0010 16'0010001000000000 transition: 4'1010 25'--------0000--00-00000--0 -> 4'1010 16'1010000000000100 transition: 4'1010 25'--------1000-000-00000--0 -> 4'1010 16'1010000000000100 transition: 4'1010 25'--------1000-100-00000--0 -> 4'0000 16'0000000000000100 transition: 4'1010 25'---------100-000-00000--0 -> 4'1010 16'1010000000000100 transition: 4'1010 25'---------100-100-00000--0 -> 4'0000 16'0000000000000100 transition: 4'1010 25'----------10-000-00000--0 -> 4'1010 16'1010000000000100 transition: 4'1010 25'----------10-100-00000--0 -> 4'0000 16'0000000000000100 transition: 4'1010 25'-----------1-000-00000--0 -> 4'1010 16'1010000000000100 transition: 4'1010 25'-----------1-100-00000--0 -> 4'0000 16'0000000000000100 transition: 4'1010 25'------------0010-00000--0 -> 4'1010 16'1010000000000100 transition: 4'1010 25'------------1010-00000--0 -> 4'0000 16'0000000000000100 transition: 4'1010 25'-------------110-00000000 -> 4'1100 16'1100000000000100 transition: 4'1010 25'-------------110-000001-0 -> 4'0010 16'0010000000000100 transition: 4'1010 25'-------------110-00000-10 -> 4'0011 16'0011000000000100 transition: 4'1010 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000000100 <ignored invalid transition!> transition: 4'1010 25'-----1---------1000000--0 -> 4'0000 16'0000000000000100 transition: 4'1010 25'-----1---------1100000--0 -> 4'1000 16'1000000000000100 transition: 4'1010 25'----1----------1-00000--0 -> 4'0001 16'0001000000000100 transition: 4'1010 25'---1-----------1-00000--0 -> 4'0010 16'0010000000000100 transition: 4'1010 25'1--------------1-00000--0 -> 4'0011 16'0011000000000100 transition: 4'1010 25'------1--------1-00000--0 -> 4'0100 16'0100000000000100 transition: 4'1010 25'--1------------1000000--0 -> 4'0101 16'0101000000000100 transition: 4'1010 25'--1------------1100000--0 -> 4'1101 16'1101000000000100 transition: 4'1010 25'-------1-------1-00000--0 -> 4'0110 16'0110000000000100 transition: 4'1010 25'-1-------------1-00000--0 -> 4'0111 16'0111000000000100 transition: 4'1010 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000000100 <ignored invalid transition!> transition: 4'1010 25'-----1-----------10000--0 -> 4'0000 16'0000000000000100 transition: 4'1010 25'----1------------10000--0 -> 4'0001 16'0001000000000100 transition: 4'1010 25'---1-------------10000--0 -> 4'0010 16'0010000000000100 transition: 4'1010 25'1----------------10000--0 -> 4'0011 16'0011000000000100 transition: 4'1010 25'------1----------10000--0 -> 4'0100 16'0100000000000100 transition: 4'1010 25'--1-------------010000--0 -> 4'0101 16'0101000000000100 transition: 4'1010 25'--1-------------110000--0 -> 4'1101 16'1101000000000100 transition: 4'1010 25'-------1---------10000--0 -> 4'0110 16'0110000000000100 transition: 4'1010 25'-1---------------10000--0 -> 4'0111 16'0111000000000100 transition: 4'1010 25'------------------1000--0 -> 4'0000 16'0000000000000100 transition: 4'1010 25'-------------------100--0 -> 4'1010 16'1010000000000100 transition: 4'1010 25'--------------------10--0 -> 4'1010 16'1010000000000100 transition: 4'1010 25'---------------------1--0 -> 4'1001 16'1001000000000100 transition: 4'1010 25'------------------------1 -> 4'1010 16'1010000000000100 transition: 4'0110 25'--------0000--00-00000--0 -> 4'0110 16'0110000000100000 transition: 4'0110 25'--------1000-000-00000--0 -> 4'0110 16'0110000000100000 transition: 4'0110 25'--------1000-100-00000--0 -> 4'0000 16'0000000000100000 transition: 4'0110 25'---------100-000-00000--0 -> 4'0110 16'0110000000100000 transition: 4'0110 25'---------100-100-00000--0 -> 4'0000 16'0000000000100000 transition: 4'0110 25'----------10-000-00000--0 -> 4'0110 16'0110000000100000 transition: 4'0110 25'----------10-100-00000--0 -> 4'0000 16'0000000000100000 transition: 4'0110 25'-----------1-000-00000--0 -> 4'0110 16'0110000000100000 transition: 4'0110 25'-----------1-100-00000--0 -> 4'0000 16'0000000000100000 transition: 4'0110 25'------------0010-00000--0 -> 4'0110 16'0110000000100000 transition: 4'0110 25'------------1010-00000--0 -> 4'0000 16'0000000000100000 transition: 4'0110 25'-------------110-00000000 -> 4'1100 16'1100000000100000 transition: 4'0110 25'-------------110-000001-0 -> 4'0010 16'0010000000100000 transition: 4'0110 25'-------------110-00000-10 -> 4'0011 16'0011000000100000 transition: 4'0110 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000100000 <ignored invalid transition!> transition: 4'0110 25'-----1---------1000000--0 -> 4'0000 16'0000000000100000 transition: 4'0110 25'-----1---------1100000--0 -> 4'1000 16'1000000000100000 transition: 4'0110 25'----1----------1-00000--0 -> 4'0001 16'0001000000100000 transition: 4'0110 25'---1-----------1-00000--0 -> 4'0010 16'0010000000100000 transition: 4'0110 25'1--------------1-00000--0 -> 4'0011 16'0011000000100000 transition: 4'0110 25'------1--------1-00000--0 -> 4'0100 16'0100000000100000 transition: 4'0110 25'--1------------1000000--0 -> 4'0101 16'0101000000100000 transition: 4'0110 25'--1------------1100000--0 -> 4'1101 16'1101000000100000 transition: 4'0110 25'-------1-------1-00000--0 -> 4'0110 16'0110000000100000 transition: 4'0110 25'-1-------------1-00000--0 -> 4'0111 16'0111000000100000 transition: 4'0110 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000100000 <ignored invalid transition!> transition: 4'0110 25'-----1-----------10000--0 -> 4'0000 16'0000000000100000 transition: 4'0110 25'----1------------10000--0 -> 4'0001 16'0001000000100000 transition: 4'0110 25'---1-------------10000--0 -> 4'0010 16'0010000000100000 transition: 4'0110 25'1----------------10000--0 -> 4'0011 16'0011000000100000 transition: 4'0110 25'------1----------10000--0 -> 4'0100 16'0100000000100000 transition: 4'0110 25'--1-------------010000--0 -> 4'0101 16'0101000000100000 transition: 4'0110 25'--1-------------110000--0 -> 4'1101 16'1101000000100000 transition: 4'0110 25'-------1---------10000--0 -> 4'0110 16'0110000000100000 transition: 4'0110 25'-1---------------10000--0 -> 4'0111 16'0111000000100000 transition: 4'0110 25'------------------1000--0 -> 4'0000 16'0000000000100000 transition: 4'0110 25'-------------------100--0 -> 4'1010 16'1010000000100000 transition: 4'0110 25'--------------------10--0 -> 4'0110 16'0110000000100000 transition: 4'0110 25'---------------------1--0 -> 4'1001 16'1001000000100000 transition: 4'0110 25'------------------------1 -> 4'0110 16'0110000000100000 transition: 4'0001 25'--------0000--00-00000--0 -> 4'0001 16'0001010000000000 transition: 4'0001 25'--------1000-000-00000--0 -> 4'0001 16'0001010000000000 transition: 4'0001 25'--------1000-100-00000--0 -> 4'0000 16'0000010000000000 transition: 4'0001 25'---------100-000-00000--0 -> 4'0001 16'0001010000000000 transition: 4'0001 25'---------100-100-00000--0 -> 4'0000 16'0000010000000000 transition: 4'0001 25'----------10-000-00000--0 -> 4'0001 16'0001010000000000 transition: 4'0001 25'----------10-100-00000--0 -> 4'0000 16'0000010000000000 transition: 4'0001 25'-----------1-000-00000--0 -> 4'0001 16'0001010000000000 transition: 4'0001 25'-----------1-100-00000--0 -> 4'0000 16'0000010000000000 transition: 4'0001 25'------------0010-00000--0 -> 4'0001 16'0001010000000000 transition: 4'0001 25'------------1010-00000--0 -> 4'0000 16'0000010000000000 transition: 4'0001 25'-------------110-00000000 -> 4'1100 16'1100010000000000 transition: 4'0001 25'-------------110-000001-0 -> 4'0010 16'0010010000000000 transition: 4'0001 25'-------------110-00000-10 -> 4'0011 16'0011010000000000 transition: 4'0001 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx010000000000 <ignored invalid transition!> transition: 4'0001 25'-----1---------1000000--0 -> 4'0000 16'0000010000000000 transition: 4'0001 25'-----1---------1100000--0 -> 4'1000 16'1000010000000000 transition: 4'0001 25'----1----------1-00000--0 -> 4'0001 16'0001010000000000 transition: 4'0001 25'---1-----------1-00000--0 -> 4'0010 16'0010010000000000 transition: 4'0001 25'1--------------1-00000--0 -> 4'0011 16'0011010000000000 transition: 4'0001 25'------1--------1-00000--0 -> 4'0100 16'0100010000000000 transition: 4'0001 25'--1------------1000000--0 -> 4'0101 16'0101010000000000 transition: 4'0001 25'--1------------1100000--0 -> 4'1101 16'1101010000000000 transition: 4'0001 25'-------1-------1-00000--0 -> 4'0110 16'0110010000000000 transition: 4'0001 25'-1-------------1-00000--0 -> 4'0111 16'0111010000000000 transition: 4'0001 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx010000000000 <ignored invalid transition!> transition: 4'0001 25'-----1-----------10000--0 -> 4'0000 16'0000010000000000 transition: 4'0001 25'----1------------10000--0 -> 4'0001 16'0001010000000000 transition: 4'0001 25'---1-------------10000--0 -> 4'0010 16'0010010000000000 transition: 4'0001 25'1----------------10000--0 -> 4'0011 16'0011010000000000 transition: 4'0001 25'------1----------10000--0 -> 4'0100 16'0100010000000000 transition: 4'0001 25'--1-------------010000--0 -> 4'0101 16'0101010000000000 transition: 4'0001 25'--1-------------110000--0 -> 4'1101 16'1101010000000000 transition: 4'0001 25'-------1---------10000--0 -> 4'0110 16'0110010000000000 transition: 4'0001 25'-1---------------10000--0 -> 4'0111 16'0111010000000000 transition: 4'0001 25'------------------1000--0 -> 4'0000 16'0000010000000000 transition: 4'0001 25'-------------------100--0 -> 4'1010 16'1010010000000000 transition: 4'0001 25'--------------------10--0 -> 4'0001 16'0001010000000000 transition: 4'0001 25'---------------------1--0 -> 4'1001 16'1001010000000000 transition: 4'0001 25'------------------------1 -> 4'0001 16'0001010000000000 transition: 4'1001 25'--------0000--00-00000--0 -> 4'1001 16'1001000000000000 transition: 4'1001 25'--------1000-000-00000--0 -> 4'1001 16'1001000000000000 transition: 4'1001 25'--------1000-100-00000--0 -> 4'0000 16'0000000000000000 transition: 4'1001 25'---------100-000-00000--0 -> 4'1001 16'1001000000000000 transition: 4'1001 25'---------100-100-00000--0 -> 4'0000 16'0000000000000000 transition: 4'1001 25'----------10-000-00000--0 -> 4'1001 16'1001000000000000 transition: 4'1001 25'----------10-100-00000--0 -> 4'0000 16'0000000000000000 transition: 4'1001 25'-----------1-000-00000--0 -> 4'1001 16'1001000000000000 transition: 4'1001 25'-----------1-100-00000--0 -> 4'0000 16'0000000000000000 transition: 4'1001 25'------------0010-00000--0 -> 4'1001 16'1001000000000000 transition: 4'1001 25'------------1010-00000--0 -> 4'0000 16'0000000000000000 transition: 4'1001 25'-------------110-00000000 -> 4'1100 16'1100000000000000 transition: 4'1001 25'-------------110-000001-0 -> 4'0010 16'0010000000000000 transition: 4'1001 25'-------------110-00000-10 -> 4'0011 16'0011000000000000 transition: 4'1001 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000000000 <ignored invalid transition!> transition: 4'1001 25'-----1---------1000000--0 -> 4'0000 16'0000000000000000 transition: 4'1001 25'-----1---------1100000--0 -> 4'1000 16'1000000000000000 transition: 4'1001 25'----1----------1-00000--0 -> 4'0001 16'0001000000000000 transition: 4'1001 25'---1-----------1-00000--0 -> 4'0010 16'0010000000000000 transition: 4'1001 25'1--------------1-00000--0 -> 4'0011 16'0011000000000000 transition: 4'1001 25'------1--------1-00000--0 -> 4'0100 16'0100000000000000 transition: 4'1001 25'--1------------1000000--0 -> 4'0101 16'0101000000000000 transition: 4'1001 25'--1------------1100000--0 -> 4'1101 16'1101000000000000 transition: 4'1001 25'-------1-------1-00000--0 -> 4'0110 16'0110000000000000 transition: 4'1001 25'-1-------------1-00000--0 -> 4'0111 16'0111000000000000 transition: 4'1001 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000000000 <ignored invalid transition!> transition: 4'1001 25'-----1-----------10000--0 -> 4'0000 16'0000000000000000 transition: 4'1001 25'----1------------10000--0 -> 4'0001 16'0001000000000000 transition: 4'1001 25'---1-------------10000--0 -> 4'0010 16'0010000000000000 transition: 4'1001 25'1----------------10000--0 -> 4'0011 16'0011000000000000 transition: 4'1001 25'------1----------10000--0 -> 4'0100 16'0100000000000000 transition: 4'1001 25'--1-------------010000--0 -> 4'0101 16'0101000000000000 transition: 4'1001 25'--1-------------110000--0 -> 4'1101 16'1101000000000000 transition: 4'1001 25'-------1---------10000--0 -> 4'0110 16'0110000000000000 transition: 4'1001 25'-1---------------10000--0 -> 4'0111 16'0111000000000000 transition: 4'1001 25'------------------1000--0 -> 4'0000 16'0000000000000000 transition: 4'1001 25'-------------------100--0 -> 4'1010 16'1010000000000000 transition: 4'1001 25'--------------------10--0 -> 4'1001 16'1001000000000000 transition: 4'1001 25'---------------------1--0 -> 4'1001 16'1001000000000000 transition: 4'1001 25'------------------------1 -> 4'1001 16'1001000000000000 transition: 4'0101 25'--------0000--00-00000--0 -> 4'0101 16'0101000001000000 transition: 4'0101 25'--------1000-000-00000--0 -> 4'0101 16'0101000001000000 transition: 4'0101 25'--------1000-100-00000--0 -> 4'0000 16'0000000001000000 transition: 4'0101 25'---------100-000-00000--0 -> 4'0101 16'0101000001000000 transition: 4'0101 25'---------100-100-00000--0 -> 4'0000 16'0000000001000000 transition: 4'0101 25'----------10-000-00000--0 -> 4'0101 16'0101000001000000 transition: 4'0101 25'----------10-100-00000--0 -> 4'0000 16'0000000001000000 transition: 4'0101 25'-----------1-000-00000--0 -> 4'0101 16'0101000001000000 transition: 4'0101 25'-----------1-100-00000--0 -> 4'0000 16'0000000001000000 transition: 4'0101 25'------------0010-00000--0 -> 4'0101 16'0101000001000000 transition: 4'0101 25'------------1010-00000--0 -> 4'0000 16'0000000001000000 transition: 4'0101 25'-------------110-00000000 -> 4'1100 16'1100000001000000 transition: 4'0101 25'-------------110-000001-0 -> 4'0010 16'0010000001000000 transition: 4'0101 25'-------------110-00000-10 -> 4'0011 16'0011000001000000 transition: 4'0101 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000001000000 <ignored invalid transition!> transition: 4'0101 25'-----1---------1000000--0 -> 4'0000 16'0000000001000000 transition: 4'0101 25'-----1---------1100000--0 -> 4'1000 16'1000000001000000 transition: 4'0101 25'----1----------1-00000--0 -> 4'0001 16'0001000001000000 transition: 4'0101 25'---1-----------1-00000--0 -> 4'0010 16'0010000001000000 transition: 4'0101 25'1--------------1-00000--0 -> 4'0011 16'0011000001000000 transition: 4'0101 25'------1--------1-00000--0 -> 4'0100 16'0100000001000000 transition: 4'0101 25'--1------------1000000--0 -> 4'0101 16'0101000001000000 transition: 4'0101 25'--1------------1100000--0 -> 4'1101 16'1101000001000000 transition: 4'0101 25'-------1-------1-00000--0 -> 4'0110 16'0110000001000000 transition: 4'0101 25'-1-------------1-00000--0 -> 4'0111 16'0111000001000000 transition: 4'0101 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000001000000 <ignored invalid transition!> transition: 4'0101 25'-----1-----------10000--0 -> 4'0000 16'0000000001000000 transition: 4'0101 25'----1------------10000--0 -> 4'0001 16'0001000001000000 transition: 4'0101 25'---1-------------10000--0 -> 4'0010 16'0010000001000000 transition: 4'0101 25'1----------------10000--0 -> 4'0011 16'0011000001000000 transition: 4'0101 25'------1----------10000--0 -> 4'0100 16'0100000001000000 transition: 4'0101 25'--1-------------010000--0 -> 4'0101 16'0101000001000000 transition: 4'0101 25'--1-------------110000--0 -> 4'1101 16'1101000001000000 transition: 4'0101 25'-------1---------10000--0 -> 4'0110 16'0110000001000000 transition: 4'0101 25'-1---------------10000--0 -> 4'0111 16'0111000001000000 transition: 4'0101 25'------------------1000--0 -> 4'0000 16'0000000001000000 transition: 4'0101 25'-------------------100--0 -> 4'1010 16'1010000001000000 transition: 4'0101 25'--------------------10--0 -> 4'0101 16'0101000001000000 transition: 4'0101 25'---------------------1--0 -> 4'1001 16'1001000001000000 transition: 4'0101 25'------------------------1 -> 4'0101 16'0101000001000000 transition: 4'1101 25'--------0000--00-00000--0 -> 4'1101 16'1101000000000010 transition: 4'1101 25'--------1000-000-00000--0 -> 4'1101 16'1101000000000010 transition: 4'1101 25'--------1000-100-00000--0 -> 4'0000 16'0000000000000010 transition: 4'1101 25'---------100-000-00000--0 -> 4'1101 16'1101000000000010 transition: 4'1101 25'---------100-100-00000--0 -> 4'0000 16'0000000000000010 transition: 4'1101 25'----------10-000-00000--0 -> 4'1101 16'1101000000000010 transition: 4'1101 25'----------10-100-00000--0 -> 4'0000 16'0000000000000010 transition: 4'1101 25'-----------1-000-00000--0 -> 4'1101 16'1101000000000010 transition: 4'1101 25'-----------1-100-00000--0 -> 4'0000 16'0000000000000010 transition: 4'1101 25'------------0010-00000--0 -> 4'1101 16'1101000000000010 transition: 4'1101 25'------------1010-00000--0 -> 4'0000 16'0000000000000010 transition: 4'1101 25'-------------110-00000000 -> 4'1100 16'1100000000000010 transition: 4'1101 25'-------------110-000001-0 -> 4'0010 16'0010000000000010 transition: 4'1101 25'-------------110-00000-10 -> 4'0011 16'0011000000000010 transition: 4'1101 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000000010 <ignored invalid transition!> transition: 4'1101 25'-----1---------1000000--0 -> 4'0000 16'0000000000000010 transition: 4'1101 25'-----1---------1100000--0 -> 4'1000 16'1000000000000010 transition: 4'1101 25'----1----------1-00000--0 -> 4'0001 16'0001000000000010 transition: 4'1101 25'---1-----------1-00000--0 -> 4'0010 16'0010000000000010 transition: 4'1101 25'1--------------1-00000--0 -> 4'0011 16'0011000000000010 transition: 4'1101 25'------1--------1-00000--0 -> 4'0100 16'0100000000000010 transition: 4'1101 25'--1------------1000000--0 -> 4'0101 16'0101000000000010 transition: 4'1101 25'--1------------1100000--0 -> 4'1101 16'1101000000000010 transition: 4'1101 25'-------1-------1-00000--0 -> 4'0110 16'0110000000000010 transition: 4'1101 25'-1-------------1-00000--0 -> 4'0111 16'0111000000000010 transition: 4'1101 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000000010 <ignored invalid transition!> transition: 4'1101 25'-----1-----------10000--0 -> 4'0000 16'0000000000000010 transition: 4'1101 25'----1------------10000--0 -> 4'0001 16'0001000000000010 transition: 4'1101 25'---1-------------10000--0 -> 4'0010 16'0010000000000010 transition: 4'1101 25'1----------------10000--0 -> 4'0011 16'0011000000000010 transition: 4'1101 25'------1----------10000--0 -> 4'0100 16'0100000000000010 transition: 4'1101 25'--1-------------010000--0 -> 4'0101 16'0101000000000010 transition: 4'1101 25'--1-------------110000--0 -> 4'1101 16'1101000000000010 transition: 4'1101 25'-------1---------10000--0 -> 4'0110 16'0110000000000010 transition: 4'1101 25'-1---------------10000--0 -> 4'0111 16'0111000000000010 transition: 4'1101 25'------------------1000--0 -> 4'0000 16'0000000000000010 transition: 4'1101 25'-------------------100--0 -> 4'1010 16'1010000000000010 transition: 4'1101 25'--------------------10--0 -> 4'1101 16'1101000000000010 transition: 4'1101 25'---------------------1--0 -> 4'1001 16'1001000000000010 transition: 4'1101 25'------------------------1 -> 4'1101 16'1101000000000010 transition: 4'0011 25'--------0000--00-00000--0 -> 4'0011 16'0011000100000000 transition: 4'0011 25'--------1000-000-00000--0 -> 4'0011 16'0011000100000000 transition: 4'0011 25'--------1000-100-00000--0 -> 4'0000 16'0000000100000000 transition: 4'0011 25'---------100-000-00000--0 -> 4'0011 16'0011000100000000 transition: 4'0011 25'---------100-100-00000--0 -> 4'0000 16'0000000100000000 transition: 4'0011 25'----------10-000-00000--0 -> 4'0011 16'0011000100000000 transition: 4'0011 25'----------10-100-00000--0 -> 4'0000 16'0000000100000000 transition: 4'0011 25'-----------1-000-00000--0 -> 4'0011 16'0011000100000000 transition: 4'0011 25'-----------1-100-00000--0 -> 4'0000 16'0000000100000000 transition: 4'0011 25'------------0010-00000--0 -> 4'0011 16'0011000100000000 transition: 4'0011 25'------------1010-00000--0 -> 4'0000 16'0000000100000000 transition: 4'0011 25'-------------110-00000000 -> 4'1100 16'1100000100000000 transition: 4'0011 25'-------------110-000001-0 -> 4'0010 16'0010000100000000 transition: 4'0011 25'-------------110-00000-10 -> 4'0011 16'0011000100000000 transition: 4'0011 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000100000000 <ignored invalid transition!> transition: 4'0011 25'-----1---------1000000--0 -> 4'0000 16'0000000100000000 transition: 4'0011 25'-----1---------1100000--0 -> 4'1000 16'1000000100000000 transition: 4'0011 25'----1----------1-00000--0 -> 4'0001 16'0001000100000000 transition: 4'0011 25'---1-----------1-00000--0 -> 4'0010 16'0010000100000000 transition: 4'0011 25'1--------------1-00000--0 -> 4'0011 16'0011000100000000 transition: 4'0011 25'------1--------1-00000--0 -> 4'0100 16'0100000100000000 transition: 4'0011 25'--1------------1000000--0 -> 4'0101 16'0101000100000000 transition: 4'0011 25'--1------------1100000--0 -> 4'1101 16'1101000100000000 transition: 4'0011 25'-------1-------1-00000--0 -> 4'0110 16'0110000100000000 transition: 4'0011 25'-1-------------1-00000--0 -> 4'0111 16'0111000100000000 transition: 4'0011 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000100000000 <ignored invalid transition!> transition: 4'0011 25'-----1-----------10000--0 -> 4'0000 16'0000000100000000 transition: 4'0011 25'----1------------10000--0 -> 4'0001 16'0001000100000000 transition: 4'0011 25'---1-------------10000--0 -> 4'0010 16'0010000100000000 transition: 4'0011 25'1----------------10000--0 -> 4'0011 16'0011000100000000 transition: 4'0011 25'------1----------10000--0 -> 4'0100 16'0100000100000000 transition: 4'0011 25'--1-------------010000--0 -> 4'0101 16'0101000100000000 transition: 4'0011 25'--1-------------110000--0 -> 4'1101 16'1101000100000000 transition: 4'0011 25'-------1---------10000--0 -> 4'0110 16'0110000100000000 transition: 4'0011 25'-1---------------10000--0 -> 4'0111 16'0111000100000000 transition: 4'0011 25'------------------1000--0 -> 4'0000 16'0000000100000000 transition: 4'0011 25'-------------------100--0 -> 4'1010 16'1010000100000000 transition: 4'0011 25'--------------------10--0 -> 4'0011 16'0011000100000000 transition: 4'0011 25'---------------------1--0 -> 4'1001 16'1001000100000000 transition: 4'0011 25'------------------------1 -> 4'0011 16'0011000100000000 transition: 4'0111 25'--------0000--00-00000--0 -> 4'0111 16'0111000000010000 transition: 4'0111 25'--------1000-000-00000--0 -> 4'0111 16'0111000000010000 transition: 4'0111 25'--------1000-100-00000--0 -> 4'0000 16'0000000000010000 transition: 4'0111 25'---------100-000-00000--0 -> 4'0111 16'0111000000010000 transition: 4'0111 25'---------100-100-00000--0 -> 4'0000 16'0000000000010000 transition: 4'0111 25'----------10-000-00000--0 -> 4'0111 16'0111000000010000 transition: 4'0111 25'----------10-100-00000--0 -> 4'0000 16'0000000000010000 transition: 4'0111 25'-----------1-000-00000--0 -> 4'0111 16'0111000000010000 transition: 4'0111 25'-----------1-100-00000--0 -> 4'0000 16'0000000000010000 transition: 4'0111 25'------------0010-00000--0 -> 4'0111 16'0111000000010000 transition: 4'0111 25'------------1010-00000--0 -> 4'0000 16'0000000000010000 transition: 4'0111 25'-------------110-00000000 -> 4'1100 16'1100000000010000 transition: 4'0111 25'-------------110-000001-0 -> 4'0010 16'0010000000010000 transition: 4'0111 25'-------------110-00000-10 -> 4'0011 16'0011000000010000 transition: 4'0111 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000010000 <ignored invalid transition!> transition: 4'0111 25'-----1---------1000000--0 -> 4'0000 16'0000000000010000 transition: 4'0111 25'-----1---------1100000--0 -> 4'1000 16'1000000000010000 transition: 4'0111 25'----1----------1-00000--0 -> 4'0001 16'0001000000010000 transition: 4'0111 25'---1-----------1-00000--0 -> 4'0010 16'0010000000010000 transition: 4'0111 25'1--------------1-00000--0 -> 4'0011 16'0011000000010000 transition: 4'0111 25'------1--------1-00000--0 -> 4'0100 16'0100000000010000 transition: 4'0111 25'--1------------1000000--0 -> 4'0101 16'0101000000010000 transition: 4'0111 25'--1------------1100000--0 -> 4'1101 16'1101000000010000 transition: 4'0111 25'-------1-------1-00000--0 -> 4'0110 16'0110000000010000 transition: 4'0111 25'-1-------------1-00000--0 -> 4'0111 16'0111000000010000 transition: 4'0111 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000010000 <ignored invalid transition!> transition: 4'0111 25'-----1-----------10000--0 -> 4'0000 16'0000000000010000 transition: 4'0111 25'----1------------10000--0 -> 4'0001 16'0001000000010000 transition: 4'0111 25'---1-------------10000--0 -> 4'0010 16'0010000000010000 transition: 4'0111 25'1----------------10000--0 -> 4'0011 16'0011000000010000 transition: 4'0111 25'------1----------10000--0 -> 4'0100 16'0100000000010000 transition: 4'0111 25'--1-------------010000--0 -> 4'0101 16'0101000000010000 transition: 4'0111 25'--1-------------110000--0 -> 4'1101 16'1101000000010000 transition: 4'0111 25'-------1---------10000--0 -> 4'0110 16'0110000000010000 transition: 4'0111 25'-1---------------10000--0 -> 4'0111 16'0111000000010000 transition: 4'0111 25'------------------1000--0 -> 4'0000 16'0000000000010000 transition: 4'0111 25'-------------------100--0 -> 4'1010 16'1010000000010000 transition: 4'0111 25'--------------------10--0 -> 4'0111 16'0111000000010000 transition: 4'0111 25'---------------------1--0 -> 4'1001 16'1001000000010000 transition: 4'0111 25'------------------------1 -> 4'0111 16'0111000000010000 Extracting FSM `\Riscado_V.ctrlUnit.aluSrcA' from module `\processorci_top'. found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3576 root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\aluSrcA[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y found state code: 2'00 found state code: 2'10 found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:123$190_Y found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:122$189_Y found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:121$188_Y ctrl inputs: { $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:121$188_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:122$189_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:123$190_Y $flatten\Riscado_V.\ctrlUnit.$0\aluSrcA[1:0] } transition: 2'00 14'0000--00000000 -> 2'00 5'10000 transition: 2'00 14'1000-000000000 -> 2'00 5'10000 transition: 2'00 14'1000-100000000 -> 2'00 5'10000 transition: 2'00 14'-100-000000000 -> 2'00 5'10000 transition: 2'00 14'-100-100000000 -> 2'00 5'10000 transition: 2'00 14'--10-000000000 -> 2'00 5'10000 transition: 2'00 14'--10-100000000 -> 2'00 5'10000 transition: 2'00 14'---1-000000000 -> 2'00 5'10000 transition: 2'00 14'---1-100000000 -> 2'10 5'10010 transition: 2'00 14'----0010000000 -> 2'00 5'10000 transition: 2'00 14'----1010000000 -> 2'10 5'10010 transition: 2'00 14'-----110000000 -> 2'00 5'10000 transition: 2'00 14'-------1000000 -> 2'00 5'10000 transition: 2'00 14'--------100000 -> 2'00 5'10000 transition: 2'00 14'---------10000 -> 2'10 5'10010 transition: 2'00 14'----------1000 -> 2'00 5'10000 transition: 2'00 14'-----------100 -> 2'00 5'10000 transition: 2'00 14'------------10 -> 2'00 5'10000 transition: 2'00 14'-------------1 -> 2'00 5'10000 transition: 2'10 14'0000--00000000 -> 2'10 5'00110 transition: 2'10 14'1000-000000000 -> 2'10 5'00110 transition: 2'10 14'1000-100000000 -> 2'00 5'00100 transition: 2'10 14'-100-000000000 -> 2'10 5'00110 transition: 2'10 14'-100-100000000 -> 2'00 5'00100 transition: 2'10 14'--10-000000000 -> 2'10 5'00110 transition: 2'10 14'--10-100000000 -> 2'00 5'00100 transition: 2'10 14'---1-000000000 -> 2'10 5'00110 transition: 2'10 14'---1-100000000 -> 2'10 5'00110 transition: 2'10 14'----0010000000 -> 2'10 5'00110 transition: 2'10 14'----1010000000 -> 2'10 5'00110 transition: 2'10 14'-----110000000 -> 2'10 5'00110 transition: 2'10 14'-------1000000 -> 2'10 5'00110 transition: 2'10 14'--------100000 -> 2'10 5'00110 transition: 2'10 14'---------10000 -> 2'10 5'00110 transition: 2'10 14'----------1000 -> 2'10 5'00110 transition: 2'10 14'-----------100 -> 2'10 5'00110 transition: 2'10 14'------------10 -> 2'00 5'00100 transition: 2'10 14'-------------1 -> 2'00 5'00100 Extracting FSM `\Riscado_V.ctrlUnit.aluSrcB' from module `\processorci_top'. found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3577 root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\aluSrcB[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y found state code: 3'010 found state code: 3'001 found state code: 3'101 found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y found state code: 3'011 found state code: 3'000 found state code: 3'100 found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$199_Y found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$198_Y found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$197_Y found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$196_Y found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:129$195_Y found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:128$194_Y ctrl inputs: { $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:128$194_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:129$195_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$196_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$197_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$198_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$199_Y $flatten\Riscado_V.\ctrlUnit.$0\aluSrcB[2:0] } transition: 3'000 14'0000--00000000 -> 3'000 9'100000000 transition: 3'000 14'1000-000000000 -> 3'000 9'100000000 transition: 3'000 14'1000-100000000 -> 3'010 9'100000010 transition: 3'000 14'-100-000000000 -> 3'000 9'100000000 transition: 3'000 14'-100-100000000 -> 3'001 9'100000001 transition: 3'000 14'--10-000000000 -> 3'000 9'100000000 transition: 3'000 14'--10-100000000 -> 3'001 9'100000001 transition: 3'000 14'---1-000000000 -> 3'000 9'100000000 transition: 3'000 14'---1-100000000 -> 3'101 9'100000101 transition: 3'000 14'----0010000000 -> 3'000 9'100000000 transition: 3'000 14'----1010000000 -> 3'011 9'100000011 transition: 3'000 14'-----110000000 -> 3'000 9'100000000 transition: 3'000 14'-------1000000 -> 3'000 9'100000000 transition: 3'000 14'--------100000 -> 3'001 9'100000001 transition: 3'000 14'---------10000 -> 3'100 9'100000100 transition: 3'000 14'----------1000 -> 3'100 9'100000100 transition: 3'000 14'-----------100 -> 3'000 9'100000000 transition: 3'000 14'------------10 -> 3'000 9'100000000 transition: 3'000 14'-------------1 -> 3'000 9'100000000 transition: 3'100 14'0000--00000000 -> 3'100 9'010000100 transition: 3'100 14'1000-000000000 -> 3'100 9'010000100 transition: 3'100 14'1000-100000000 -> 3'010 9'010000010 transition: 3'100 14'-100-000000000 -> 3'100 9'010000100 transition: 3'100 14'-100-100000000 -> 3'001 9'010000001 transition: 3'100 14'--10-000000000 -> 3'100 9'010000100 transition: 3'100 14'--10-100000000 -> 3'001 9'010000001 transition: 3'100 14'---1-000000000 -> 3'100 9'010000100 transition: 3'100 14'---1-100000000 -> 3'101 9'010000101 transition: 3'100 14'----0010000000 -> 3'100 9'010000100 transition: 3'100 14'----1010000000 -> 3'011 9'010000011 transition: 3'100 14'-----110000000 -> 3'100 9'010000100 transition: 3'100 14'-------1000000 -> 3'000 9'010000000 transition: 3'100 14'--------100000 -> 3'001 9'010000001 transition: 3'100 14'---------10000 -> 3'100 9'010000100 transition: 3'100 14'----------1000 -> 3'100 9'010000100 transition: 3'100 14'-----------100 -> 3'100 9'010000100 transition: 3'100 14'------------10 -> 3'000 9'010000000 transition: 3'100 14'-------------1 -> 3'000 9'010000000 transition: 3'010 14'0000--00000000 -> 3'010 9'000001010 transition: 3'010 14'1000-000000000 -> 3'010 9'000001010 transition: 3'010 14'1000-100000000 -> 3'010 9'000001010 transition: 3'010 14'-100-000000000 -> 3'010 9'000001010 transition: 3'010 14'-100-100000000 -> 3'001 9'000001001 transition: 3'010 14'--10-000000000 -> 3'010 9'000001010 transition: 3'010 14'--10-100000000 -> 3'001 9'000001001 transition: 3'010 14'---1-000000000 -> 3'010 9'000001010 transition: 3'010 14'---1-100000000 -> 3'101 9'000001101 transition: 3'010 14'----0010000000 -> 3'010 9'000001010 transition: 3'010 14'----1010000000 -> 3'011 9'000001011 transition: 3'010 14'-----110000000 -> 3'010 9'000001010 transition: 3'010 14'-------1000000 -> 3'000 9'000001000 transition: 3'010 14'--------100000 -> 3'001 9'000001001 transition: 3'010 14'---------10000 -> 3'100 9'000001100 transition: 3'010 14'----------1000 -> 3'100 9'000001100 transition: 3'010 14'-----------100 -> 3'010 9'000001010 transition: 3'010 14'------------10 -> 3'000 9'000001000 transition: 3'010 14'-------------1 -> 3'000 9'000001000 transition: 3'001 14'0000--00000000 -> 3'001 9'001000001 transition: 3'001 14'1000-000000000 -> 3'001 9'001000001 transition: 3'001 14'1000-100000000 -> 3'010 9'001000010 transition: 3'001 14'-100-000000000 -> 3'001 9'001000001 transition: 3'001 14'-100-100000000 -> 3'001 9'001000001 transition: 3'001 14'--10-000000000 -> 3'001 9'001000001 transition: 3'001 14'--10-100000000 -> 3'001 9'001000001 transition: 3'001 14'---1-000000000 -> 3'001 9'001000001 transition: 3'001 14'---1-100000000 -> 3'101 9'001000101 transition: 3'001 14'----0010000000 -> 3'001 9'001000001 transition: 3'001 14'----1010000000 -> 3'011 9'001000011 transition: 3'001 14'-----110000000 -> 3'001 9'001000001 transition: 3'001 14'-------1000000 -> 3'000 9'001000000 transition: 3'001 14'--------100000 -> 3'001 9'001000001 transition: 3'001 14'---------10000 -> 3'100 9'001000100 transition: 3'001 14'----------1000 -> 3'100 9'001000100 transition: 3'001 14'-----------100 -> 3'001 9'001000001 transition: 3'001 14'------------10 -> 3'000 9'001000000 transition: 3'001 14'-------------1 -> 3'000 9'001000000 transition: 3'101 14'0000--00000000 -> 3'101 9'000010101 transition: 3'101 14'1000-000000000 -> 3'101 9'000010101 transition: 3'101 14'1000-100000000 -> 3'010 9'000010010 transition: 3'101 14'-100-000000000 -> 3'101 9'000010101 transition: 3'101 14'-100-100000000 -> 3'001 9'000010001 transition: 3'101 14'--10-000000000 -> 3'101 9'000010101 transition: 3'101 14'--10-100000000 -> 3'001 9'000010001 transition: 3'101 14'---1-000000000 -> 3'101 9'000010101 transition: 3'101 14'---1-100000000 -> 3'101 9'000010101 transition: 3'101 14'----0010000000 -> 3'101 9'000010101 transition: 3'101 14'----1010000000 -> 3'011 9'000010011 transition: 3'101 14'-----110000000 -> 3'101 9'000010101 transition: 3'101 14'-------1000000 -> 3'000 9'000010000 transition: 3'101 14'--------100000 -> 3'001 9'000010001 transition: 3'101 14'---------10000 -> 3'100 9'000010100 transition: 3'101 14'----------1000 -> 3'100 9'000010100 transition: 3'101 14'-----------100 -> 3'101 9'000010101 transition: 3'101 14'------------10 -> 3'000 9'000010000 transition: 3'101 14'-------------1 -> 3'000 9'000010000 transition: 3'011 14'0000--00000000 -> 3'011 9'000100011 transition: 3'011 14'1000-000000000 -> 3'011 9'000100011 transition: 3'011 14'1000-100000000 -> 3'010 9'000100010 transition: 3'011 14'-100-000000000 -> 3'011 9'000100011 transition: 3'011 14'-100-100000000 -> 3'001 9'000100001 transition: 3'011 14'--10-000000000 -> 3'011 9'000100011 transition: 3'011 14'--10-100000000 -> 3'001 9'000100001 transition: 3'011 14'---1-000000000 -> 3'011 9'000100011 transition: 3'011 14'---1-100000000 -> 3'101 9'000100101 transition: 3'011 14'----0010000000 -> 3'011 9'000100011 transition: 3'011 14'----1010000000 -> 3'011 9'000100011 transition: 3'011 14'-----110000000 -> 3'011 9'000100011 transition: 3'011 14'-------1000000 -> 3'000 9'000100000 transition: 3'011 14'--------100000 -> 3'001 9'000100001 transition: 3'011 14'---------10000 -> 3'100 9'000100100 transition: 3'011 14'----------1000 -> 3'100 9'000100100 transition: 3'011 14'-----------100 -> 3'011 9'000100011 transition: 3'011 14'------------10 -> 3'000 9'000100000 transition: 3'011 14'-------------1 -> 3'000 9'000100000 Extracting FSM `\Riscado_V.ctrlUnit.readLen' from module `\processorci_top'. found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3579 root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\readLen[1:0] found reset state: 2'10 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y found state code: 2'10 found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$3657 found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$3659 found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP found state code: 2'01 found state code: 2'00 found ctrl output: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:110$233_Y found ctrl output: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:111$234_Y ctrl inputs: { $auto$opt_reduce.cc:137:opt_pmux$3659 $auto$opt_reduce.cc:137:opt_pmux$3657 $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\Riscado_V.\ctrlUnit.$0\readLen[1:0] $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:111$234_Y $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:110$233_Y } transition: 2'00 17'---0000--00000000 -> 2'00 4'0001 transition: 2'00 17'---1000-000000000 -> 2'00 4'0001 transition: 2'00 17'---1000-100000000 -> 2'10 4'1001 transition: 2'00 17'----1000000000000 -> 2'00 4'0001 transition: 2'00 17'000-1001000000000 -> 2'00 4'0001 transition: 2'00 17'--1-1001000000000 -> 2'10 4'1001 transition: 2'00 17'1---1001000000000 -> 2'00 4'0001 transition: 2'00 17'-1--1001000000000 -> 2'01 4'0101 transition: 2'00 17'----100-100000000 -> 2'00 4'0001 transition: 2'00 17'-----10--00000000 -> 2'00 4'0001 transition: 2'00 17'------1--00000000 -> 2'00 4'0001 transition: 2'00 17'---------10000000 -> 2'00 4'0001 transition: 2'00 17'----------1000000 -> 2'00 4'0001 transition: 2'00 17'-----------100000 -> 2'00 4'0001 transition: 2'00 17'------------10000 -> 2'00 4'0001 transition: 2'00 17'-------------1000 -> 2'00 4'0001 transition: 2'00 17'--------------100 -> 2'00 4'0001 transition: 2'00 17'---------------10 -> 2'10 4'1001 transition: 2'00 17'----------------1 -> 2'10 4'1001 transition: 2'10 17'---0000--00000000 -> 2'10 4'1000 transition: 2'10 17'---1000-000000000 -> 2'10 4'1000 transition: 2'10 17'---1000-100000000 -> 2'10 4'1000 transition: 2'10 17'----1000000000000 -> 2'10 4'1000 transition: 2'10 17'000-1001000000000 -> 2'10 4'1000 transition: 2'10 17'--1-1001000000000 -> 2'10 4'1000 transition: 2'10 17'1---1001000000000 -> 2'00 4'0000 transition: 2'10 17'-1--1001000000000 -> 2'01 4'0100 transition: 2'10 17'----100-100000000 -> 2'10 4'1000 transition: 2'10 17'-----10--00000000 -> 2'10 4'1000 transition: 2'10 17'------1--00000000 -> 2'10 4'1000 transition: 2'10 17'---------10000000 -> 2'10 4'1000 transition: 2'10 17'----------1000000 -> 2'10 4'1000 transition: 2'10 17'-----------100000 -> 2'10 4'1000 transition: 2'10 17'------------10000 -> 2'10 4'1000 transition: 2'10 17'-------------1000 -> 2'10 4'1000 transition: 2'10 17'--------------100 -> 2'10 4'1000 transition: 2'10 17'---------------10 -> 2'10 4'1000 transition: 2'10 17'----------------1 -> 2'10 4'1000 transition: 2'01 17'---0000--00000000 -> 2'01 4'0110 transition: 2'01 17'---1000-000000000 -> 2'01 4'0110 transition: 2'01 17'---1000-100000000 -> 2'10 4'1010 transition: 2'01 17'----1000000000000 -> 2'01 4'0110 transition: 2'01 17'000-1001000000000 -> 2'01 4'0110 transition: 2'01 17'--1-1001000000000 -> 2'10 4'1010 transition: 2'01 17'1---1001000000000 -> 2'00 4'0010 transition: 2'01 17'-1--1001000000000 -> 2'01 4'0110 transition: 2'01 17'----100-100000000 -> 2'01 4'0110 transition: 2'01 17'-----10--00000000 -> 2'01 4'0110 transition: 2'01 17'------1--00000000 -> 2'01 4'0110 transition: 2'01 17'---------10000000 -> 2'01 4'0110 transition: 2'01 17'----------1000000 -> 2'01 4'0110 transition: 2'01 17'-----------100000 -> 2'01 4'0110 transition: 2'01 17'------------10000 -> 2'01 4'0110 transition: 2'01 17'-------------1000 -> 2'01 4'0110 transition: 2'01 17'--------------100 -> 2'01 4'0110 transition: 2'01 17'---------------10 -> 2'10 4'1010 transition: 2'01 17'----------------1 -> 2'10 4'1010 Extracting FSM `\Riscado_V.ctrlUnit.regDataSrc' from module `\processorci_top'. found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3573 root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\regDataSrc[1:0] found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y found state code: 2'01 found state code: 2'10 found state code: 2'00 found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:80$184_Y found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:79$183_Y found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:78$182_Y ctrl inputs: { $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:78$182_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:79$183_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:80$184_Y $flatten\Riscado_V.\ctrlUnit.$0\regDataSrc[1:0] } transition: 2'00 13'0000-00000000 -> 2'00 5'10000 transition: 2'00 13'1000000000000 -> 2'00 5'10000 transition: 2'00 13'1000100000000 -> 2'01 5'10001 transition: 2'00 13'-100000000000 -> 2'00 5'10000 transition: 2'00 13'-100100000000 -> 2'01 5'10001 transition: 2'00 13'--10000000000 -> 2'00 5'10000 transition: 2'00 13'--10100000000 -> 2'10 5'10010 transition: 2'00 13'---1000000000 -> 2'00 5'10000 transition: 2'00 13'---1100000000 -> 2'10 5'10010 transition: 2'00 13'-----10000000 -> 2'00 5'10000 transition: 2'00 13'------1000000 -> 2'00 5'10000 transition: 2'00 13'-------100000 -> 2'00 5'10000 transition: 2'00 13'--------10000 -> 2'00 5'10000 transition: 2'00 13'---------1000 -> 2'00 5'10000 transition: 2'00 13'----------100 -> 2'00 5'10000 transition: 2'00 13'-----------10 -> 2'00 5'10000 transition: 2'00 13'------------1 -> 2'00 5'10000 transition: 2'10 13'0000-00000000 -> 2'10 5'00110 transition: 2'10 13'1000000000000 -> 2'10 5'00110 transition: 2'10 13'1000100000000 -> 2'01 5'00101 transition: 2'10 13'-100000000000 -> 2'10 5'00110 transition: 2'10 13'-100100000000 -> 2'01 5'00101 transition: 2'10 13'--10000000000 -> 2'10 5'00110 transition: 2'10 13'--10100000000 -> 2'10 5'00110 transition: 2'10 13'---1000000000 -> 2'10 5'00110 transition: 2'10 13'---1100000000 -> 2'10 5'00110 transition: 2'10 13'-----10000000 -> 2'10 5'00110 transition: 2'10 13'------1000000 -> 2'10 5'00110 transition: 2'10 13'-------100000 -> 2'10 5'00110 transition: 2'10 13'--------10000 -> 2'10 5'00110 transition: 2'10 13'---------1000 -> 2'10 5'00110 transition: 2'10 13'----------100 -> 2'10 5'00110 transition: 2'10 13'-----------10 -> 2'00 5'00100 transition: 2'10 13'------------1 -> 2'10 5'00110 transition: 2'01 13'0000-00000000 -> 2'01 5'01001 transition: 2'01 13'1000000000000 -> 2'01 5'01001 transition: 2'01 13'1000100000000 -> 2'01 5'01001 transition: 2'01 13'-100000000000 -> 2'01 5'01001 transition: 2'01 13'-100100000000 -> 2'01 5'01001 transition: 2'01 13'--10000000000 -> 2'01 5'01001 transition: 2'01 13'--10100000000 -> 2'10 5'01010 transition: 2'01 13'---1000000000 -> 2'01 5'01001 transition: 2'01 13'---1100000000 -> 2'10 5'01010 transition: 2'01 13'-----10000000 -> 2'01 5'01001 transition: 2'01 13'------1000000 -> 2'01 5'01001 transition: 2'01 13'-------100000 -> 2'01 5'01001 transition: 2'01 13'--------10000 -> 2'01 5'01001 transition: 2'01 13'---------1000 -> 2'01 5'01001 transition: 2'01 13'----------100 -> 2'01 5'01001 transition: 2'01 13'-----------10 -> 2'00 5'01000 transition: 2'01 13'------------1 -> 2'01 5'01001 Extracting FSM `\Riscado_V.ctrlUnit.state' from module `\processorci_top'. found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3582 root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y found state code: 3'000 found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:307$60_Y found state code: 3'101 found state code: 3'100 found state code: 3'011 found ctrl input: $flatten\Riscado_V.\ctrlUnit.$or$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:175$44_Y found state code: 3'010 found state code: 3'001 found ctrl output: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y found ctrl output: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y found ctrl output: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y found ctrl output: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y found ctrl output: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:307$60_Y found ctrl output: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y ctrl inputs: { $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$or$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:175$44_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:307$60_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y $flatten\Riscado_V.\ctrlUnit.$0\state[2:0] } transition: 3'000 11'----------0 -> 3'001 9'000001001 transition: 3'000 11'----------1 -> 3'000 9'000001000 transition: 3'100 11'0000-000000 -> 3'000 9'010000000 transition: 3'100 11'1000-000000 -> 3'101 9'010000101 transition: 3'100 11'-100-000000 -> 3'000 9'010000000 transition: 3'100 11'--10-000000 -> 3'000 9'010000000 transition: 3'100 11'---1-000000 -> 3'000 9'010000000 transition: 3'100 11'-----100000 -> 3'000 9'010000000 transition: 3'100 11'------10000 -> 3'000 9'010000000 transition: 3'100 11'-------1000 -> 3'000 9'010000000 transition: 3'100 11'--------100 -> 3'000 9'010000000 transition: 3'100 11'---------10 -> 3'000 9'010000000 transition: 3'100 11'----------1 -> 3'000 9'010000000 transition: 3'010 11'0000-000000 -> 3'000 9'000100000 transition: 3'010 11'1000-000000 -> 3'011 9'000100011 transition: 3'010 11'-100-000000 -> 3'011 9'000100011 transition: 3'010 11'--10-000000 -> 3'011 9'000100011 transition: 3'010 11'---1-000000 -> 3'011 9'000100011 transition: 3'010 11'-----100000 -> 3'011 9'000100011 transition: 3'010 11'------10000 -> 3'000 9'000100000 transition: 3'010 11'-------1000 -> 3'000 9'000100000 transition: 3'010 11'--------100 -> 3'000 9'000100000 transition: 3'010 11'---------10 -> 3'000 9'000100000 transition: 3'010 11'----------1 -> 3'000 9'000100000 transition: 3'001 11'----------0 -> 3'010 9'000010010 transition: 3'001 11'----------1 -> 3'000 9'000010000 transition: 3'101 11'0000-000000 -> 3'000 9'100000000 transition: 3'101 11'1000-000000 -> 3'000 9'100000000 transition: 3'101 11'-100-000000 -> 3'101 9'100000101 transition: 3'101 11'--10-000000 -> 3'000 9'100000000 transition: 3'101 11'---1-000000 -> 3'000 9'100000000 transition: 3'101 11'-----100000 -> 3'101 9'100000101 transition: 3'101 11'------10000 -> 3'000 9'100000000 transition: 3'101 11'-------1000 -> 3'000 9'100000000 transition: 3'101 11'--------100 -> 3'000 9'100000000 transition: 3'101 11'---------10 -> 3'000 9'100000000 transition: 3'101 11'----------1 -> 3'000 9'100000000 transition: 3'011 11'0000-000000 -> 3'000 9'001000000 transition: 3'011 11'1000-000000 -> 3'100 9'001000100 transition: 3'011 11'-100-000000 -> 3'100 9'001000100 transition: 3'011 11'--10-000000 -> 3'000 9'001000000 transition: 3'011 11'---1-000000 -> 3'000 9'001000000 transition: 3'011 11'----0100000 -> 3'000 9'001000000 transition: 3'011 11'----1100000 -> 3'100 9'001000100 transition: 3'011 11'------10000 -> 3'000 9'001000000 transition: 3'011 11'-------1000 -> 3'000 9'001000000 transition: 3'011 11'--------100 -> 3'000 9'001000000 transition: 3'011 11'---------10 -> 3'000 9'001000000 transition: 3'011 11'----------1 -> 3'000 9'001000000 Extracting FSM `\Riscado_V.ctrlUnit.writeLen' from module `\processorci_top'. found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3580 root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\writeLen[1:0] found reset state: 2'10 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2766_CMP found state code: 2'10 found state code: 2'01 found state code: 2'00 found ctrl output: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:88$229_Y found ctrl output: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:89$230_Y ctrl inputs: { $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2766_CMP $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\Riscado_V.\ctrlUnit.$0\writeLen[1:0] $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:89$230_Y $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:88$229_Y } transition: 2'00 18'---0000---00000000 -> 2'00 4'0001 transition: 2'00 18'---100000000000000 -> 2'00 4'0001 transition: 2'00 18'000100010000000000 -> 2'00 4'0001 transition: 2'00 18'--1100010000000000 -> 2'00 4'0001 transition: 2'00 18'-1-100010000000000 -> 2'01 4'0101 transition: 2'00 18'1--100010000000000 -> 2'10 4'1001 transition: 2'00 18'---1000-1000000000 -> 2'00 4'0001 transition: 2'00 18'---1000--100000000 -> 2'00 4'0001 transition: 2'00 18'----100---00000000 -> 2'00 4'0001 transition: 2'00 18'-----10---00000000 -> 2'00 4'0001 transition: 2'00 18'------1---00000000 -> 2'00 4'0001 transition: 2'00 18'----------10000000 -> 2'00 4'0001 transition: 2'00 18'-----------1000000 -> 2'00 4'0001 transition: 2'00 18'------------100000 -> 2'00 4'0001 transition: 2'00 18'-------------10000 -> 2'00 4'0001 transition: 2'00 18'--------------1000 -> 2'00 4'0001 transition: 2'00 18'---------------100 -> 2'00 4'0001 transition: 2'00 18'----------------10 -> 2'10 4'1001 transition: 2'00 18'-----------------1 -> 2'10 4'1001 transition: 2'10 18'---0000---00000000 -> 2'10 4'1000 transition: 2'10 18'---100000000000000 -> 2'10 4'1000 transition: 2'10 18'000100010000000000 -> 2'10 4'1000 transition: 2'10 18'--1100010000000000 -> 2'00 4'0000 transition: 2'10 18'-1-100010000000000 -> 2'01 4'0100 transition: 2'10 18'1--100010000000000 -> 2'10 4'1000 transition: 2'10 18'---1000-1000000000 -> 2'10 4'1000 transition: 2'10 18'---1000--100000000 -> 2'10 4'1000 transition: 2'10 18'----100---00000000 -> 2'10 4'1000 transition: 2'10 18'-----10---00000000 -> 2'10 4'1000 transition: 2'10 18'------1---00000000 -> 2'10 4'1000 transition: 2'10 18'----------10000000 -> 2'10 4'1000 transition: 2'10 18'-----------1000000 -> 2'10 4'1000 transition: 2'10 18'------------100000 -> 2'10 4'1000 transition: 2'10 18'-------------10000 -> 2'10 4'1000 transition: 2'10 18'--------------1000 -> 2'10 4'1000 transition: 2'10 18'---------------100 -> 2'10 4'1000 transition: 2'10 18'----------------10 -> 2'10 4'1000 transition: 2'10 18'-----------------1 -> 2'10 4'1000 transition: 2'01 18'---0000---00000000 -> 2'01 4'0110 transition: 2'01 18'---100000000000000 -> 2'01 4'0110 transition: 2'01 18'000100010000000000 -> 2'01 4'0110 transition: 2'01 18'--1100010000000000 -> 2'00 4'0010 transition: 2'01 18'-1-100010000000000 -> 2'01 4'0110 transition: 2'01 18'1--100010000000000 -> 2'10 4'1010 transition: 2'01 18'---1000-1000000000 -> 2'01 4'0110 transition: 2'01 18'---1000--100000000 -> 2'01 4'0110 transition: 2'01 18'----100---00000000 -> 2'01 4'0110 transition: 2'01 18'-----10---00000000 -> 2'01 4'0110 transition: 2'01 18'------1---00000000 -> 2'01 4'0110 transition: 2'01 18'----------10000000 -> 2'01 4'0110 transition: 2'01 18'-----------1000000 -> 2'01 4'0110 transition: 2'01 18'------------100000 -> 2'01 4'0110 transition: 2'01 18'-------------10000 -> 2'01 4'0110 transition: 2'01 18'--------------1000 -> 2'01 4'0110 transition: 2'01 18'---------------100 -> 2'01 4'0110 transition: 2'01 18'----------------10 -> 2'10 4'1010 transition: 2'01 18'-----------------1 -> 2'10 4'1010 17.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.writeLen$3737' from module `\processorci_top'. Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.state$3729' from module `\processorci_top'. Merging pattern 11'0000-000000 and 11'1000-000000 from group (4 0 9'100000000). Merging pattern 11'1000-000000 and 11'0000-000000 from group (4 0 9'100000000). Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.regDataSrc$3724' from module `\processorci_top'. Merging pattern 13'--10000000000 and 13'--10100000000 from group (1 1 5'00110). Merging pattern 13'---1000000000 and 13'---1100000000 from group (1 1 5'00110). Merging pattern 13'--10100000000 and 13'--10000000000 from group (1 1 5'00110). Merging pattern 13'---1100000000 and 13'---1000000000 from group (1 1 5'00110). Merging pattern 13'1000000000000 and 13'1000100000000 from group (2 2 5'01001). Merging pattern 13'-100000000000 and 13'-100100000000 from group (2 2 5'01001). Merging pattern 13'1000100000000 and 13'1000000000000 from group (2 2 5'01001). Merging pattern 13'-100100000000 and 13'-100000000000 from group (2 2 5'01001). Merging pattern 13'0000-00000000 and 13'1000-00000000 from group (2 2 5'01001). Merging pattern 13'1000-00000000 and 13'0000-00000000 from group (2 2 5'01001). Merging pattern 13'-000-00000000 and 13'-100-00000000 from group (2 2 5'01001). Merging pattern 13'-100-00000000 and 13'-000-00000000 from group (2 2 5'01001). Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.readLen$3720' from module `\processorci_top'. Merging pattern 17'---1000-000000000 and 17'---1000-100000000 from group (1 1 4'1000). Merging pattern 17'---1000-100000000 and 17'---1000-000000000 from group (1 1 4'1000). Merging pattern 17'---0000--00000000 and 17'---1000--00000000 from group (1 1 4'1000). Merging pattern 17'---1000--00000000 and 17'---0000--00000000 from group (1 1 4'1000). Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcB$3712' from module `\processorci_top'. Merging pattern 14'1000-000000000 and 14'1000-100000000 from group (2 2 9'000001010). Merging pattern 14'1000-100000000 and 14'1000-000000000 from group (2 2 9'000001010). Merging pattern 14'0000--00000000 and 14'1000--00000000 from group (2 2 9'000001010). Merging pattern 14'1000--00000000 and 14'0000--00000000 from group (2 2 9'000001010). Merging pattern 14'-100-000000000 and 14'-100-100000000 from group (3 3 9'001000001). Merging pattern 14'--10-000000000 and 14'--10-100000000 from group (3 3 9'001000001). Merging pattern 14'-100-100000000 and 14'-100-000000000 from group (3 3 9'001000001). Merging pattern 14'--10-100000000 and 14'--10-000000000 from group (3 3 9'001000001). Merging pattern 14'---1-000000000 and 14'---1-100000000 from group (4 4 9'000010101). Merging pattern 14'---1-100000000 and 14'---1-000000000 from group (4 4 9'000010101). Merging pattern 14'----0010000000 and 14'----1010000000 from group (5 5 9'000100011). Merging pattern 14'----1010000000 and 14'----0010000000 from group (5 5 9'000100011). Merging pattern 14'-----010000000 and 14'-----110000000 from group (5 5 9'000100011). Merging pattern 14'-----110000000 and 14'-----010000000 from group (5 5 9'000100011). Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcA$3707' from module `\processorci_top'. Merging pattern 14'1000-000000000 and 14'1000-100000000 from group (0 0 5'10000). Merging pattern 14'-100-000000000 and 14'-100-100000000 from group (0 0 5'10000). Merging pattern 14'--10-000000000 and 14'--10-100000000 from group (0 0 5'10000). Merging pattern 14'1000-100000000 and 14'1000-000000000 from group (0 0 5'10000). Merging pattern 14'-100-100000000 and 14'-100-000000000 from group (0 0 5'10000). Merging pattern 14'--10-100000000 and 14'--10-000000000 from group (0 0 5'10000). Merging pattern 14'0000--00000000 and 14'1000--00000000 from group (0 0 5'10000). Merging pattern 14'1000--00000000 and 14'0000--00000000 from group (0 0 5'10000). Merging pattern 14'-000--00000000 and 14'-100--00000000 from group (0 0 5'10000). Merging pattern 14'-100--00000000 and 14'-000--00000000 from group (0 0 5'10000). Merging pattern 14'--00--00000000 and 14'--10--00000000 from group (0 0 5'10000). Merging pattern 14'--10--00000000 and 14'--00--00000000 from group (0 0 5'10000). Merging pattern 14'---1-000000000 and 14'---1-100000000 from group (1 1 5'00110). Merging pattern 14'---1-100000000 and 14'---1-000000000 from group (1 1 5'00110). Merging pattern 14'----0010000000 and 14'----1010000000 from group (1 1 5'00110). Merging pattern 14'----1010000000 and 14'----0010000000 from group (1 1 5'00110). Merging pattern 14'-----010000000 and 14'-----110000000 from group (1 1 5'00110). Merging pattern 14'-----110000000 and 14'-----010000000 from group (1 1 5'00110). Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.aluOperation$3693' from module `\processorci_top'. Merging pattern 25'--------1000-000-00000--0 and 25'--------1000-100-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'---------100-000-00000--0 and 25'---------100-100-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'----------10-000-00000--0 and 25'----------10-100-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'-----------1-000-00000--0 and 25'-----------1-100-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'--------1000-100-00000--0 and 25'--------1000-000-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'---------100-100-00000--0 and 25'---------100-000-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'----------10-100-00000--0 and 25'----------10-000-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'-----------1-100-00000--0 and 25'-----------1-000-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'------------0010-00000--0 and 25'------------1010-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'------------1010-00000--0 and 25'------------0010-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'--------0000--00-00000--0 and 25'--------1000--00-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'--------1000--00-00000--0 and 25'--------0000--00-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'---------000--00-00000--0 and 25'---------100--00-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'---------100--00-00000--0 and 25'---------000--00-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'----------00--00-00000--0 and 25'----------10--00-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'----------10--00-00000--0 and 25'----------00--00-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'-----------0--00-00000--0 and 25'-----------1--00-00000--0 from group (0 0 16'0000100000000000). Merging pattern 25'-----------1--00-00000--0 and 25'-----------0--00-00000--0 from group (0 0 16'0000100000000000). Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3687' from module `\processorci_top'. Merging pattern 2'0- and 2'1- from group (3 0 6'010000). Merging pattern 2'1- and 2'0- from group (3 0 6'010000). Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$3680' from module `\processorci_top'. 17.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 178 unused cells and 187 unused wires. <suppressed ~188 debug messages> 17.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$3680' from module `\processorci_top'. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3687' from module `\processorci_top'. Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0]. Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1]. Removing unused output signal $flatten\Controller.\Uart.$procmux$2294_CMP. Removing unused output signal $flatten\Controller.\Uart.$procmux$2296_CMP. Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.aluOperation$3693' from module `\processorci_top'. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluOperation[3:0] [0]. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluOperation[3:0] [1]. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluOperation[3:0] [2]. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluOperation[3:0] [3]. Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcA$3707' from module `\processorci_top'. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluSrcA[1:0] [0]. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluSrcA[1:0] [1]. Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcB$3712' from module `\processorci_top'. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluSrcB[2:0] [0]. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluSrcB[2:0] [1]. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluSrcB[2:0] [2]. Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.readLen$3720' from module `\processorci_top'. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\readLen[1:0] [0]. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\readLen[1:0] [1]. Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.regDataSrc$3724' from module `\processorci_top'. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\regDataSrc[1:0] [0]. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\regDataSrc[1:0] [1]. Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.state$3729' from module `\processorci_top'. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\state[2:0] [0]. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\state[2:0] [1]. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\state[2:0] [2]. Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.writeLen$3737' from module `\processorci_top'. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\writeLen[1:0] [0]. Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\writeLen[1:0] [1]. 17.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$3680' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3687' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- Recoding FSM `$fsm$\Riscado_V.ctrlUnit.aluOperation$3693' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> ------------1 1000 -> -----------1- 0100 -> ----------1-- 1100 -> ---------1--- 0010 -> --------1---- 1010 -> -------1----- 0110 -> ------1------ 0001 -> -----1------- 1001 -> ----1-------- 0101 -> ---1--------- 1101 -> --1---------- 0011 -> -1----------- 0111 -> 1------------ Recoding FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcA$3707' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> -1 10 -> 1- Recoding FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcB$3712' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> -----1 100 -> ----1- 010 -> ---1-- 001 -> --1--- 101 -> -1---- 011 -> 1----- Recoding FSM `$fsm$\Riscado_V.ctrlUnit.readLen$3720' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> -1- 10 -> --1 01 -> 1-- Recoding FSM `$fsm$\Riscado_V.ctrlUnit.regDataSrc$3724' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> --1 10 -> -1- 01 -> 1-- Recoding FSM `$fsm$\Riscado_V.ctrlUnit.state$3729' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> -----1 100 -> ----1- 010 -> ---1-- 001 -> --1--- 101 -> -1---- 011 -> 1----- Recoding FSM `$fsm$\Riscado_V.ctrlUnit.writeLen$3737' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> -1- 10 -> --1 01 -> 1-- 17.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$3680' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$3680 (\Controller.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \Controller.Uart.i_uart_rx.payload_done 1: \Controller.Uart.i_uart_rx.next_bit 2: \Controller.Uart.i_uart_rx.rxd_reg 3: \ResetBootSystem.reset_o Output signals: 0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1181_Y 1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1172_Y 2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1168_Y 3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1167_Y 4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1155_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'01-- -> 0 5'01010 1: 0 4'1--- -> 0 5'01010 2: 0 4'00-- -> 2 5'01010 3: 1 4'1--- -> 0 5'00100 4: 1 4'0--0 -> 1 5'00100 5: 1 4'0--1 -> 3 5'00100 6: 2 4'1--- -> 0 5'00011 7: 2 4'0-1- -> 1 5'00011 8: 2 4'0-0- -> 2 5'00011 9: 3 4'0-1- -> 0 5'10010 10: 3 4'1--- -> 0 5'10010 11: 3 4'0-0- -> 3 5'10010 ------------------------------------- FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3687' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$3687 (\Controller.Uart.tx_fifo_read_state): Number of input signals: 2 Number of output signals: 2 Number of state bits: 4 Input signals: 0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1041_Y 1: \ResetBootSystem.reset_o Output signals: 0: $flatten\Controller.\Uart.$procmux$2283_CMP 1: $flatten\Controller.\Uart.$procmux$2289_CMP State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 2'00 -> 0 2'01 1: 0 2'1- -> 0 2'01 2: 0 2'01 -> 2 2'01 3: 1 2'1- -> 0 2'10 4: 1 2'0- -> 3 2'10 5: 2 2'1- -> 0 2'00 6: 2 2'0- -> 1 2'00 7: 3 2'-- -> 0 2'00 ------------------------------------- FSM `$fsm$\Riscado_V.ctrlUnit.aluOperation$3693' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Riscado_V.ctrlUnit.aluOperation$3693 (\Riscado_V.ctrlUnit.aluOperation): Number of input signals: 25 Number of output signals: 12 Number of state bits: 13 Input signals: 0: \Controller.Interpreter.core_reset 1: $auto$opt_reduce.cc:137:opt_pmux$3663 2: $auto$opt_reduce.cc:137:opt_pmux$3665 3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y 4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y 5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y 6: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y 7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y 8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:123$28_Y 9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y 10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y 11: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y 12: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y 13: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y 14: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y 15: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y 16: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y 17: $flatten\Riscado_V.\ctrlUnit.$procmux$2764_CMP 18: $flatten\Riscado_V.\ctrlUnit.$procmux$2765_CMP 19: $flatten\Riscado_V.\ctrlUnit.$procmux$2766_CMP 20: $flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP 21: $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP 22: $flatten\Riscado_V.\ctrlUnit.$procmux$2973_CMP 23: $flatten\Riscado_V.\ctrlUnit.$procmux$3046_CMP 24: $flatten\Riscado_V.\ctrlUnit.$procmux$3060_CMP Output signals: 0: $flatten\Riscado_V.\alu.$procmux$3468_CMP 1: $flatten\Riscado_V.\alu.$procmux$3467_CMP 2: $flatten\Riscado_V.\alu.$procmux$3466_CMP 3: $flatten\Riscado_V.\alu.$procmux$3465_CMP 4: $flatten\Riscado_V.\alu.$procmux$3469_CMP 5: $flatten\Riscado_V.\alu.$procmux$3470_CMP 6: $flatten\Riscado_V.\alu.$procmux$3471_CMP 7: $flatten\Riscado_V.\alu.$procmux$3472_CMP 8: $flatten\Riscado_V.\alu.$procmux$3473_CMP 9: $flatten\Riscado_V.\alu.$procmux$3474_CMP 10: $flatten\Riscado_V.\alu.$procmux$3475_CMP 11: $flatten\Riscado_V.\alu.$procmux$3476_CMP State encoding: 0: 13'------------1 1: 13'-----------1- 2: 13'----------1-- 3: 13'---------1--- 4: 13'--------1---- 5: 13'-------1----- 6: 13'------1------ 7: 13'-----1------- 8: 13'----1-------- 9: 13'---1--------- 10: 13'--1---------- 11: 13'-1----------- 12: 13'1------------ Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 25'-----1---------1000000--0 -> 0 12'100000000000 1: 0 25'--------------00-00000--0 -> 0 12'100000000000 2: 0 25'-------------010-00000--0 -> 0 12'100000000000 3: 0 25'-----1-----------10000--0 -> 0 12'100000000000 4: 0 25'------------------1000--0 -> 0 12'100000000000 5: 0 25'--------------------10--0 -> 0 12'100000000000 6: 0 25'------------------------1 -> 0 12'100000000000 7: 0 25'-----1---------1100000--0 -> 1 12'100000000000 8: 0 25'------1--------1-00000--0 -> 2 12'100000000000 9: 0 25'------1----------10000--0 -> 2 12'100000000000 10: 0 25'-------------110-00000000 -> 3 12'100000000000 11: 0 25'-------------110-000001-0 -> 4 12'100000000000 12: 0 25'---1-----------1-00000--0 -> 4 12'100000000000 13: 0 25'---1-------------10000--0 -> 4 12'100000000000 14: 0 25'-------------------100--0 -> 5 12'100000000000 15: 0 25'-------1-------1-00000--0 -> 6 12'100000000000 16: 0 25'-------1---------10000--0 -> 6 12'100000000000 17: 0 25'----1----------1-00000--0 -> 7 12'100000000000 18: 0 25'----1------------10000--0 -> 7 12'100000000000 19: 0 25'---------------------1--0 -> 8 12'100000000000 20: 0 25'--1------------1000000--0 -> 9 12'100000000000 21: 0 25'--1-------------010000--0 -> 9 12'100000000000 22: 0 25'--1------------1100000--0 -> 10 12'100000000000 23: 0 25'--1-------------110000--0 -> 10 12'100000000000 24: 0 25'-------------110-00000-10 -> 11 12'100000000000 25: 0 25'1--------------1-00000--0 -> 11 12'100000000000 26: 0 25'1----------------10000--0 -> 11 12'100000000000 27: 0 25'-1-------------1-00000--0 -> 12 12'100000000000 28: 0 25'-1---------------10000--0 -> 12 12'100000000000 29: 1 25'-----1---------1000000--0 -> 0 12'000000000001 30: 1 25'--------1000-100-00000--0 -> 0 12'000000000001 31: 1 25'---------100-100-00000--0 -> 0 12'000000000001 32: 1 25'----------10-100-00000--0 -> 0 12'000000000001 33: 1 25'-----------1-100-00000--0 -> 0 12'000000000001 34: 1 25'------------1010-00000--0 -> 0 12'000000000001 35: 1 25'-----1-----------10000--0 -> 0 12'000000000001 36: 1 25'------------------1000--0 -> 0 12'000000000001 37: 1 25'-----1---------1100000--0 -> 1 12'000000000001 38: 1 25'--------1000-000-00000--0 -> 1 12'000000000001 39: 1 25'---------100-000-00000--0 -> 1 12'000000000001 40: 1 25'----------10-000-00000--0 -> 1 12'000000000001 41: 1 25'-----------1-000-00000--0 -> 1 12'000000000001 42: 1 25'--------0000--00-00000--0 -> 1 12'000000000001 43: 1 25'------------0010-00000--0 -> 1 12'000000000001 44: 1 25'--------------------10--0 -> 1 12'000000000001 45: 1 25'------------------------1 -> 1 12'000000000001 46: 1 25'------1--------1-00000--0 -> 2 12'000000000001 47: 1 25'------1----------10000--0 -> 2 12'000000000001 48: 1 25'-------------110-00000000 -> 3 12'000000000001 49: 1 25'-------------110-000001-0 -> 4 12'000000000001 50: 1 25'---1-----------1-00000--0 -> 4 12'000000000001 51: 1 25'---1-------------10000--0 -> 4 12'000000000001 52: 1 25'-------------------100--0 -> 5 12'000000000001 53: 1 25'-------1-------1-00000--0 -> 6 12'000000000001 54: 1 25'-------1---------10000--0 -> 6 12'000000000001 55: 1 25'----1----------1-00000--0 -> 7 12'000000000001 56: 1 25'----1------------10000--0 -> 7 12'000000000001 57: 1 25'---------------------1--0 -> 8 12'000000000001 58: 1 25'--1------------1000000--0 -> 9 12'000000000001 59: 1 25'--1-------------010000--0 -> 9 12'000000000001 60: 1 25'--1------------1100000--0 -> 10 12'000000000001 61: 1 25'--1-------------110000--0 -> 10 12'000000000001 62: 1 25'-------------110-00000-10 -> 11 12'000000000001 63: 1 25'1--------------1-00000--0 -> 11 12'000000000001 64: 1 25'1----------------10000--0 -> 11 12'000000000001 65: 1 25'-1-------------1-00000--0 -> 12 12'000000000001 66: 1 25'-1---------------10000--0 -> 12 12'000000000001 67: 2 25'-----1---------1000000--0 -> 0 12'000010000000 68: 2 25'--------1000-100-00000--0 -> 0 12'000010000000 69: 2 25'---------100-100-00000--0 -> 0 12'000010000000 70: 2 25'----------10-100-00000--0 -> 0 12'000010000000 71: 2 25'-----------1-100-00000--0 -> 0 12'000010000000 72: 2 25'------------1010-00000--0 -> 0 12'000010000000 73: 2 25'-----1-----------10000--0 -> 0 12'000010000000 74: 2 25'------------------1000--0 -> 0 12'000010000000 75: 2 25'-----1---------1100000--0 -> 1 12'000010000000 76: 2 25'--------1000-000-00000--0 -> 2 12'000010000000 77: 2 25'---------100-000-00000--0 -> 2 12'000010000000 78: 2 25'----------10-000-00000--0 -> 2 12'000010000000 79: 2 25'-----------1-000-00000--0 -> 2 12'000010000000 80: 2 25'--------0000--00-00000--0 -> 2 12'000010000000 81: 2 25'------------0010-00000--0 -> 2 12'000010000000 82: 2 25'------1--------1-00000--0 -> 2 12'000010000000 83: 2 25'------1----------10000--0 -> 2 12'000010000000 84: 2 25'--------------------10--0 -> 2 12'000010000000 85: 2 25'------------------------1 -> 2 12'000010000000 86: 2 25'-------------110-00000000 -> 3 12'000010000000 87: 2 25'-------------110-000001-0 -> 4 12'000010000000 88: 2 25'---1-----------1-00000--0 -> 4 12'000010000000 89: 2 25'---1-------------10000--0 -> 4 12'000010000000 90: 2 25'-------------------100--0 -> 5 12'000010000000 91: 2 25'-------1-------1-00000--0 -> 6 12'000010000000 92: 2 25'-------1---------10000--0 -> 6 12'000010000000 93: 2 25'----1----------1-00000--0 -> 7 12'000010000000 94: 2 25'----1------------10000--0 -> 7 12'000010000000 95: 2 25'---------------------1--0 -> 8 12'000010000000 96: 2 25'--1------------1000000--0 -> 9 12'000010000000 97: 2 25'--1-------------010000--0 -> 9 12'000010000000 98: 2 25'--1------------1100000--0 -> 10 12'000010000000 99: 2 25'--1-------------110000--0 -> 10 12'000010000000 100: 2 25'-------------110-00000-10 -> 11 12'000010000000 101: 2 25'1--------------1-00000--0 -> 11 12'000010000000 102: 2 25'1----------------10000--0 -> 11 12'000010000000 103: 2 25'-1-------------1-00000--0 -> 12 12'000010000000 104: 2 25'-1---------------10000--0 -> 12 12'000010000000 105: 3 25'-----1---------1000000--0 -> 0 12'000000001000 106: 3 25'--------1000-100-00000--0 -> 0 12'000000001000 107: 3 25'---------100-100-00000--0 -> 0 12'000000001000 108: 3 25'----------10-100-00000--0 -> 0 12'000000001000 109: 3 25'-----------1-100-00000--0 -> 0 12'000000001000 110: 3 25'------------1010-00000--0 -> 0 12'000000001000 111: 3 25'-----1-----------10000--0 -> 0 12'000000001000 112: 3 25'------------------1000--0 -> 0 12'000000001000 113: 3 25'-----1---------1100000--0 -> 1 12'000000001000 114: 3 25'------1--------1-00000--0 -> 2 12'000000001000 115: 3 25'------1----------10000--0 -> 2 12'000000001000 116: 3 25'-------------110-00000000 -> 3 12'000000001000 117: 3 25'--------1000-000-00000--0 -> 3 12'000000001000 118: 3 25'---------100-000-00000--0 -> 3 12'000000001000 119: 3 25'----------10-000-00000--0 -> 3 12'000000001000 120: 3 25'-----------1-000-00000--0 -> 3 12'000000001000 121: 3 25'--------0000--00-00000--0 -> 3 12'000000001000 122: 3 25'------------0010-00000--0 -> 3 12'000000001000 123: 3 25'--------------------10--0 -> 3 12'000000001000 124: 3 25'------------------------1 -> 3 12'000000001000 125: 3 25'-------------110-000001-0 -> 4 12'000000001000 126: 3 25'---1-----------1-00000--0 -> 4 12'000000001000 127: 3 25'---1-------------10000--0 -> 4 12'000000001000 128: 3 25'-------------------100--0 -> 5 12'000000001000 129: 3 25'-------1-------1-00000--0 -> 6 12'000000001000 130: 3 25'-------1---------10000--0 -> 6 12'000000001000 131: 3 25'----1----------1-00000--0 -> 7 12'000000001000 132: 3 25'----1------------10000--0 -> 7 12'000000001000 133: 3 25'---------------------1--0 -> 8 12'000000001000 134: 3 25'--1------------1000000--0 -> 9 12'000000001000 135: 3 25'--1-------------010000--0 -> 9 12'000000001000 136: 3 25'--1------------1100000--0 -> 10 12'000000001000 137: 3 25'--1-------------110000--0 -> 10 12'000000001000 138: 3 25'-------------110-00000-10 -> 11 12'000000001000 139: 3 25'1--------------1-00000--0 -> 11 12'000000001000 140: 3 25'1----------------10000--0 -> 11 12'000000001000 141: 3 25'-1-------------1-00000--0 -> 12 12'000000001000 142: 3 25'-1---------------10000--0 -> 12 12'000000001000 143: 4 25'-----1---------1000000--0 -> 0 12'001000000000 144: 4 25'--------1000-100-00000--0 -> 0 12'001000000000 145: 4 25'---------100-100-00000--0 -> 0 12'001000000000 146: 4 25'----------10-100-00000--0 -> 0 12'001000000000 147: 4 25'-----------1-100-00000--0 -> 0 12'001000000000 148: 4 25'------------1010-00000--0 -> 0 12'001000000000 149: 4 25'-----1-----------10000--0 -> 0 12'001000000000 150: 4 25'------------------1000--0 -> 0 12'001000000000 151: 4 25'-----1---------1100000--0 -> 1 12'001000000000 152: 4 25'------1--------1-00000--0 -> 2 12'001000000000 153: 4 25'------1----------10000--0 -> 2 12'001000000000 154: 4 25'-------------110-00000000 -> 3 12'001000000000 155: 4 25'-------------110-000001-0 -> 4 12'001000000000 156: 4 25'--------1000-000-00000--0 -> 4 12'001000000000 157: 4 25'---------100-000-00000--0 -> 4 12'001000000000 158: 4 25'----------10-000-00000--0 -> 4 12'001000000000 159: 4 25'-----------1-000-00000--0 -> 4 12'001000000000 160: 4 25'--------0000--00-00000--0 -> 4 12'001000000000 161: 4 25'------------0010-00000--0 -> 4 12'001000000000 162: 4 25'---1-----------1-00000--0 -> 4 12'001000000000 163: 4 25'---1-------------10000--0 -> 4 12'001000000000 164: 4 25'--------------------10--0 -> 4 12'001000000000 165: 4 25'------------------------1 -> 4 12'001000000000 166: 4 25'-------------------100--0 -> 5 12'001000000000 167: 4 25'-------1-------1-00000--0 -> 6 12'001000000000 168: 4 25'-------1---------10000--0 -> 6 12'001000000000 169: 4 25'----1----------1-00000--0 -> 7 12'001000000000 170: 4 25'----1------------10000--0 -> 7 12'001000000000 171: 4 25'---------------------1--0 -> 8 12'001000000000 172: 4 25'--1------------1000000--0 -> 9 12'001000000000 173: 4 25'--1-------------010000--0 -> 9 12'001000000000 174: 4 25'--1------------1100000--0 -> 10 12'001000000000 175: 4 25'--1-------------110000--0 -> 10 12'001000000000 176: 4 25'-------------110-00000-10 -> 11 12'001000000000 177: 4 25'1--------------1-00000--0 -> 11 12'001000000000 178: 4 25'1----------------10000--0 -> 11 12'001000000000 179: 4 25'-1-------------1-00000--0 -> 12 12'001000000000 180: 4 25'-1---------------10000--0 -> 12 12'001000000000 181: 5 25'-----1---------1000000--0 -> 0 12'000000000100 182: 5 25'--------1000-100-00000--0 -> 0 12'000000000100 183: 5 25'---------100-100-00000--0 -> 0 12'000000000100 184: 5 25'----------10-100-00000--0 -> 0 12'000000000100 185: 5 25'-----------1-100-00000--0 -> 0 12'000000000100 186: 5 25'------------1010-00000--0 -> 0 12'000000000100 187: 5 25'-----1-----------10000--0 -> 0 12'000000000100 188: 5 25'------------------1000--0 -> 0 12'000000000100 189: 5 25'-----1---------1100000--0 -> 1 12'000000000100 190: 5 25'------1--------1-00000--0 -> 2 12'000000000100 191: 5 25'------1----------10000--0 -> 2 12'000000000100 192: 5 25'-------------110-00000000 -> 3 12'000000000100 193: 5 25'-------------110-000001-0 -> 4 12'000000000100 194: 5 25'---1-----------1-00000--0 -> 4 12'000000000100 195: 5 25'---1-------------10000--0 -> 4 12'000000000100 196: 5 25'--------1000-000-00000--0 -> 5 12'000000000100 197: 5 25'---------100-000-00000--0 -> 5 12'000000000100 198: 5 25'----------10-000-00000--0 -> 5 12'000000000100 199: 5 25'-----------1-000-00000--0 -> 5 12'000000000100 200: 5 25'--------0000--00-00000--0 -> 5 12'000000000100 201: 5 25'------------0010-00000--0 -> 5 12'000000000100 202: 5 25'-------------------100--0 -> 5 12'000000000100 203: 5 25'--------------------10--0 -> 5 12'000000000100 204: 5 25'------------------------1 -> 5 12'000000000100 205: 5 25'-------1-------1-00000--0 -> 6 12'000000000100 206: 5 25'-------1---------10000--0 -> 6 12'000000000100 207: 5 25'----1----------1-00000--0 -> 7 12'000000000100 208: 5 25'----1------------10000--0 -> 7 12'000000000100 209: 5 25'---------------------1--0 -> 8 12'000000000100 210: 5 25'--1------------1000000--0 -> 9 12'000000000100 211: 5 25'--1-------------010000--0 -> 9 12'000000000100 212: 5 25'--1------------1100000--0 -> 10 12'000000000100 213: 5 25'--1-------------110000--0 -> 10 12'000000000100 214: 5 25'-------------110-00000-10 -> 11 12'000000000100 215: 5 25'1--------------1-00000--0 -> 11 12'000000000100 216: 5 25'1----------------10000--0 -> 11 12'000000000100 217: 5 25'-1-------------1-00000--0 -> 12 12'000000000100 218: 5 25'-1---------------10000--0 -> 12 12'000000000100 219: 6 25'-----1---------1000000--0 -> 0 12'000000100000 220: 6 25'--------1000-100-00000--0 -> 0 12'000000100000 221: 6 25'---------100-100-00000--0 -> 0 12'000000100000 222: 6 25'----------10-100-00000--0 -> 0 12'000000100000 223: 6 25'-----------1-100-00000--0 -> 0 12'000000100000 224: 6 25'------------1010-00000--0 -> 0 12'000000100000 225: 6 25'-----1-----------10000--0 -> 0 12'000000100000 226: 6 25'------------------1000--0 -> 0 12'000000100000 227: 6 25'-----1---------1100000--0 -> 1 12'000000100000 228: 6 25'------1--------1-00000--0 -> 2 12'000000100000 229: 6 25'------1----------10000--0 -> 2 12'000000100000 230: 6 25'-------------110-00000000 -> 3 12'000000100000 231: 6 25'-------------110-000001-0 -> 4 12'000000100000 232: 6 25'---1-----------1-00000--0 -> 4 12'000000100000 233: 6 25'---1-------------10000--0 -> 4 12'000000100000 234: 6 25'-------------------100--0 -> 5 12'000000100000 235: 6 25'--------1000-000-00000--0 -> 6 12'000000100000 236: 6 25'---------100-000-00000--0 -> 6 12'000000100000 237: 6 25'----------10-000-00000--0 -> 6 12'000000100000 238: 6 25'-----------1-000-00000--0 -> 6 12'000000100000 239: 6 25'--------0000--00-00000--0 -> 6 12'000000100000 240: 6 25'------------0010-00000--0 -> 6 12'000000100000 241: 6 25'-------1-------1-00000--0 -> 6 12'000000100000 242: 6 25'-------1---------10000--0 -> 6 12'000000100000 243: 6 25'--------------------10--0 -> 6 12'000000100000 244: 6 25'------------------------1 -> 6 12'000000100000 245: 6 25'----1----------1-00000--0 -> 7 12'000000100000 246: 6 25'----1------------10000--0 -> 7 12'000000100000 247: 6 25'---------------------1--0 -> 8 12'000000100000 248: 6 25'--1------------1000000--0 -> 9 12'000000100000 249: 6 25'--1-------------010000--0 -> 9 12'000000100000 250: 6 25'--1------------1100000--0 -> 10 12'000000100000 251: 6 25'--1-------------110000--0 -> 10 12'000000100000 252: 6 25'-------------110-00000-10 -> 11 12'000000100000 253: 6 25'1--------------1-00000--0 -> 11 12'000000100000 254: 6 25'1----------------10000--0 -> 11 12'000000100000 255: 6 25'-1-------------1-00000--0 -> 12 12'000000100000 256: 6 25'-1---------------10000--0 -> 12 12'000000100000 257: 7 25'-----1---------1000000--0 -> 0 12'010000000000 258: 7 25'--------1000-100-00000--0 -> 0 12'010000000000 259: 7 25'---------100-100-00000--0 -> 0 12'010000000000 260: 7 25'----------10-100-00000--0 -> 0 12'010000000000 261: 7 25'-----------1-100-00000--0 -> 0 12'010000000000 262: 7 25'------------1010-00000--0 -> 0 12'010000000000 263: 7 25'-----1-----------10000--0 -> 0 12'010000000000 264: 7 25'------------------1000--0 -> 0 12'010000000000 265: 7 25'-----1---------1100000--0 -> 1 12'010000000000 266: 7 25'------1--------1-00000--0 -> 2 12'010000000000 267: 7 25'------1----------10000--0 -> 2 12'010000000000 268: 7 25'-------------110-00000000 -> 3 12'010000000000 269: 7 25'-------------110-000001-0 -> 4 12'010000000000 270: 7 25'---1-----------1-00000--0 -> 4 12'010000000000 271: 7 25'---1-------------10000--0 -> 4 12'010000000000 272: 7 25'-------------------100--0 -> 5 12'010000000000 273: 7 25'-------1-------1-00000--0 -> 6 12'010000000000 274: 7 25'-------1---------10000--0 -> 6 12'010000000000 275: 7 25'--------1000-000-00000--0 -> 7 12'010000000000 276: 7 25'---------100-000-00000--0 -> 7 12'010000000000 277: 7 25'----------10-000-00000--0 -> 7 12'010000000000 278: 7 25'-----------1-000-00000--0 -> 7 12'010000000000 279: 7 25'--------0000--00-00000--0 -> 7 12'010000000000 280: 7 25'------------0010-00000--0 -> 7 12'010000000000 281: 7 25'----1----------1-00000--0 -> 7 12'010000000000 282: 7 25'----1------------10000--0 -> 7 12'010000000000 283: 7 25'--------------------10--0 -> 7 12'010000000000 284: 7 25'------------------------1 -> 7 12'010000000000 285: 7 25'---------------------1--0 -> 8 12'010000000000 286: 7 25'--1------------1000000--0 -> 9 12'010000000000 287: 7 25'--1-------------010000--0 -> 9 12'010000000000 288: 7 25'--1------------1100000--0 -> 10 12'010000000000 289: 7 25'--1-------------110000--0 -> 10 12'010000000000 290: 7 25'-------------110-00000-10 -> 11 12'010000000000 291: 7 25'1--------------1-00000--0 -> 11 12'010000000000 292: 7 25'1----------------10000--0 -> 11 12'010000000000 293: 7 25'-1-------------1-00000--0 -> 12 12'010000000000 294: 7 25'-1---------------10000--0 -> 12 12'010000000000 295: 8 25'-----1---------1000000--0 -> 0 12'000000000000 296: 8 25'--------1000-100-00000--0 -> 0 12'000000000000 297: 8 25'---------100-100-00000--0 -> 0 12'000000000000 298: 8 25'----------10-100-00000--0 -> 0 12'000000000000 299: 8 25'-----------1-100-00000--0 -> 0 12'000000000000 300: 8 25'------------1010-00000--0 -> 0 12'000000000000 301: 8 25'-----1-----------10000--0 -> 0 12'000000000000 302: 8 25'------------------1000--0 -> 0 12'000000000000 303: 8 25'-----1---------1100000--0 -> 1 12'000000000000 304: 8 25'------1--------1-00000--0 -> 2 12'000000000000 305: 8 25'------1----------10000--0 -> 2 12'000000000000 306: 8 25'-------------110-00000000 -> 3 12'000000000000 307: 8 25'-------------110-000001-0 -> 4 12'000000000000 308: 8 25'---1-----------1-00000--0 -> 4 12'000000000000 309: 8 25'---1-------------10000--0 -> 4 12'000000000000 310: 8 25'-------------------100--0 -> 5 12'000000000000 311: 8 25'-------1-------1-00000--0 -> 6 12'000000000000 312: 8 25'-------1---------10000--0 -> 6 12'000000000000 313: 8 25'----1----------1-00000--0 -> 7 12'000000000000 314: 8 25'----1------------10000--0 -> 7 12'000000000000 315: 8 25'--------1000-000-00000--0 -> 8 12'000000000000 316: 8 25'---------100-000-00000--0 -> 8 12'000000000000 317: 8 25'----------10-000-00000--0 -> 8 12'000000000000 318: 8 25'-----------1-000-00000--0 -> 8 12'000000000000 319: 8 25'--------0000--00-00000--0 -> 8 12'000000000000 320: 8 25'------------0010-00000--0 -> 8 12'000000000000 321: 8 25'--------------------10--0 -> 8 12'000000000000 322: 8 25'---------------------1--0 -> 8 12'000000000000 323: 8 25'------------------------1 -> 8 12'000000000000 324: 8 25'--1------------1000000--0 -> 9 12'000000000000 325: 8 25'--1-------------010000--0 -> 9 12'000000000000 326: 8 25'--1------------1100000--0 -> 10 12'000000000000 327: 8 25'--1-------------110000--0 -> 10 12'000000000000 328: 8 25'-------------110-00000-10 -> 11 12'000000000000 329: 8 25'1--------------1-00000--0 -> 11 12'000000000000 330: 8 25'1----------------10000--0 -> 11 12'000000000000 331: 8 25'-1-------------1-00000--0 -> 12 12'000000000000 332: 8 25'-1---------------10000--0 -> 12 12'000000000000 333: 9 25'-----1---------1000000--0 -> 0 12'000001000000 334: 9 25'--------1000-100-00000--0 -> 0 12'000001000000 335: 9 25'---------100-100-00000--0 -> 0 12'000001000000 336: 9 25'----------10-100-00000--0 -> 0 12'000001000000 337: 9 25'-----------1-100-00000--0 -> 0 12'000001000000 338: 9 25'------------1010-00000--0 -> 0 12'000001000000 339: 9 25'-----1-----------10000--0 -> 0 12'000001000000 340: 9 25'------------------1000--0 -> 0 12'000001000000 341: 9 25'-----1---------1100000--0 -> 1 12'000001000000 342: 9 25'------1--------1-00000--0 -> 2 12'000001000000 343: 9 25'------1----------10000--0 -> 2 12'000001000000 344: 9 25'-------------110-00000000 -> 3 12'000001000000 345: 9 25'-------------110-000001-0 -> 4 12'000001000000 346: 9 25'---1-----------1-00000--0 -> 4 12'000001000000 347: 9 25'---1-------------10000--0 -> 4 12'000001000000 348: 9 25'-------------------100--0 -> 5 12'000001000000 349: 9 25'-------1-------1-00000--0 -> 6 12'000001000000 350: 9 25'-------1---------10000--0 -> 6 12'000001000000 351: 9 25'----1----------1-00000--0 -> 7 12'000001000000 352: 9 25'----1------------10000--0 -> 7 12'000001000000 353: 9 25'---------------------1--0 -> 8 12'000001000000 354: 9 25'--1------------1000000--0 -> 9 12'000001000000 355: 9 25'--------1000-000-00000--0 -> 9 12'000001000000 356: 9 25'---------100-000-00000--0 -> 9 12'000001000000 357: 9 25'----------10-000-00000--0 -> 9 12'000001000000 358: 9 25'-----------1-000-00000--0 -> 9 12'000001000000 359: 9 25'--------0000--00-00000--0 -> 9 12'000001000000 360: 9 25'------------0010-00000--0 -> 9 12'000001000000 361: 9 25'--1-------------010000--0 -> 9 12'000001000000 362: 9 25'--------------------10--0 -> 9 12'000001000000 363: 9 25'------------------------1 -> 9 12'000001000000 364: 9 25'--1------------1100000--0 -> 10 12'000001000000 365: 9 25'--1-------------110000--0 -> 10 12'000001000000 366: 9 25'-------------110-00000-10 -> 11 12'000001000000 367: 9 25'1--------------1-00000--0 -> 11 12'000001000000 368: 9 25'1----------------10000--0 -> 11 12'000001000000 369: 9 25'-1-------------1-00000--0 -> 12 12'000001000000 370: 9 25'-1---------------10000--0 -> 12 12'000001000000 371: 10 25'-----1---------1000000--0 -> 0 12'000000000010 372: 10 25'--------1000-100-00000--0 -> 0 12'000000000010 373: 10 25'---------100-100-00000--0 -> 0 12'000000000010 374: 10 25'----------10-100-00000--0 -> 0 12'000000000010 375: 10 25'-----------1-100-00000--0 -> 0 12'000000000010 376: 10 25'------------1010-00000--0 -> 0 12'000000000010 377: 10 25'-----1-----------10000--0 -> 0 12'000000000010 378: 10 25'------------------1000--0 -> 0 12'000000000010 379: 10 25'-----1---------1100000--0 -> 1 12'000000000010 380: 10 25'------1--------1-00000--0 -> 2 12'000000000010 381: 10 25'------1----------10000--0 -> 2 12'000000000010 382: 10 25'-------------110-00000000 -> 3 12'000000000010 383: 10 25'-------------110-000001-0 -> 4 12'000000000010 384: 10 25'---1-----------1-00000--0 -> 4 12'000000000010 385: 10 25'---1-------------10000--0 -> 4 12'000000000010 386: 10 25'-------------------100--0 -> 5 12'000000000010 387: 10 25'-------1-------1-00000--0 -> 6 12'000000000010 388: 10 25'-------1---------10000--0 -> 6 12'000000000010 389: 10 25'----1----------1-00000--0 -> 7 12'000000000010 390: 10 25'----1------------10000--0 -> 7 12'000000000010 391: 10 25'---------------------1--0 -> 8 12'000000000010 392: 10 25'--1------------1000000--0 -> 9 12'000000000010 393: 10 25'--1-------------010000--0 -> 9 12'000000000010 394: 10 25'--1------------1100000--0 -> 10 12'000000000010 395: 10 25'--------1000-000-00000--0 -> 10 12'000000000010 396: 10 25'---------100-000-00000--0 -> 10 12'000000000010 397: 10 25'----------10-000-00000--0 -> 10 12'000000000010 398: 10 25'-----------1-000-00000--0 -> 10 12'000000000010 399: 10 25'--------0000--00-00000--0 -> 10 12'000000000010 400: 10 25'------------0010-00000--0 -> 10 12'000000000010 401: 10 25'--1-------------110000--0 -> 10 12'000000000010 402: 10 25'--------------------10--0 -> 10 12'000000000010 403: 10 25'------------------------1 -> 10 12'000000000010 404: 10 25'-------------110-00000-10 -> 11 12'000000000010 405: 10 25'1--------------1-00000--0 -> 11 12'000000000010 406: 10 25'1----------------10000--0 -> 11 12'000000000010 407: 10 25'-1-------------1-00000--0 -> 12 12'000000000010 408: 10 25'-1---------------10000--0 -> 12 12'000000000010 409: 11 25'-----1---------1000000--0 -> 0 12'000100000000 410: 11 25'--------1000-100-00000--0 -> 0 12'000100000000 411: 11 25'---------100-100-00000--0 -> 0 12'000100000000 412: 11 25'----------10-100-00000--0 -> 0 12'000100000000 413: 11 25'-----------1-100-00000--0 -> 0 12'000100000000 414: 11 25'------------1010-00000--0 -> 0 12'000100000000 415: 11 25'-----1-----------10000--0 -> 0 12'000100000000 416: 11 25'------------------1000--0 -> 0 12'000100000000 417: 11 25'-----1---------1100000--0 -> 1 12'000100000000 418: 11 25'------1--------1-00000--0 -> 2 12'000100000000 419: 11 25'------1----------10000--0 -> 2 12'000100000000 420: 11 25'-------------110-00000000 -> 3 12'000100000000 421: 11 25'-------------110-000001-0 -> 4 12'000100000000 422: 11 25'---1-----------1-00000--0 -> 4 12'000100000000 423: 11 25'---1-------------10000--0 -> 4 12'000100000000 424: 11 25'-------------------100--0 -> 5 12'000100000000 425: 11 25'-------1-------1-00000--0 -> 6 12'000100000000 426: 11 25'-------1---------10000--0 -> 6 12'000100000000 427: 11 25'----1----------1-00000--0 -> 7 12'000100000000 428: 11 25'----1------------10000--0 -> 7 12'000100000000 429: 11 25'---------------------1--0 -> 8 12'000100000000 430: 11 25'--1------------1000000--0 -> 9 12'000100000000 431: 11 25'--1-------------010000--0 -> 9 12'000100000000 432: 11 25'--1------------1100000--0 -> 10 12'000100000000 433: 11 25'--1-------------110000--0 -> 10 12'000100000000 434: 11 25'-------------110-00000-10 -> 11 12'000100000000 435: 11 25'--------1000-000-00000--0 -> 11 12'000100000000 436: 11 25'---------100-000-00000--0 -> 11 12'000100000000 437: 11 25'----------10-000-00000--0 -> 11 12'000100000000 438: 11 25'-----------1-000-00000--0 -> 11 12'000100000000 439: 11 25'--------0000--00-00000--0 -> 11 12'000100000000 440: 11 25'------------0010-00000--0 -> 11 12'000100000000 441: 11 25'1--------------1-00000--0 -> 11 12'000100000000 442: 11 25'1----------------10000--0 -> 11 12'000100000000 443: 11 25'--------------------10--0 -> 11 12'000100000000 444: 11 25'------------------------1 -> 11 12'000100000000 445: 11 25'-1-------------1-00000--0 -> 12 12'000100000000 446: 11 25'-1---------------10000--0 -> 12 12'000100000000 447: 12 25'-----1---------1000000--0 -> 0 12'000000010000 448: 12 25'--------1000-100-00000--0 -> 0 12'000000010000 449: 12 25'---------100-100-00000--0 -> 0 12'000000010000 450: 12 25'----------10-100-00000--0 -> 0 12'000000010000 451: 12 25'-----------1-100-00000--0 -> 0 12'000000010000 452: 12 25'------------1010-00000--0 -> 0 12'000000010000 453: 12 25'-----1-----------10000--0 -> 0 12'000000010000 454: 12 25'------------------1000--0 -> 0 12'000000010000 455: 12 25'-----1---------1100000--0 -> 1 12'000000010000 456: 12 25'------1--------1-00000--0 -> 2 12'000000010000 457: 12 25'------1----------10000--0 -> 2 12'000000010000 458: 12 25'-------------110-00000000 -> 3 12'000000010000 459: 12 25'-------------110-000001-0 -> 4 12'000000010000 460: 12 25'---1-----------1-00000--0 -> 4 12'000000010000 461: 12 25'---1-------------10000--0 -> 4 12'000000010000 462: 12 25'-------------------100--0 -> 5 12'000000010000 463: 12 25'-------1-------1-00000--0 -> 6 12'000000010000 464: 12 25'-------1---------10000--0 -> 6 12'000000010000 465: 12 25'----1----------1-00000--0 -> 7 12'000000010000 466: 12 25'----1------------10000--0 -> 7 12'000000010000 467: 12 25'---------------------1--0 -> 8 12'000000010000 468: 12 25'--1------------1000000--0 -> 9 12'000000010000 469: 12 25'--1-------------010000--0 -> 9 12'000000010000 470: 12 25'--1------------1100000--0 -> 10 12'000000010000 471: 12 25'--1-------------110000--0 -> 10 12'000000010000 472: 12 25'-------------110-00000-10 -> 11 12'000000010000 473: 12 25'1--------------1-00000--0 -> 11 12'000000010000 474: 12 25'1----------------10000--0 -> 11 12'000000010000 475: 12 25'--------1000-000-00000--0 -> 12 12'000000010000 476: 12 25'---------100-000-00000--0 -> 12 12'000000010000 477: 12 25'----------10-000-00000--0 -> 12 12'000000010000 478: 12 25'-----------1-000-00000--0 -> 12 12'000000010000 479: 12 25'--------0000--00-00000--0 -> 12 12'000000010000 480: 12 25'------------0010-00000--0 -> 12 12'000000010000 481: 12 25'-1-------------1-00000--0 -> 12 12'000000010000 482: 12 25'-1---------------10000--0 -> 12 12'000000010000 483: 12 25'--------------------10--0 -> 12 12'000000010000 484: 12 25'------------------------1 -> 12 12'000000010000 ------------------------------------- FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcA$3707' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Riscado_V.ctrlUnit.aluSrcA$3707 (\Riscado_V.ctrlUnit.aluSrcA): Number of input signals: 14 Number of output signals: 3 Number of state bits: 2 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y 2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y 3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y 4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y 5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y 6: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y 7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y 8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y 9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y 10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y 11: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y 12: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y 13: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y Output signals: 0: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:123$190_Y 1: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:122$189_Y 2: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:121$188_Y State encoding: 0: 2'-1 <RESET STATE> 1: 2'1- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 14'---1-000000000 -> 0 3'100 1: 0 14'---0--00000000 -> 0 3'100 2: 0 14'----0010000000 -> 0 3'100 3: 0 14'-----110000000 -> 0 3'100 4: 0 14'-------1000000 -> 0 3'100 5: 0 14'--------100000 -> 0 3'100 6: 0 14'----------1000 -> 0 3'100 7: 0 14'-----------100 -> 0 3'100 8: 0 14'------------10 -> 0 3'100 9: 0 14'-------------1 -> 0 3'100 10: 0 14'---1-100000000 -> 1 3'100 11: 0 14'----1010000000 -> 1 3'100 12: 0 14'---------10000 -> 1 3'100 13: 1 14'1000-100000000 -> 0 3'001 14: 1 14'-100-100000000 -> 0 3'001 15: 1 14'--10-100000000 -> 0 3'001 16: 1 14'------------10 -> 0 3'001 17: 1 14'-------------1 -> 0 3'001 18: 1 14'1000-000000000 -> 1 3'001 19: 1 14'-100-000000000 -> 1 3'001 20: 1 14'--10-000000000 -> 1 3'001 21: 1 14'0000--00000000 -> 1 3'001 22: 1 14'---1--00000000 -> 1 3'001 23: 1 14'------10000000 -> 1 3'001 24: 1 14'-------1000000 -> 1 3'001 25: 1 14'--------100000 -> 1 3'001 26: 1 14'---------10000 -> 1 3'001 27: 1 14'----------1000 -> 1 3'001 28: 1 14'-----------100 -> 1 3'001 ------------------------------------- FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcB$3712' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Riscado_V.ctrlUnit.aluSrcB$3712 (\Riscado_V.ctrlUnit.aluSrcB): Number of input signals: 14 Number of output signals: 6 Number of state bits: 6 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y 2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y 3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y 4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y 5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y 6: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y 7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y 8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y 9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y 10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y 11: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y 12: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y 13: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y Output signals: 0: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$199_Y 1: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$198_Y 2: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$197_Y 3: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$196_Y 4: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:129$195_Y 5: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:128$194_Y State encoding: 0: 6'-----1 <RESET STATE> 1: 6'----1- 2: 6'---1-- 3: 6'--1--- 4: 6'-1---- 5: 6'1----- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 14'1000-000000000 -> 0 6'100000 1: 0 14'-100-000000000 -> 0 6'100000 2: 0 14'--10-000000000 -> 0 6'100000 3: 0 14'---1-000000000 -> 0 6'100000 4: 0 14'0000--00000000 -> 0 6'100000 5: 0 14'----0010000000 -> 0 6'100000 6: 0 14'-----110000000 -> 0 6'100000 7: 0 14'-------1000000 -> 0 6'100000 8: 0 14'-----------100 -> 0 6'100000 9: 0 14'------------10 -> 0 6'100000 10: 0 14'-------------1 -> 0 6'100000 11: 0 14'---------10000 -> 1 6'100000 12: 0 14'----------1000 -> 1 6'100000 13: 0 14'1000-100000000 -> 2 6'100000 14: 0 14'-100-100000000 -> 3 6'100000 15: 0 14'--10-100000000 -> 3 6'100000 16: 0 14'--------100000 -> 3 6'100000 17: 0 14'---1-100000000 -> 4 6'100000 18: 0 14'----1010000000 -> 5 6'100000 19: 1 14'-------1000000 -> 0 6'010000 20: 1 14'------------10 -> 0 6'010000 21: 1 14'-------------1 -> 0 6'010000 22: 1 14'1000-000000000 -> 1 6'010000 23: 1 14'-100-000000000 -> 1 6'010000 24: 1 14'--10-000000000 -> 1 6'010000 25: 1 14'---1-000000000 -> 1 6'010000 26: 1 14'0000--00000000 -> 1 6'010000 27: 1 14'----0010000000 -> 1 6'010000 28: 1 14'-----110000000 -> 1 6'010000 29: 1 14'---------10000 -> 1 6'010000 30: 1 14'----------1000 -> 1 6'010000 31: 1 14'-----------100 -> 1 6'010000 32: 1 14'1000-100000000 -> 2 6'010000 33: 1 14'-100-100000000 -> 3 6'010000 34: 1 14'--10-100000000 -> 3 6'010000 35: 1 14'--------100000 -> 3 6'010000 36: 1 14'---1-100000000 -> 4 6'010000 37: 1 14'----1010000000 -> 5 6'010000 38: 2 14'-------1000000 -> 0 6'000001 39: 2 14'------------10 -> 0 6'000001 40: 2 14'-------------1 -> 0 6'000001 41: 2 14'---------10000 -> 1 6'000001 42: 2 14'----------1000 -> 1 6'000001 43: 2 14'-100-000000000 -> 2 6'000001 44: 2 14'--10-000000000 -> 2 6'000001 45: 2 14'---1-000000000 -> 2 6'000001 46: 2 14'-000--00000000 -> 2 6'000001 47: 2 14'----0010000000 -> 2 6'000001 48: 2 14'-----110000000 -> 2 6'000001 49: 2 14'-----------100 -> 2 6'000001 50: 2 14'-100-100000000 -> 3 6'000001 51: 2 14'--10-100000000 -> 3 6'000001 52: 2 14'--------100000 -> 3 6'000001 53: 2 14'---1-100000000 -> 4 6'000001 54: 2 14'----1010000000 -> 5 6'000001 55: 3 14'-------1000000 -> 0 6'001000 56: 3 14'------------10 -> 0 6'001000 57: 3 14'-------------1 -> 0 6'001000 58: 3 14'---------10000 -> 1 6'001000 59: 3 14'----------1000 -> 1 6'001000 60: 3 14'1000-100000000 -> 2 6'001000 61: 3 14'1000-000000000 -> 3 6'001000 62: 3 14'---1-000000000 -> 3 6'001000 63: 3 14'0000--00000000 -> 3 6'001000 64: 3 14'-100--00000000 -> 3 6'001000 65: 3 14'--10--00000000 -> 3 6'001000 66: 3 14'----0010000000 -> 3 6'001000 67: 3 14'-----110000000 -> 3 6'001000 68: 3 14'--------100000 -> 3 6'001000 69: 3 14'-----------100 -> 3 6'001000 70: 3 14'---1-100000000 -> 4 6'001000 71: 3 14'----1010000000 -> 5 6'001000 72: 4 14'-------1000000 -> 0 6'000010 73: 4 14'------------10 -> 0 6'000010 74: 4 14'-------------1 -> 0 6'000010 75: 4 14'---------10000 -> 1 6'000010 76: 4 14'----------1000 -> 1 6'000010 77: 4 14'1000-100000000 -> 2 6'000010 78: 4 14'-100-100000000 -> 3 6'000010 79: 4 14'--10-100000000 -> 3 6'000010 80: 4 14'--------100000 -> 3 6'000010 81: 4 14'1000-000000000 -> 4 6'000010 82: 4 14'-100-000000000 -> 4 6'000010 83: 4 14'--10-000000000 -> 4 6'000010 84: 4 14'0000--00000000 -> 4 6'000010 85: 4 14'---1--00000000 -> 4 6'000010 86: 4 14'----0010000000 -> 4 6'000010 87: 4 14'-----110000000 -> 4 6'000010 88: 4 14'-----------100 -> 4 6'000010 89: 4 14'----1010000000 -> 5 6'000010 90: 5 14'-------1000000 -> 0 6'000100 91: 5 14'------------10 -> 0 6'000100 92: 5 14'-------------1 -> 0 6'000100 93: 5 14'---------10000 -> 1 6'000100 94: 5 14'----------1000 -> 1 6'000100 95: 5 14'1000-100000000 -> 2 6'000100 96: 5 14'-100-100000000 -> 3 6'000100 97: 5 14'--10-100000000 -> 3 6'000100 98: 5 14'--------100000 -> 3 6'000100 99: 5 14'---1-100000000 -> 4 6'000100 100: 5 14'1000-000000000 -> 5 6'000100 101: 5 14'-100-000000000 -> 5 6'000100 102: 5 14'--10-000000000 -> 5 6'000100 103: 5 14'---1-000000000 -> 5 6'000100 104: 5 14'0000--00000000 -> 5 6'000100 105: 5 14'------10000000 -> 5 6'000100 106: 5 14'-----------100 -> 5 6'000100 ------------------------------------- FSM `$fsm$\Riscado_V.ctrlUnit.readLen$3720' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Riscado_V.ctrlUnit.readLen$3720 (\Riscado_V.ctrlUnit.readLen): Number of input signals: 17 Number of output signals: 2 Number of state bits: 3 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y 2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y 3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y 4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y 5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y 6: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y 7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y 8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y 9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y 10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y 11: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y 12: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y 13: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y 14: $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP 15: $auto$opt_reduce.cc:137:opt_pmux$3657 16: $auto$opt_reduce.cc:137:opt_pmux$3659 Output signals: 0: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:110$233_Y 1: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:111$234_Y State encoding: 0: 3'-1- 1: 3'--1 <RESET STATE> 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 17'----1000000000000 -> 0 2'01 1: 0 17'000-1001000000000 -> 0 2'01 2: 0 17'1---1001000000000 -> 0 2'01 3: 0 17'---1000-000000000 -> 0 2'01 4: 0 17'----100-100000000 -> 0 2'01 5: 0 17'---0000--00000000 -> 0 2'01 6: 0 17'-----10--00000000 -> 0 2'01 7: 0 17'------1--00000000 -> 0 2'01 8: 0 17'---------10000000 -> 0 2'01 9: 0 17'----------1000000 -> 0 2'01 10: 0 17'-----------100000 -> 0 2'01 11: 0 17'------------10000 -> 0 2'01 12: 0 17'-------------1000 -> 0 2'01 13: 0 17'--------------100 -> 0 2'01 14: 0 17'--1-1001000000000 -> 1 2'01 15: 0 17'---1000-100000000 -> 1 2'01 16: 0 17'---------------10 -> 1 2'01 17: 0 17'----------------1 -> 1 2'01 18: 0 17'-1--1001000000000 -> 2 2'01 19: 1 17'1---1001000000000 -> 0 2'00 20: 1 17'----1000000000000 -> 1 2'00 21: 1 17'000-1001000000000 -> 1 2'00 22: 1 17'--1-1001000000000 -> 1 2'00 23: 1 17'----100-100000000 -> 1 2'00 24: 1 17'----000--00000000 -> 1 2'00 25: 1 17'-----10--00000000 -> 1 2'00 26: 1 17'------1--00000000 -> 1 2'00 27: 1 17'---------10000000 -> 1 2'00 28: 1 17'----------1000000 -> 1 2'00 29: 1 17'-----------100000 -> 1 2'00 30: 1 17'------------10000 -> 1 2'00 31: 1 17'-------------1000 -> 1 2'00 32: 1 17'--------------100 -> 1 2'00 33: 1 17'---------------10 -> 1 2'00 34: 1 17'----------------1 -> 1 2'00 35: 1 17'-1--1001000000000 -> 2 2'00 36: 2 17'1---1001000000000 -> 0 2'10 37: 2 17'--1-1001000000000 -> 1 2'10 38: 2 17'---1000-100000000 -> 1 2'10 39: 2 17'---------------10 -> 1 2'10 40: 2 17'----------------1 -> 1 2'10 41: 2 17'----1000000000000 -> 2 2'10 42: 2 17'000-1001000000000 -> 2 2'10 43: 2 17'-1--1001000000000 -> 2 2'10 44: 2 17'---1000-000000000 -> 2 2'10 45: 2 17'----100-100000000 -> 2 2'10 46: 2 17'---0000--00000000 -> 2 2'10 47: 2 17'-----10--00000000 -> 2 2'10 48: 2 17'------1--00000000 -> 2 2'10 49: 2 17'---------10000000 -> 2 2'10 50: 2 17'----------1000000 -> 2 2'10 51: 2 17'-----------100000 -> 2 2'10 52: 2 17'------------10000 -> 2 2'10 53: 2 17'-------------1000 -> 2 2'10 54: 2 17'--------------100 -> 2 2'10 ------------------------------------- FSM `$fsm$\Riscado_V.ctrlUnit.regDataSrc$3724' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Riscado_V.ctrlUnit.regDataSrc$3724 (\Riscado_V.ctrlUnit.regDataSrc): Number of input signals: 13 Number of output signals: 3 Number of state bits: 3 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y 2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y 3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y 4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y 5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y 6: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y 7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y 8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y 9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y 10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y 11: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y 12: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y Output signals: 0: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:80$184_Y 1: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:79$183_Y 2: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:78$182_Y State encoding: 0: 3'--1 1: 3'-1- 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 13'1000000000000 -> 0 3'100 1: 0 13'-100000000000 -> 0 3'100 2: 0 13'--10000000000 -> 0 3'100 3: 0 13'---1000000000 -> 0 3'100 4: 0 13'0000-00000000 -> 0 3'100 5: 0 13'-----10000000 -> 0 3'100 6: 0 13'------1000000 -> 0 3'100 7: 0 13'-------100000 -> 0 3'100 8: 0 13'--------10000 -> 0 3'100 9: 0 13'---------1000 -> 0 3'100 10: 0 13'----------100 -> 0 3'100 11: 0 13'-----------10 -> 0 3'100 12: 0 13'------------1 -> 0 3'100 13: 0 13'--10100000000 -> 1 3'100 14: 0 13'---1100000000 -> 1 3'100 15: 0 13'1000100000000 -> 2 3'100 16: 0 13'-100100000000 -> 2 3'100 17: 1 13'-----------10 -> 0 3'001 18: 1 13'1000000000000 -> 1 3'001 19: 1 13'-100000000000 -> 1 3'001 20: 1 13'0000-00000000 -> 1 3'001 21: 1 13'--10-00000000 -> 1 3'001 22: 1 13'---1-00000000 -> 1 3'001 23: 1 13'-----10000000 -> 1 3'001 24: 1 13'------1000000 -> 1 3'001 25: 1 13'-------100000 -> 1 3'001 26: 1 13'--------10000 -> 1 3'001 27: 1 13'---------1000 -> 1 3'001 28: 1 13'----------100 -> 1 3'001 29: 1 13'------------1 -> 1 3'001 30: 1 13'1000100000000 -> 2 3'001 31: 1 13'-100100000000 -> 2 3'001 32: 2 13'-----------10 -> 0 3'010 33: 2 13'--10100000000 -> 1 3'010 34: 2 13'---1100000000 -> 1 3'010 35: 2 13'--10000000000 -> 2 3'010 36: 2 13'---1000000000 -> 2 3'010 37: 2 13'--00-00000000 -> 2 3'010 38: 2 13'-----10000000 -> 2 3'010 39: 2 13'------1000000 -> 2 3'010 40: 2 13'-------100000 -> 2 3'010 41: 2 13'--------10000 -> 2 3'010 42: 2 13'---------1000 -> 2 3'010 43: 2 13'----------100 -> 2 3'010 44: 2 13'------------1 -> 2 3'010 ------------------------------------- FSM `$fsm$\Riscado_V.ctrlUnit.state$3729' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Riscado_V.ctrlUnit.state$3729 (\Riscado_V.ctrlUnit.state): Number of input signals: 11 Number of output signals: 6 Number of state bits: 6 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y 2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y 3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y 4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y 5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y 6: $flatten\Riscado_V.\ctrlUnit.$or$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:175$44_Y 7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y 8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y 9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y 10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y Output signals: 0: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y 1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y 2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y 3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y 4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y 5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:307$60_Y State encoding: 0: 6'-----1 <RESET STATE> 1: 6'----1- 2: 6'---1-- 3: 6'--1--- 4: 6'-1---- 5: 6'1----- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 11'----------1 -> 0 6'000001 1: 0 11'----------0 -> 3 6'000001 2: 1 11'0000-000000 -> 0 6'010000 3: 1 11'-100-000000 -> 0 6'010000 4: 1 11'--10-000000 -> 0 6'010000 5: 1 11'---1-000000 -> 0 6'010000 6: 1 11'-----100000 -> 0 6'010000 7: 1 11'------10000 -> 0 6'010000 8: 1 11'-------1000 -> 0 6'010000 9: 1 11'--------100 -> 0 6'010000 10: 1 11'---------10 -> 0 6'010000 11: 1 11'----------1 -> 0 6'010000 12: 1 11'1000-000000 -> 4 6'010000 13: 2 11'0000-000000 -> 0 6'000100 14: 2 11'------10000 -> 0 6'000100 15: 2 11'-------1000 -> 0 6'000100 16: 2 11'--------100 -> 0 6'000100 17: 2 11'---------10 -> 0 6'000100 18: 2 11'----------1 -> 0 6'000100 19: 2 11'1000-000000 -> 5 6'000100 20: 2 11'-100-000000 -> 5 6'000100 21: 2 11'--10-000000 -> 5 6'000100 22: 2 11'---1-000000 -> 5 6'000100 23: 2 11'-----100000 -> 5 6'000100 24: 3 11'----------1 -> 0 6'000010 25: 3 11'----------0 -> 2 6'000010 26: 4 11'-000-000000 -> 0 6'100000 27: 4 11'--10-000000 -> 0 6'100000 28: 4 11'---1-000000 -> 0 6'100000 29: 4 11'------10000 -> 0 6'100000 30: 4 11'-------1000 -> 0 6'100000 31: 4 11'--------100 -> 0 6'100000 32: 4 11'---------10 -> 0 6'100000 33: 4 11'----------1 -> 0 6'100000 34: 4 11'-100-000000 -> 4 6'100000 35: 4 11'-----100000 -> 4 6'100000 36: 5 11'0000-000000 -> 0 6'001000 37: 5 11'--10-000000 -> 0 6'001000 38: 5 11'---1-000000 -> 0 6'001000 39: 5 11'----0100000 -> 0 6'001000 40: 5 11'------10000 -> 0 6'001000 41: 5 11'-------1000 -> 0 6'001000 42: 5 11'--------100 -> 0 6'001000 43: 5 11'---------10 -> 0 6'001000 44: 5 11'----------1 -> 0 6'001000 45: 5 11'1000-000000 -> 1 6'001000 46: 5 11'-100-000000 -> 1 6'001000 47: 5 11'----1100000 -> 1 6'001000 ------------------------------------- FSM `$fsm$\Riscado_V.ctrlUnit.writeLen$3737' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Riscado_V.ctrlUnit.writeLen$3737 (\Riscado_V.ctrlUnit.writeLen): Number of input signals: 18 Number of output signals: 2 Number of state bits: 3 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y 2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y 3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y 4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y 5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y 6: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y 7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y 8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y 9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y 10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y 11: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y 12: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y 13: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y 14: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y 15: $flatten\Riscado_V.\ctrlUnit.$procmux$2766_CMP 16: $flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP 17: $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP Output signals: 0: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:88$229_Y 1: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:89$230_Y State encoding: 0: 3'-1- 1: 3'--1 <RESET STATE> 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 18'---100000000000000 -> 0 2'01 1: 0 18'000100010000000000 -> 0 2'01 2: 0 18'--1100010000000000 -> 0 2'01 3: 0 18'---1000-1000000000 -> 0 2'01 4: 0 18'---1000--100000000 -> 0 2'01 5: 0 18'---0000---00000000 -> 0 2'01 6: 0 18'----100---00000000 -> 0 2'01 7: 0 18'-----10---00000000 -> 0 2'01 8: 0 18'------1---00000000 -> 0 2'01 9: 0 18'----------10000000 -> 0 2'01 10: 0 18'-----------1000000 -> 0 2'01 11: 0 18'------------100000 -> 0 2'01 12: 0 18'-------------10000 -> 0 2'01 13: 0 18'--------------1000 -> 0 2'01 14: 0 18'---------------100 -> 0 2'01 15: 0 18'1--100010000000000 -> 1 2'01 16: 0 18'----------------10 -> 1 2'01 17: 0 18'-----------------1 -> 1 2'01 18: 0 18'-1-100010000000000 -> 2 2'01 19: 1 18'--1100010000000000 -> 0 2'00 20: 1 18'---100000000000000 -> 1 2'00 21: 1 18'000100010000000000 -> 1 2'00 22: 1 18'1--100010000000000 -> 1 2'00 23: 1 18'---1000-1000000000 -> 1 2'00 24: 1 18'---1000--100000000 -> 1 2'00 25: 1 18'---0000---00000000 -> 1 2'00 26: 1 18'----100---00000000 -> 1 2'00 27: 1 18'-----10---00000000 -> 1 2'00 28: 1 18'------1---00000000 -> 1 2'00 29: 1 18'----------10000000 -> 1 2'00 30: 1 18'-----------1000000 -> 1 2'00 31: 1 18'------------100000 -> 1 2'00 32: 1 18'-------------10000 -> 1 2'00 33: 1 18'--------------1000 -> 1 2'00 34: 1 18'---------------100 -> 1 2'00 35: 1 18'----------------10 -> 1 2'00 36: 1 18'-----------------1 -> 1 2'00 37: 1 18'-1-100010000000000 -> 2 2'00 38: 2 18'--1100010000000000 -> 0 2'10 39: 2 18'1--100010000000000 -> 1 2'10 40: 2 18'----------------10 -> 1 2'10 41: 2 18'-----------------1 -> 1 2'10 42: 2 18'---100000000000000 -> 2 2'10 43: 2 18'000100010000000000 -> 2 2'10 44: 2 18'-1-100010000000000 -> 2 2'10 45: 2 18'---1000-1000000000 -> 2 2'10 46: 2 18'---1000--100000000 -> 2 2'10 47: 2 18'---0000---00000000 -> 2 2'10 48: 2 18'----100---00000000 -> 2 2'10 49: 2 18'-----10---00000000 -> 2 2'10 50: 2 18'------1---00000000 -> 2 2'10 51: 2 18'----------10000000 -> 2 2'10 52: 2 18'-----------1000000 -> 2 2'10 53: 2 18'------------100000 -> 2 2'10 54: 2 18'-------------10000 -> 2 2'10 55: 2 18'--------------1000 -> 2 2'10 56: 2 18'---------------100 -> 2 2'10 ------------------------------------- 17.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$3680' from module `\processorci_top'. Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3687' from module `\processorci_top'. Mapping FSM `$fsm$\Riscado_V.ctrlUnit.aluOperation$3693' from module `\processorci_top'. Mapping FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcA$3707' from module `\processorci_top'. Mapping FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcB$3712' from module `\processorci_top'. Mapping FSM `$fsm$\Riscado_V.ctrlUnit.readLen$3720' from module `\processorci_top'. Mapping FSM `$fsm$\Riscado_V.ctrlUnit.regDataSrc$3724' from module `\processorci_top'. Mapping FSM `$fsm$\Riscado_V.ctrlUnit.state$3729' from module `\processorci_top'. Mapping FSM `$fsm$\Riscado_V.ctrlUnit.writeLen$3737' from module `\processorci_top'. 17.13. Executing OPT pass (performing simple optimizations). 17.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~65 debug messages> 17.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~840 debug messages> Removed a total of 280 cells. 17.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~140 debug messages> 17.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 17.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\Riscado_V.\pc.$procdff$3568 ($dff) from module processorci_top (D = $flatten\Riscado_V.\pc.$procmux$2539_Y, Q = \Riscado_V.pc.pc, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$5223 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\pc.$procmux$2539_Y, Q = \Riscado_V.pc.pc). Adding EN signal on $flatten\Riscado_V.\pc.$procdff$3567 ($dff) from module processorci_top (D = $flatten\Riscado_V.\pc.$procmux$2547_Y, Q = \Riscado_V.pc.prevPc). Adding EN signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3583 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$2787_Y, Q = \Riscado_V.ctrlUnit.branchTestTrue). Adding SRST signal on $auto$ff.cc:266:slice$5234 ($dffe) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$2784_Y, Q = \Riscado_V.ctrlUnit.branchTestTrue, rval = 1'0). Adding SRST signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3581 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$2907_Y, Q = \Riscado_V.ctrlUnit.readSignExtend, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$5256 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$2883_Y, Q = \Riscado_V.ctrlUnit.readSignExtend). Adding SRST signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3575 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3240_Y, Q = \Riscado_V.ctrlUnit.pcWriteEnable, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$5288 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3234_Y, Q = \Riscado_V.ctrlUnit.pcWriteEnable). Adding SRST signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3574 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3287_Y, Q = \Riscado_V.ctrlUnit.regWriteEnable, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$5310 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3284_Y, Q = \Riscado_V.ctrlUnit.regWriteEnable). Adding SRST signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3572 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3347_Y, Q = \Riscado_V.ctrlUnit.incrementPc, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$5326 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3347_Y, Q = \Riscado_V.ctrlUnit.incrementPc). Adding SRST signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3571 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3399_Y, Q = \Riscado_V.ctrlUnit.addressIsPc, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$5330 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3375_Y, Q = \Riscado_V.ctrlUnit.addressIsPc). Adding EN signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3570 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3411_Y, Q = \Riscado_V.ctrlUnit.irWriteEnable). Adding SRST signal on $auto$ff.cc:266:slice$5364 ($dffe) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3408_Y, Q = \Riscado_V.ctrlUnit.irWriteEnable, rval = 1'1). Adding SRST signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3569 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3455_Y, Q = \Riscado_V.ctrlUnit.writeEnable, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$5372 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3420_Y, Q = \Riscado_V.ctrlUnit.writeEnable). Adding EN signal on $flatten\Riscado_V.$procdff$3563 ($dff) from module processorci_top (D = \Riscado_V.lsReadDataOut, Q = \Riscado_V.ir). Adding EN signal on $flatten\ResetBootSystem.$procdff$3562 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$3561 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$3504 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1505_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1499_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1490_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1481_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1472_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1463_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1445_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1454_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$5419 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$5419 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1499_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1490_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1481_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1472_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1463_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1445_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1454_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$3502 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1421_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$5424 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1421_Y, Q = \Controller.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$3501 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1410_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$5430 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1135_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$3500 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$3499 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1399_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$5435 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1399_Y, Q = \Controller.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3498 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1388_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$5441 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3497 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1365_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1356_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1347_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1338_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1329_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1320_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1302_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1311_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$5443 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3495 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1284_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$5447 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1175_Y, Q = \Controller.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3494 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1279_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$5451 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3493 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1271_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$5453 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1186_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3491 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3490 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$3489 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1248_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$5459 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$995_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr). Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$3488 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$992_DATA, Q = \Controller.Uart.TX_FIFO.read_data). Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$3484 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1243_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$5466 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1011_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr). Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$3489 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1248_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$5468 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$995_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr). Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$3488 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$992_DATA, Q = \Controller.Uart.RX_FIFO.read_data). Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$3484 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1243_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$5475 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1011_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3552 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2419_Y, Q = \Controller.Uart.state_read, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$5477 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2419_Y, Q = \Controller.Uart.state_read). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3551 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2444_Y, Q = \Controller.Uart.counter_read, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$5481 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2444_Y, Q = \Controller.Uart.counter_read). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3550 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2408_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3549 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2459_Y, Q = \Controller.Uart.read_data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$5498 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2457_Y, Q = \Controller.Uart.read_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3548 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2397_Y, Q = \Controller.Uart.read_response, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3547 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2341_Y, Q = \Controller.Uart.state_write, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$5505 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2341_Y, Q = \Controller.Uart.state_write). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3546 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2363_Y, Q = \Controller.Uart.counter_write, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$5509 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2363_Y, Q = \Controller.Uart.counter_write). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3545 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2377_Y, Q = \Controller.Uart.write_data_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$5519 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2377_Y, Q = \Controller.Uart.write_data_buffer). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3544 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2391_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$5529 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3543 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2323_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3542 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2333_Y, Q = \Controller.Uart.write_response, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3541 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2314_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$5543 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3540 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2309_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3538 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2304_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$5546 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3537 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2280_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$3536 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2288_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3535 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1827_Y, Q = \Controller.Interpreter.temp_buffer). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3534 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1870_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$5563 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1870_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]). Adding EN signal on $auto$ff.cc:266:slice$5563 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1870_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3533 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1880_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$5578 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1880_Y, Q = \Controller.Interpreter.timeout_counter). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3532 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3531 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1921_Y, Q = \Controller.Interpreter.read_buffer). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3530 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1949_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$5594 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3529 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1974_Y, Q = \Controller.Interpreter.num_of_positions). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3528 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1996_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$5605 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3527 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2002_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$5607 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2002_Y, Q = \Controller.Interpreter.return_state). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3526 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2026_Y, Q = \Controller.Interpreter.memory_page_number). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3525 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2034_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$5622 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2034_Y, Q = \Controller.Interpreter.memory_mux_selector). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3524 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2074_Y, Q = \Controller.Interpreter.end_position, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$5626 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2074_Y, Q = \Controller.Interpreter.end_position). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3522 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2116_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$5630 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2116_Y, Q = \Controller.Interpreter.bus_mode). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3521 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1655_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3520 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2127_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3519 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1760_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3518 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2137_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$5643 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2137_Y, Q = \Controller.Interpreter.core_clk_enable). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3517 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3516 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1779_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3515 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1802_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3514 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1701_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3513 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1712_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3512 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2213_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$5660 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2213_Y, Q = \Controller.Interpreter.counter). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3511 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2237_Y, Q = \Controller.Interpreter.write_data). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3510 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1679_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3509 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2263_Y, Q = \Controller.Interpreter.address). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3508 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1555_Y, Q = \Controller.Interpreter.state, rval = 8'00000000). Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$3505 ($dff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1529_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$5682 ($sdff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1529_Y, Q = \Controller.ClkDivider.pulse_counter). Adding SRST signal on $flatten\Controller.$procdff$3559 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2480_Y, Q = \Controller.finish_execution, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$5690 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2480_Y, Q = \Controller.finish_execution). Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top. 17.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 175 unused cells and 534 unused wires. <suppressed ~176 debug messages> 17.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~38 debug messages> 17.13.9. Rerunning OPT passes. (Maybe there is more to do..) 17.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~113 debug messages> 17.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$5449: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] } Optimizing cells in module \processorci_top. Performed a total of 1 changes. 17.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~153 debug messages> Removed a total of 51 cells. 17.13.13. Executing OPT_DFF pass (perform DFF optimizations). 17.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 52 unused wires. <suppressed ~2 debug messages> 17.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.13.16. Rerunning OPT passes. (Maybe there is more to do..) 17.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~114 debug messages> 17.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 17.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.13.20. Executing OPT_DFF pass (perform DFF optimizations). 17.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 17.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.13.23. Finished OPT passes. (There is nothing left to do.) 17.14. Executing WREDUCE pass (reducing word size of cells). Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$3585 (Controller.Data_Memory.memory). Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$802 (Controller.Data_Memory.memory). Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3585 (Controller.Memory.memory). Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$802 (Controller.Memory.memory). Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3584 (Controller.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$992 (Controller.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3584 (Controller.Uart.TX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$992 (Controller.Uart.TX_FIFO.memory). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$115 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$116 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$117 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$118 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$119 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$120 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$121 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$122 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$123 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$124 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$125 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$126 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$127 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$128 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$129 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$130 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$131 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$132 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$133 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$134 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$135 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$136 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$137 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$138 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$139 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$140 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$141 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$142 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$143 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$144 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$145 (Riscado_V.registerFile.registers). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$146 (Riscado_V.registerFile.registers). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3775 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3761 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3750 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5695 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5685 ($ne). Removed top 3 bits (of 18) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5169 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4949 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1093 ($gt). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1050 ($eq). Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1054 ($add). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1057 ($add). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1066 ($lt). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1071 ($eq). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1073 ($ge). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1556_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1557_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1559 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1561_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1562_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1563_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1564_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1565_CMP0 ($eq). Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1567 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1569_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1570_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1572 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1574_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1575_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1579_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1580_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1581_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1583 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1585_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1586_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1587_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1589 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1591_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1593 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1595_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1596_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1597_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1598_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1599_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1600_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1601_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1603 ($mux). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1605_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1607 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1609_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1610_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1612 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1614_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1615_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1618_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1617 ($pmux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1619_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1620_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1621_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1622_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1623_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1624_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1625_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1626_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1627_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1628_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1629_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1630_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1631_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1632_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1633_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1634_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1635_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1636_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1637_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1638_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1639_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1640_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1641_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1643 ($mux). Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1645_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1647 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1681_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1682_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1683_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1716_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1871_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1872_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1873_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1916_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2042_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2075_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2076_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2149_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2150_CMP0 ($eq). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$1024 ($lt). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1029 ($lt). Removed top 1 bits (of 7) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5295 ($ne). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2328_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2334_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2335_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2347_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2349 ($mux). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2398_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2399_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2413_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2421_CMP0 ($eq). Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2429 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1240 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1228 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012 ($sub). Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012 ($sub). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1011 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1009 ($eq). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$995 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$993 ($eq). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1240 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1228 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012 ($sub). Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012 ($sub). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1011 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1009 ($eq). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$995 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$993 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1163 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1162 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1161 ($mux). Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1156 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1154 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1130 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1122 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1120 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1117 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1116 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1112 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1106 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1105 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1104 ($mux). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1100 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1098 ($eq). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2471 ($mux). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2471 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$779 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$763 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$762 ($mux). Removed top 3 bits (of 16) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4715 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3800 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3828 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5238 ($ne). Removed top 2 bits (of 10) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4551 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5409 ($ne). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Riscado_V.\alu.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:21$5 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Riscado_V.\alu.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:22$7 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Riscado_V.\alu.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:31$15 ($mux). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Riscado_V.\ls.\br.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:15$208 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:123$28 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30 ($eq). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$procmux$3060_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5263 ($ne). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Riscado_V.\pc.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:30$64 ($add). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2497_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$749 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$748 ($add). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$748 ($add). Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$747 ($lt). Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$762_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_ADDR[31:0]$806. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1559_Y. Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1567_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1572_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1583_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1589_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1593_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1603_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1607_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1612_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1617_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1643_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1647_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_ADDR[31:0]$806. Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2349_Y. Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2429_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR[5:0]$997. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR[5:0]$1006. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1011_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR[5:0]$997. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR[5:0]$1006. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$995_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1011_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$748_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Riscado_V.\alu.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:21$5_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Riscado_V.\alu.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:22$7_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Riscado_V.\alu.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:31$15_Y. 17.15. Executing PEEPOPT pass (run peephole optimizers). 17.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 32 unused wires. <suppressed ~1 debug messages> 17.17. Executing SHARE pass (SAT-based resource sharing). Found 7 cells in module processorci_top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113 ($memrd): Found 13 activation_patterns using ctrl signal { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Controller.Memory.memory_write \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [12:9] \Riscado_V.ctrlUnit.aluOperation [7:0] \Controller.Interpreter.memory_mux_selector }. Found 1 candidates: $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110 Analyzing resource sharing with $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110 ($memrd): Found 12 activation_patterns using ctrl signal { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [12:9] \Riscado_V.ctrlUnit.aluOperation [7:0] }. Forbidden control signals for this pair of cells: { $flatten\Riscado_V.\ctrlUnit.$or$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:175$44_Y $flatten\Riscado_V.\ls.\br.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:14$207_Y $flatten\Riscado_V.\ls.\br.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:15$208_Y $flatten\Riscado_V.\ls.\br.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:16$209_Y $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:21$4_Y $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:22$6_Y $flatten\Riscado_V.\alu.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:31$14_Y $flatten\Controller.$eq$/eda/processor-ci-controller/src/controller.v:118$796_Y $flatten\Controller.$logic_or$/eda/processor-ci-controller/src/controller.v:121$799_Y } Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [5] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [7] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [9] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [10] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [0] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [12] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [3] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [4] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [11] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [6] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [1] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [2] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Controller.Memory.memory_write \Controller.Interpreter.memory_mux_selector } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [12:9] \Riscado_V.ctrlUnit.aluOperation [7:0] } = 14'01000000000000 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [0] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [12] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [3] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [4] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [11] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [6] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [7] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [9] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [10] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [1] } = 3'011 Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [2] } = 3'011 Size of SAT problem: 0 cells, 189 variables, 727 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Controller.Memory.memory_write \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [12:9] \Riscado_V.ctrlUnit.aluOperation [7:0] \Controller.Interpreter.memory_mux_selector } = 18'000110000100000000 Analyzing resource sharing options for $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110 ($memrd): Found 12 activation_patterns using ctrl signal { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [12:9] \Riscado_V.ctrlUnit.aluOperation [7:0] }. No candidates found. Analyzing resource sharing options for $flatten\Riscado_V.\alu.$sshr$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:28$13 ($sshr): Found 1 activation_patterns using ctrl signal \Riscado_V.ctrlUnit.aluOperation [10]. No candidates found. Analyzing resource sharing options for $flatten\Riscado_V.\alu.$shr$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:24$9 ($shr): Found 1 activation_patterns using ctrl signal \Riscado_V.ctrlUnit.aluOperation [9]. No candidates found. Analyzing resource sharing options for $flatten\Riscado_V.\alu.$shl$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:20$3 ($shl): Found 1 activation_patterns using ctrl signal \Riscado_V.ctrlUnit.aluOperation [7]. No candidates found. Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$802 ($memrd): Found 4 activation_patterns using ctrl signal { \Controller.Memory.memory_write \Controller.Memory.memory_read \Riscado_V.ctrlUnit.writeLen [2:1] $flatten\Controller.\Interpreter.$procmux$1599_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }. No candidates found. Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$802 ($memrd): Found 1 activation_patterns using ctrl signal { \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1599_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }. No candidates found. 17.18. Executing TECHMAP pass (map to technology primitives). 17.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/cmp2lut.v Parsing Verilog input from `/usr/local/share/synlig/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 17.18.2. Continuing TECHMAP pass. Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt. No more expansions possible. <suppressed ~197 debug messages> 17.19. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 6 unused wires. <suppressed ~1 debug messages> 17.21. Executing TECHMAP pass (map to technology primitives). 17.21.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/mul2dsp.v Parsing Verilog input from `/usr/local/share/synlig/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 17.21.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/dsp_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 17.21.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 17.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module processorci_top: creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1094 ($sub). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1049 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1053 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1054 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1057 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1064 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1068 ($add). creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1056 ($sub). creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1031 ($add). creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1026 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012 ($sub). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994 ($add). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010 ($add). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012 ($sub). creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1175 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1186 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1124 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1135 ($add). creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$748 ($add). creating $macc model for $flatten\Riscado_V.\alu.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:19$2 ($add). creating $macc model for $flatten\Riscado_V.\alu.$sub$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:27$12 ($sub). creating $macc model for $flatten\Riscado_V.\pc.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:30$64 ($add). creating $alu model for $macc $flatten\Riscado_V.\pc.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:30$64. creating $alu model for $macc $flatten\Riscado_V.\alu.$sub$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:27$12. creating $alu model for $macc $flatten\Riscado_V.\alu.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:19$2. creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$748. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1135. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1124. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1186. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1175. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994. creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1026. creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1031. creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1056. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1068. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1064. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1057. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1054. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1053. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1049. creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1094. creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1093 ($gt): new $alu creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1073 ($ge): new $alu creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1066 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1073. creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$747 ($lt): new $alu creating $alu model for $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:21$4 ($lt): new $alu creating $alu model for $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:22$6 ($lt): new $alu creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1071 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1073. creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$749 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$747. creating $alu model for $flatten\Riscado_V.\alu.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:31$14 ($eq): merged with $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:22$6. creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$747, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$749: $auto$alumacc.cc:485:replace_alu$5740 creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1073, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1066, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1071: $auto$alumacc.cc:485:replace_alu$5751 creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1093: $auto$alumacc.cc:485:replace_alu$5764 creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1094: $auto$alumacc.cc:485:replace_alu$5769 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1049: $auto$alumacc.cc:485:replace_alu$5772 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1053: $auto$alumacc.cc:485:replace_alu$5775 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1054: $auto$alumacc.cc:485:replace_alu$5778 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1057: $auto$alumacc.cc:485:replace_alu$5781 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1064: $auto$alumacc.cc:485:replace_alu$5784 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1068: $auto$alumacc.cc:485:replace_alu$5787 creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1056: $auto$alumacc.cc:485:replace_alu$5790 creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1031: $auto$alumacc.cc:485:replace_alu$5793 creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1026: $auto$alumacc.cc:485:replace_alu$5796 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994: $auto$alumacc.cc:485:replace_alu$5799 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010: $auto$alumacc.cc:485:replace_alu$5802 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012: $auto$alumacc.cc:485:replace_alu$5805 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994: $auto$alumacc.cc:485:replace_alu$5808 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010: $auto$alumacc.cc:485:replace_alu$5811 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012: $auto$alumacc.cc:485:replace_alu$5814 creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1175: $auto$alumacc.cc:485:replace_alu$5817 creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1186: $auto$alumacc.cc:485:replace_alu$5820 creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1124: $auto$alumacc.cc:485:replace_alu$5823 creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1135: $auto$alumacc.cc:485:replace_alu$5826 creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$748: $auto$alumacc.cc:485:replace_alu$5829 creating $alu cell for $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:22$6, $flatten\Riscado_V.\alu.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:31$14: $auto$alumacc.cc:485:replace_alu$5832 creating $alu cell for $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:21$4: $auto$alumacc.cc:485:replace_alu$5843 creating $alu cell for $flatten\Riscado_V.\alu.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:19$2: $auto$alumacc.cc:485:replace_alu$5856 creating $alu cell for $flatten\Riscado_V.\alu.$sub$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:27$12: $auto$alumacc.cc:485:replace_alu$5859 creating $alu cell for $flatten\Riscado_V.\pc.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:30$64: $auto$alumacc.cc:485:replace_alu$5862 created 29 $alu and 0 $macc cells. 17.23. Executing OPT pass (performing simple optimizations). 17.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~5 debug messages> 17.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~114 debug messages> 17.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 17.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 17.23.6. Executing OPT_DFF pass (perform DFF optimizations). 17.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 2 unused cells and 13 unused wires. <suppressed ~3 debug messages> 17.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.23.9. Rerunning OPT passes. (Maybe there is more to do..) 17.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~114 debug messages> 17.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 17.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.23.13. Executing OPT_DFF pass (perform DFF optimizations). 17.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 17.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.23.16. Finished OPT passes. (There is nothing left to do.) 17.24. Executing MEMORY pass. 17.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 17.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 17.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing processorci_top.Controller.Data_Memory.memory write port 0. Analyzing processorci_top.Controller.Memory.memory write port 0. Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0. Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0. Analyzing processorci_top.Riscado_V.registerFile.registers write port 0. 17.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 17.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\Riscado_V.registerFile.registers'[0] in module `\processorci_top': no output FF found. Checking read port `\Riscado_V.registerFile.registers'[1] in module `\processorci_top': no output FF found. Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found. Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found. Checking read port address `\Riscado_V.registerFile.registers'[0] in module `\processorci_top': address FF has fully-defined init value, not supported. Checking read port address `\Riscado_V.registerFile.registers'[1] in module `\processorci_top': address FF has fully-defined init value, not supported. 17.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 2 unused cells and 18 unused wires. <suppressed ~3 debug messages> 17.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory processorci_top.Riscado_V.registerFile.registers by address: 17.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 17.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 17.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 17.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 17.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0] mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0] mapping memory processorci_top.Riscado_V.registerFile.registers via $__TRELLIS_DPR16X4_ <suppressed ~1170 debug messages> 17.27. Executing TECHMAP pass (map to technology primitives). 17.27.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/lutrams_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 17.27.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/brams_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 17.27.3. Continuing TECHMAP pass. Using template $paramod$23110e440dd343be7ccff453e7838cea1dda03ba\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~1091 debug messages> 17.28. Executing OPT pass (performing simple optimizations). 17.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~180 debug messages> 17.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 17.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\ResetBootSystem.$procdff$3560 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Adding SRST signal on $auto$ff.cc:266:slice$5615 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1068_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$5554 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1827_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]). Adding SRST signal on $auto$ff.cc:266:slice$5403 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2494_Y, Q = \ResetBootSystem.counter, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$5224 ($sdffe) from module processorci_top (D = $flatten\Riscado_V.\pc.$procmux$2539_Y [1:0], Q = \Riscado_V.pc.pc [1:0]). 17.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 2 unused cells and 7545 unused wires. <suppressed ~3 debug messages> 17.28.5. Rerunning OPT passes. (Removed registers in this run.) 17.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~10 debug messages> 17.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$8299 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$5727 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). 17.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 9 unused wires. <suppressed ~2 debug messages> 17.28.10. Rerunning OPT passes. (Removed registers in this run.) 17.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.28.13. Executing OPT_DFF pass (perform DFF optimizations). 17.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 17.28.15. Finished fast OPT passes. 17.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 17.30. Executing OPT pass (performing simple optimizations). 17.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~73 debug messages> 17.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$8297: { $auto$opt_dff.cc:194:make_patterns_logic$8294 $auto$fsm_map.cc:74:implement_pattern_cache$3795 $auto$opt_dff.cc:194:make_patterns_logic$5555 $auto$opt_dff.cc:194:make_patterns_logic$5557 } Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$762: Old ports: A=\Controller.core_address_memory [11:0], B={ \Controller.Interpreter.memory_page_number [5:0] \Controller.core_address_memory [5:0] }, Y=$auto$wreduce.cc:461:run$5699 [11:0] New ports: A=\Controller.core_address_memory [11:6], B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$5699 [11:6] New connections: $auto$wreduce.cc:461:run$5699 [5:0] = \Controller.core_address_memory [5:0] Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1567: Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$5702 [2:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$5702 [2] $auto$wreduce.cc:461:run$5702 [0] } New connections: $auto$wreduce.cc:461:run$5702 [1] = $auto$wreduce.cc:461:run$5702 [0] Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1572: Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$5703 [6:0] New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$5703 [1:0] New connections: $auto$wreduce.cc:461:run$5703 [6:2] = { $auto$wreduce.cc:461:run$5703 [1] 3'010 $auto$wreduce.cc:461:run$5703 [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1583: Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$5704 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$5704 [2] New connections: { $auto$wreduce.cc:461:run$5704 [3] $auto$wreduce.cc:461:run$5704 [1:0] } = { $auto$wreduce.cc:461:run$5704 [2] 2'00 } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1593: Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$5706 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$5706 [0] New connections: $auto$wreduce.cc:461:run$5706 [3:1] = { $auto$wreduce.cc:461:run$5706 [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1607: Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$5708 [6:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$5708 [0] New connections: $auto$wreduce.cc:461:run$5708 [6:1] = { $auto$wreduce.cc:461:run$5708 [0] 1'0 $auto$wreduce.cc:461:run$5708 [0] 3'011 } Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2002: Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$2002_Y New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$2002_Y [4:0] New connections: $flatten\Controller.\Interpreter.$procmux$2002_Y [7:5] = 3'000 Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2127: Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2127_Y New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2127_Y [23:0] New connections: $flatten\Controller.\Interpreter.$procmux$2127_Y [31:24] = 8'00000000 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2137: $auto$opt_reduce.cc:137:opt_pmux$3629 Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2341: Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$5714 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2341_Y New ports: A=3'000, B={ $auto$wreduce.cc:461:run$5714 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2341_Y [2:0] New connections: $flatten\Controller.\Uart.$procmux$2341_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2349: Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$5714 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$5714 [2] New connections: $auto$wreduce.cc:461:run$5714 [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2425: Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2425_Y New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2425_Y [2:1] New connections: { $flatten\Controller.\Uart.$procmux$2425_Y [3] $flatten\Controller.\Uart.$procmux$2425_Y [0] } = 2'00 Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1383: Old ports: A=3'000, B={ 2'00 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1161_Y [0] 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1162_Y [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164_Y [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1161_Y [0] $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1162_Y [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164_Y [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164: Old ports: A=2'11, B=2'00, Y=$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164_Y [1:0] New ports: A=1'1, B=1'0, Y=$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164_Y [0] New connections: $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164_Y [1] = $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164_Y [0] Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1520: Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1105_Y [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107_Y [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1105_Y [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107_Y [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107: Old ports: A=2'11, B=2'00, Y=$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107_Y [1:0] New ports: A=1'1, B=1'0, Y=$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107_Y [0] New connections: $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107_Y [1] = $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107_Y [0] New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2512: { $flatten\ResetBootSystem.$procmux$2498_CMP $flatten\ResetBootSystem.$procmux$2497_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2515: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2515_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2515_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2515_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200: Old ports: A=0, B={ \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31:25] \Riscado_V.ir [11:7] }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y New ports: A=12'000000000000, B={ \Riscado_V.ir [31:25] \Riscado_V.ir [11:7] }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11:0] New connections: $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [31:12] = { $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] } Consolidated identical input bits for $mux cell $flatten\Riscado_V.\ls.\br.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:18$213: Old ports: A={ 24'000000000000000000000000 \Riscado_V.ls.br.byte }, B={ \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte }, Y=\Riscado_V.ls.byteReadOut New ports: A=1'0, B=\Riscado_V.ls.br.byte [7], Y=\Riscado_V.ls.byteReadOut [8] New connections: { \Riscado_V.ls.byteReadOut [31:9] \Riscado_V.ls.byteReadOut [7:0] } = { \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.br.byte } Consolidated identical input bits for $mux cell $flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:43$222: Old ports: A={ \Riscado_V.ls.writeDataIn [7:0] \Riscado_V.ls.br.dataIn [23:0] }, B={ \Riscado_V.ls.br.dataIn [31:24] \Riscado_V.ls.writeDataIn [7:0] \Riscado_V.ls.br.dataIn [15:0] }, Y=$flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:43$222_Y New ports: A={ \Riscado_V.ls.writeDataIn [7:0] \Riscado_V.ls.br.dataIn [23:16] }, B={ \Riscado_V.ls.br.dataIn [31:24] \Riscado_V.ls.writeDataIn [7:0] }, Y=$flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:43$222_Y [31:16] New connections: $flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:43$222_Y [15:0] = \Riscado_V.ls.br.dataIn [15:0] Consolidated identical input bits for $mux cell $flatten\Riscado_V.\ls.\hr.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:31$218: Old ports: A={ 16'0000000000000000 \Riscado_V.ls.hr.half }, B={ \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half }, Y=\Riscado_V.ls.halfReadOut New ports: A=1'0, B=\Riscado_V.ls.hr.half [15], Y=\Riscado_V.ls.halfReadOut [16] New connections: { \Riscado_V.ls.halfReadOut [31:17] \Riscado_V.ls.halfReadOut [15:0] } = { \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.hr.half } Consolidated identical input bits for $mux cell $flatten\Riscado_V.\ls.\hw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:54$227: Old ports: A={ \Riscado_V.ls.writeDataIn [15:0] \Riscado_V.ls.br.dataIn [15:0] }, B={ \Riscado_V.ls.br.dataIn [31:24] \Riscado_V.ls.writeDataIn [15:0] \Riscado_V.ls.br.dataIn [7:0] }, Y=$flatten\Riscado_V.\ls.\hw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:54$227_Y New ports: A={ \Riscado_V.ls.writeDataIn [15:0] \Riscado_V.ls.br.dataIn [15:8] }, B={ \Riscado_V.ls.br.dataIn [31:24] \Riscado_V.ls.writeDataIn [15:0] }, Y=$flatten\Riscado_V.\ls.\hw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:54$227_Y [31:8] New connections: $flatten\Riscado_V.\ls.\hw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:54$227_Y [7:0] = \Riscado_V.ls.br.dataIn [7:0] Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2419: Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2425_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2419_Y New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2425_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2419_Y [2:0] New connections: $flatten\Controller.\Uart.$procmux$2419_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2521: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2515_Y, Y=$flatten\ResetBootSystem.$procmux$2521_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2515_Y [1], Y=$flatten\ResetBootSystem.$procmux$2521_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2521_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201: Old ports: A=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y, B={ \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [19:12] \Riscado_V.ir [20] \Riscado_V.ir [30:21] 1'0 }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y New ports: A={ $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11:0] }, B={ \Riscado_V.ir [31] \Riscado_V.ir [19:12] \Riscado_V.ir [20] \Riscado_V.ir [30:21] 1'0 }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20:0] New connections: $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [31:21] = { $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] } Consolidated identical input bits for $mux cell $flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:42$223: Old ports: A=$flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:43$222_Y, B={ \Riscado_V.ls.br.dataIn [31:16] \Riscado_V.ls.writeDataIn [7:0] \Riscado_V.ls.br.dataIn [7:0] }, Y=$flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:42$223_Y New ports: A={ $flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:43$222_Y [31:16] \Riscado_V.ls.br.dataIn [15:8] }, B={ \Riscado_V.ls.br.dataIn [31:16] \Riscado_V.ls.writeDataIn [7:0] }, Y=$flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:42$223_Y [31:8] New connections: $flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:42$223_Y [7:0] = \Riscado_V.ls.br.dataIn [7:0] Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202: Old ports: A=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y, B={ \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [7] \Riscado_V.ir [30:25] \Riscado_V.ir [11:8] 1'0 }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y New ports: A=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20:0], B={ \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [7] \Riscado_V.ir [30:25] \Riscado_V.ir [11:8] 1'0 }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20:0] New connections: $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [31:21] = { $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] } Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203: Old ports: A=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y, B={ \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31:20] }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y New ports: A=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20:0], B={ \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31:20] }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20:0] New connections: $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [31:21] = { $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] } Optimizing cells in module \processorci_top. Performed a total of 32 changes. 17.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 17.30.6. Executing OPT_DFF pass (perform DFF optimizations). 17.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 1 unused wires. <suppressed ~1 debug messages> 17.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 17.30.9. Rerunning OPT passes. (Maybe there is more to do..) 17.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~75 debug messages> 17.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 17.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.30.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$5434 ($sdff) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$5478 ($sdffe) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$5506 ($sdffe) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$5608 ($sdffe) from module processorci_top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$5608 ($sdffe) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$5608 ($sdffe) from module processorci_top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top. 17.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 17.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~4 debug messages> 17.30.16. Rerunning OPT passes. (Maybe there is more to do..) 17.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~75 debug messages> 17.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1577: Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1577_Y New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1577_Y [4:0] New connections: $flatten\Controller.\Interpreter.$procmux$1577_Y [7:5] = 3'000 Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1555: Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$5712 [0] 6'000000 $auto$wreduce.cc:461:run$5705 [1:0] 1'0 $auto$wreduce.cc:461:run$5710 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$5709 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$5708 [6] 1'0 $auto$wreduce.cc:461:run$5708 [6] 3'011 $auto$wreduce.cc:461:run$5708 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$5704 [3] 2'00 $auto$wreduce.cc:461:run$5704 [3] 6'000010 $auto$wreduce.cc:461:run$5705 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$5704 [3] $auto$wreduce.cc:461:run$5704 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1577_Y 1'0 $auto$wreduce.cc:461:run$5703 [6] 3'010 $auto$wreduce.cc:461:run$5703 [2] $auto$wreduce.cc:461:run$5703 [6] $auto$wreduce.cc:461:run$5703 [2] 13'0001001100010 $auto$wreduce.cc:461:run$5702 [2:1] $auto$wreduce.cc:461:run$5702 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$5701 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1555_Y New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$5712 [0] 5'00000 $auto$wreduce.cc:461:run$5705 [1:0] $auto$wreduce.cc:461:run$5710 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$5709 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$5708 [6] 1'0 $auto$wreduce.cc:461:run$5708 [6] 3'011 $auto$wreduce.cc:461:run$5708 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$5704 [3] 2'00 $auto$wreduce.cc:461:run$5704 [3] 5'00010 $auto$wreduce.cc:461:run$5705 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$5704 [3] $auto$wreduce.cc:461:run$5704 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1577_Y [4:0] $auto$wreduce.cc:461:run$5703 [6] 3'010 $auto$wreduce.cc:461:run$5703 [2] $auto$wreduce.cc:461:run$5703 [6] $auto$wreduce.cc:461:run$5703 [2] 11'00100110010 $auto$wreduce.cc:461:run$5702 [2:1] $auto$wreduce.cc:461:run$5702 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$5701 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1555_Y [6:0] New connections: $flatten\Controller.\Interpreter.$procmux$1555_Y [7] = 1'0 Optimizing cells in module \processorci_top. Performed a total of 2 changes. 17.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.30.20. Executing OPT_DFF pass (perform DFF optimizations). 17.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 17.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.30.23. Rerunning OPT passes. (Maybe there is more to do..) 17.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~75 debug messages> 17.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 17.30.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.30.27. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$5681 ($sdff) from module processorci_top. 17.30.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 17.30.29. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 17.30.30. Rerunning OPT passes. (Maybe there is more to do..) 17.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~75 debug messages> 17.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 17.30.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.30.34. Executing OPT_DFF pass (perform DFF optimizations). 17.30.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 17.30.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.30.37. Finished OPT passes. (There is nothing left to do.) 17.31. Executing TECHMAP pass (map to technology primitives). 17.31.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 17.31.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/arith_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 17.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $ne. Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $bmux. Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $or. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $lut. Using extmapper simplemap for cells of type $sdffe. Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu. Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu. Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu. Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu. Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu. Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux. Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux. Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux. Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux. Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $xor. Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux. Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $sdff. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ecp5_alu for cells of type $alu. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$e765c459d3029c22a22a27989e94858fd9ebfa9c\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_80_ecp5_alu for cells of type $alu. Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $sdffce. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~5510 debug messages> 17.32. Executing OPT pass (performing simple optimizations). 17.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~11054 debug messages> 17.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~5217 debug messages> Removed a total of 1739 cells. 17.32.3. Executing OPT_DFF pass (perform DFF optimizations). 17.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1402 unused cells and 4837 unused wires. <suppressed ~1408 debug messages> 17.32.5. Finished fast OPT passes. 17.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 17.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 17.35. Executing TECHMAP pass (map to technology primitives). 17.35.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 17.35.2. Continuing TECHMAP pass. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. No more expansions possible. <suppressed ~920 debug messages> 17.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~104 debug messages> 17.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 17.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in processorci_top. 17.39. Executing ATTRMVCP pass (move or copy attributes). 17.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 4432 unused wires. <suppressed ~1 debug messages> 17.41. Executing TECHMAP pass (map to technology primitives). 17.41.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/latches_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 17.41.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 17.42. Executing ABC9 pass. 17.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 17.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 17.42.3. Executing PROC pass (convert processes to netlists). 17.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$39255'. Cleaned up 1 empty switch. 17.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$39256 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 17.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 17.42.3.4. Executing PROC_INIT pass (extract init attributes). 17.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 17.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 17.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$39256'. 1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$39254_EN[3:0]$39262 2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$39254_DATA[3:0]$39260 3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$39254_ADDR[3:0]$39261 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$39255'. 17.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 17.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39248_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39247_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39243_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39240_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39241_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39242_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39246_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39244_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39252_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39238_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39253_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39249_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39250_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39251_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39245_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39239_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$39254_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$39256'. created $dff cell `$procdff$39306' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$39254_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$39256'. created $dff cell `$procdff$39307' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$39254_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$39256'. created $dff cell `$procdff$39308' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$39255'. created direct connection (no actual register cell created). 17.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 17.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39280'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$39256'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$39255'. Cleaned up 1 empty switch. 17.42.3.12. Executing OPT_EXPR pass (perform const folding). 17.42.4. Executing PROC pass (convert processes to netlists). 17.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$39326'. Cleaned up 1 empty switch. 17.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$39327 in module $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 17.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 17.42.4.4. Executing PROC_INIT pass (extract init attributes). 17.42.4.5. Executing PROC_ARST pass (detect async resets in processes). 17.42.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 17.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. Creating decoders for process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$39327'. 1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$39325_EN[3:0]$39332 2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$39325_DATA[3:0]$39331 3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$39325_ADDR[3:0]$39333 Creating decoders for process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$39326'. 17.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 17.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.\i' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39309_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39310_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39311_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39315_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39316_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39321_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39320_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39317_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39313_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39322_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39323_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39312_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39318_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39324_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39319_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$39314_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$39325_DATA' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$39327'. created $dff cell `$procdff$39377' with positive edge clock. Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$39325_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$39327'. created $dff cell `$procdff$39378' with positive edge clock. Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$39325_ADDR' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$39327'. created $dff cell `$procdff$39379' with positive edge clock. Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.\muxwre' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$39326'. created direct connection (no actual register cell created). 17.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 17.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$39351'. Found and cleaned up 1 empty switch in `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$39327'. Removing empty process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$39326'. Cleaned up 1 empty switch. 17.42.4.12. Executing OPT_EXPR pass (perform const folding). 17.42.5. Executing SCC pass (detecting logic loops). Found an SCC: $auto$simplemap.cc:38:simplemap_not$25595 $auto$ff.cc:266:slice$24175 $auto$ff.cc:479:convert_ce_over_srst$38335 $auto$alumacc.cc:485:replace_alu$5740.slice[0].ccu2c_i $auto$ff.cc:266:slice$24176 $auto$ff.cc:479:convert_ce_over_srst$38337 $auto$ff.cc:266:slice$24177 $auto$ff.cc:479:convert_ce_over_srst$38339 $auto$alumacc.cc:485:replace_alu$5740.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12236 $auto$simplemap.cc:38:simplemap_not$25598 $auto$ff.cc:266:slice$24178 $auto$ff.cc:479:convert_ce_over_srst$38341 $auto$ff.cc:266:slice$24179 $auto$ff.cc:479:convert_ce_over_srst$38343 $auto$simplemap.cc:126:simplemap_reduce$8443 $auto$simplemap.cc:126:simplemap_reduce$18332 $auto$simplemap.cc:38:simplemap_not$10729 $auto$simplemap.cc:75:simplemap_bitop$15783 $auto$simplemap.cc:38:simplemap_not$10938 $auto$alumacc.cc:485:replace_alu$5740.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12237 $auto$simplemap.cc:38:simplemap_not$30685 $auto$ff.cc:266:slice$24180 $auto$ff.cc:479:convert_ce_over_srst$38345 $auto$simplemap.cc:126:simplemap_reduce$18298 $auto$simplemap.cc:126:simplemap_reduce$18296 $auto$simplemap.cc:126:simplemap_reduce$18334 $auto$simplemap.cc:126:simplemap_reduce$18331 $auto$simplemap.cc:126:simplemap_reduce$12241 $auto$simplemap.cc:126:simplemap_reduce$12239 $auto$simplemap.cc:126:simplemap_reduce$12235 $auto$simplemap.cc:38:simplemap_not$25596 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$37719 $auto$ff.cc:266:slice$16590 $auto$simplemap.cc:126:simplemap_reduce$16714 $auto$simplemap.cc:126:simplemap_reduce$16729 $auto$ff.cc:266:slice$16589 $auto$ff.cc:266:slice$16588 $auto$opt_expr.cc:617:replace_const_cells$37735 $auto$simplemap.cc:267:simplemap_mux$30650 $auto$simplemap.cc:126:simplemap_reduce$30635 $auto$simplemap.cc:126:simplemap_reduce$30632 $auto$simplemap.cc:75:simplemap_bitop$30648 $auto$simplemap.cc:267:simplemap_mux$16700 $auto$simplemap.cc:225:simplemap_logbin$16703 $auto$simplemap.cc:196:simplemap_lognot$16718 $auto$simplemap.cc:126:simplemap_reduce$16716 $auto$simplemap.cc:126:simplemap_reduce$16713 $auto$opt_expr.cc:617:replace_const_cells$37721 $auto$simplemap.cc:196:simplemap_lognot$16733 $auto$simplemap.cc:126:simplemap_reduce$16731 $auto$simplemap.cc:126:simplemap_reduce$16728 $auto$ff.cc:266:slice$16587 $auto$simplemap.cc:126:simplemap_reduce$18120 $auto$simplemap.cc:126:simplemap_reduce$18118 $auto$simplemap.cc:225:simplemap_logbin$16658 $auto$simplemap.cc:196:simplemap_lognot$16668 $auto$simplemap.cc:126:simplemap_reduce$16666 $auto$opt_expr.cc:617:replace_const_cells$37733 $auto$simplemap.cc:267:simplemap_mux$30649 $auto$simplemap.cc:126:simplemap_reduce$30640 $auto$simplemap.cc:126:simplemap_reduce$30637 $auto$simplemap.cc:75:simplemap_bitop$30645 Found an SCC: $auto$ff.cc:266:slice$16431 $auto$opt_expr.cc:617:replace_const_cells$37589 $auto$ff.cc:266:slice$16430 $auto$simplemap.cc:126:simplemap_reduce$16545 $auto$simplemap.cc:126:simplemap_reduce$16572 $auto$opt_expr.cc:617:replace_const_cells$37587 $auto$ff.cc:266:slice$16429 $auto$opt_expr.cc:617:replace_const_cells$37577 $auto$ff.cc:266:slice$16428 $auto$simplemap.cc:126:simplemap_reduce$16548 $auto$simplemap.cc:126:simplemap_reduce$16544 $auto$simplemap.cc:126:simplemap_reduce$16575 $auto$simplemap.cc:126:simplemap_reduce$16571 $auto$opt_expr.cc:617:replace_const_cells$37585 $auto$ff.cc:266:slice$16427 $auto$opt_expr.cc:617:replace_const_cells$37583 $auto$ff.cc:266:slice$16426 $auto$simplemap.cc:126:simplemap_reduce$16543 $auto$opt_expr.cc:617:replace_const_cells$37573 $auto$simplemap.cc:126:simplemap_reduce$16570 $auto$ff.cc:266:slice$16425 $auto$ff.cc:266:slice$16424 $auto$simplemap.cc:196:simplemap_lognot$16581 $auto$simplemap.cc:126:simplemap_reduce$16579 $auto$simplemap.cc:126:simplemap_reduce$16577 $auto$simplemap.cc:126:simplemap_reduce$16574 $auto$simplemap.cc:126:simplemap_reduce$16569 $auto$simplemap.cc:38:simplemap_not$30621 $auto$simplemap.cc:225:simplemap_logbin$16527 $auto$simplemap.cc:196:simplemap_lognot$16554 $auto$simplemap.cc:126:simplemap_reduce$16552 $auto$simplemap.cc:126:simplemap_reduce$16550 $auto$simplemap.cc:126:simplemap_reduce$16547 $auto$simplemap.cc:126:simplemap_reduce$16542 $auto$ff.cc:266:slice$16423 $auto$simplemap.cc:167:logic_reduce$10805 $auto$simplemap.cc:225:simplemap_logbin$16526 Found an SCC: $auto$ff.cc:266:slice$16593 $auto$ff.cc:266:slice$16599 $auto$opt_expr.cc:617:replace_const_cells$37731 $auto$ff.cc:266:slice$16598 $auto$simplemap.cc:126:simplemap_reduce$16751 $auto$opt_expr.cc:617:replace_const_cells$37729 $auto$ff.cc:266:slice$16597 $auto$ff.cc:266:slice$16596 $auto$simplemap.cc:126:simplemap_reduce$16754 $auto$simplemap.cc:126:simplemap_reduce$16750 $auto$opt_expr.cc:617:replace_const_cells$37727 $auto$ff.cc:266:slice$16595 $auto$simplemap.cc:126:simplemap_reduce$16749 $auto$opt_expr.cc:617:replace_const_cells$37725 $auto$ff.cc:266:slice$16594 $auto$ff.cc:266:slice$16592 $auto$simplemap.cc:126:simplemap_reduce$16756 $auto$simplemap.cc:126:simplemap_reduce$16753 $auto$simplemap.cc:126:simplemap_reduce$16748 $auto$opt_expr.cc:617:replace_const_cells$37723 $auto$ff.cc:266:slice$16591 $auto$simplemap.cc:126:simplemap_reduce$17955 $auto$simplemap.cc:196:simplemap_lognot$16760 $auto$simplemap.cc:126:simplemap_reduce$16758 Found 4 SCCs in module processorci_top. Found 4 SCCs. 17.42.6. Executing ABC9_OPS pass (helper functions for ABC9). 17.42.7. Executing PROC pass (convert processes to netlists). 17.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 17.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 17.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 17.42.7.4. Executing PROC_INIT pass (extract init attributes). 17.42.7.5. Executing PROC_ARST pass (detect async resets in processes). 17.42.7.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 17.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 17.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches). 17.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs). 17.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 17.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 17.42.7.12. Executing OPT_EXPR pass (perform const folding). 17.42.8. Executing TECHMAP pass (map to technology primitives). 17.42.8.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 17.42.8.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~164 debug messages> 17.42.9. Executing OPT pass (performing simple optimizations). 17.42.9.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4. 17.42.9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4'. Removed a total of 0 cells. 17.42.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 17.42.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4. Performed a total of 0 changes. 17.42.9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4'. Removed a total of 0 cells. 17.42.9.6. Executing OPT_DFF pass (perform DFF optimizations). 17.42.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.. 17.42.9.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4. 17.42.9.9. Finished OPT passes. (There is nothing left to do.) 17.42.10. Executing TECHMAP pass (map to technology primitives). 17.42.10.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_map.v Parsing Verilog input from `/usr/local/share/synlig/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 17.42.10.2. Continuing TECHMAP pass. Using template $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4 for cells of type $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~1064 debug messages> 17.42.11. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_model.v Parsing Verilog input from `/usr/local/share/synlig/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 17.42.12. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 17.42.13. Executing ABC9_OPS pass (helper functions for ABC9). 17.42.14. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 17.42.15. Executing TECHMAP pass (map to technology primitives). 17.42.15.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 17.42.15.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~203 debug messages> 17.42.16. Executing OPT pass (performing simple optimizations). 17.42.16.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~18 debug messages> 17.42.16.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 17.42.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 17.42.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 17.42.16.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.42.16.6. Executing OPT_DFF pass (perform DFF optimizations). 17.42.16.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 17.42.16.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.42.16.9. Rerunning OPT passes. (Maybe there is more to do..) 17.42.16.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 17.42.16.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 17.42.16.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 17.42.16.13. Executing OPT_DFF pass (perform DFF optimizations). 17.42.16.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 17.42.16.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 17.42.16.16. Finished OPT passes. (There is nothing left to do.) 17.42.17. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 17.42.18. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 7958 cells with 50483 new cells, skipped 4858 cells. replaced 3 cell types: 1741 $_OR_ 180 $_XOR_ 6037 $_MUX_ not replaced 11 cell types: 11 $print 21 $scopeinfo 392 $_NOT_ 1255 $_AND_ 253 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 805 TRELLIS_FF 32 $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4 32 $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4_$abc9_byp 1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1 $__ABC9_SCC_BREAKER 17.42.18.1. Executing ABC9_OPS pass (helper functions for ABC9). 17.42.18.2. Executing ABC9_OPS pass (helper functions for ABC9). 17.42.18.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 21647 AND gates and 63092 wires from module `processorci_top' to a netlist network with 5056 inputs and 1165 outputs. 17.42.18.4. Executing ABC9_EXE pass (technology mapping using ABC9). 17.42.18.5. Executing ABC9. Running ABC command: "built in abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 5056/ 1165 and = 19870 lev = 58 (6.48) mem = 0.56 MB box = 1313 bb = 1060 ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 1 carries. ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 5056/ 1165 and = 25526 lev = 63 (4.97) mem = 0.63 MB ch = 2445 box = 1312 bb = 1060 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 64. Obj = 148. Set = 672. CutMin = no ABC: Node = 25526. Ch = 1808. Total mem = 7.43 MB. Peak cut mem = 0.36 MB. ABC: P: Del = 8653.00. Ar = 22972.0. Edge = 26640. Cut = 384518. T = 0.18 sec ABC: P: Del = 8313.00. Ar = 30387.0. Edge = 32606. Cut = 322807. T = 0.16 sec ABC: P: Del = 8313.00. Ar = 12194.0. Edge = 25467. Cut = 700449. T = 0.31 sec ABC: F: Del = 8313.00. Ar = 8270.0. Edge = 22692. Cut = 519585. T = 0.24 sec ABC: A: Del = 8313.00. Ar = 7378.0. Edge = 20274. Cut = 509464. T = 0.36 sec ABC: A: Del = 8313.00. Ar = 7262.0. Edge = 20176. Cut = 512589. T = 0.36 sec ABC: Total time = 1.62 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 5056/ 1165 and = 16269 lev = 53 (5.42) mem = 0.52 MB box = 1296 bb = 1060 ABC: Mapping (K=7) : lut = 5117 edge = 20028 lev = 17 (2.20) Boxes are not in a topological order. Switching to level computation without boxes. ABC: levB = 53 mem = 0.26 MB ABC: LUT = 5117 : 2=561 11.0 % 3=740 14.5 % 4=2776 54.3 % 5=791 15.5 % 6=116 2.3 % 7=133 2.6 % Ave = 3.91 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 20.83 seconds, total: 20.83 seconds 17.42.18.6. Executing AIGER frontend. <suppressed ~12471 debug messages> Removed 21666 unused cells and 48150 unused wires. 17.42.18.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 5128 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 236 ABC RESULTS: $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4_$abc9_byp cells: 32 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 1028 ABC RESULTS: input signals: 1140 ABC RESULTS: output signals: 235 Removing temp directory. 17.42.19. Executing TECHMAP pass (map to technology primitives). 17.42.19.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_unmap.v Parsing Verilog input from `/usr/local/share/synlig/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 17.42.19.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4 for cells of type $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4. Using template $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000110 for cells of type $__ABC9_SCC_BREAKER. No more expansions possible. <suppressed ~2378 debug messages> Removed 394 unused cells and 79316 unused wires. 17.43. Executing TECHMAP pass (map to technology primitives). 17.43.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 17.43.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$d1088e62ce917367af6d3bdefd80398c954f4dd8\$lut for cells of type $lut. Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod$ce842517356ca46fc2cf2d3b7e874d6b9c6d1946\$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. Using template $paramod$dc9c215adf430fe146293bd1a8c0ece29df469f5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$41369c42bc38092838c87189bc1039c10165227e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. Using template $paramod$70ebb6cf5bc7d63c5c1a98ccefefa2af79e8f2a9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$96fb3234aee435e167d512822a0548b5860ec3b1\$lut for cells of type $lut. Using template $paramod$18bae5195eb8a56a96d2430b2583b478653a0cde\$lut for cells of type $lut. Using template $paramod$1a7f8886b6169f822a6b7b468375f76af630467d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$7f5774e254b7c1bd737c62ce10e03679e6a3bbf2\$lut for cells of type $lut. Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut. Using template $paramod$c017e2dbeb95a3a99478d935373a8d6522f778e6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8\$lut for cells of type $lut. Using template $paramod$ff37fe8b5223ab3ba2a45b5838342966dcda7aac\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$9256a92edc7b95b13cb92b8d69124efbc2dbd89d\$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$94c7bdeb9de71452ba15823befae43641100f4bc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$ab16631cbb2449b9281844acac755bf651b420a4\$lut for cells of type $lut. Using template $paramod$cd14f2ec08667ca50a951d6d9af08c05385f11fd\$lut for cells of type $lut. Using template $paramod$46a9d0e9d20fa7ad6bc1e8e22dc804e878bf1130\$lut for cells of type $lut. Using template $paramod$1e06da73d21c5736c1f943dd00fdcd4f80e36a2b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$dd7c1583fe0ade167c7826c594e5d16b758a72fe\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$0defb1586b24785b85905f661056d6b3d902c0c8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. Using template $paramod$2645ed3928f2726e8ccb403cb23252de43b617d7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$0a4d85497e20c50068555dd5ad9ad3a7952cab73\$lut for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod$e6049326c8634f79a905c381bb150ca718b543fa\$lut for cells of type $lut. Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut. Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut. Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut. Using template $paramod$98e99942f364173ee1da9b31f34c7829f11e4be1\$lut for cells of type $lut. Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b\$lut for cells of type $lut. Using template $paramod$0b4a818b50b974f2b502864857d108b0e2e1184a\$lut for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut. Using template $paramod$de2b92d66e62d2468c774d4959d51c030800288f\$lut for cells of type $lut. Using template $paramod$c5ae4a26b8b7e5a6a536bdea20f9591490cb00a0\$lut for cells of type $lut. Using template $paramod$6bbecc238d553ded483f2323ce76a99b796f10c9\$lut for cells of type $lut. Using template $paramod$2cb90edbefd7638f92a4216b3809ac8b60fb0f91\$lut for cells of type $lut. Using template $paramod$ec550b5800a904067a82103907051ec480669ed0\$lut for cells of type $lut. Using template $paramod$8047a6f809c8770d17fded70c2951e9612e81e83\$lut for cells of type $lut. Using template $paramod$30f43de0d88e1950580c77ad3a0f288be4709d23\$lut for cells of type $lut. Using template $paramod$11adacc60cd4186fdee68ce9d87a6c16a5ba0864\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$ae9483265228e4e0b2c20bd8c835dd40724e466e\$lut for cells of type $lut. Using template $paramod$05cbcf47f086ea960ce7a945351e4a1d003e41b3\$lut for cells of type $lut. Using template $paramod$fb50d55974231237d52f82bc4c40ce86a760e101\$lut for cells of type $lut. Using template $paramod$46efe61198730d17c03edbd142da58f04b80bf9b\$lut for cells of type $lut. Using template $paramod$ab5f6cbda813df0763ad05c5e0cfe5a674acf259\$lut for cells of type $lut. Using template $paramod$121f66828c71d3c18a58c99e9f44b94525cfca81\$lut for cells of type $lut. Using template $paramod$4e6d8e2ee24a1884fe9908cb3a0eda7e2b1a62a3\$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. Using template $paramod$6f0547802945021e6fdc0977929ff11107937221\$lut for cells of type $lut. Using template $paramod$1f4d2a104b6f335e8e772a2d5a7e3fc719494422\$lut for cells of type $lut. Using template $paramod$2380dcfa48846b0c44a07da45467d8b1ae5c75d7\$lut for cells of type $lut. Using template $paramod$c6932d0419018208e5384761d78f0ead9bcc772f\$lut for cells of type $lut. Using template $paramod$fc735a6b7ee41acd03b3c70d70e6e1d6f5252226\$lut for cells of type $lut. Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut. Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut. Using template $paramod$d93e317e4305845c36a4846fab4f21562ddc07f3\$lut for cells of type $lut. Using template $paramod$9efeb40c2db26d2cc697d82988297f1077d5cb67\$lut for cells of type $lut. Using template $paramod$32e92861273454a2286710218400a452d7c0f8cf\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476\$lut for cells of type $lut. Using template $paramod$e5f809ec2c0443d7cc45f028e94bf65375b09f5b\$lut for cells of type $lut. Using template $paramod$dbc238cd6094d9b39dd4c26b36a773d0faa0f4a4\$lut for cells of type $lut. Using template $paramod$eea12c0b24ec4cf43fe74baafcf0fb8fc7498ed6\$lut for cells of type $lut. Using template $paramod$3f943b31daf852ed1ca222e5bb6488e4bbd6a0e6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$440c55e9b86a4d19d2d9af4513ac1f3c626292af\$lut for cells of type $lut. Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut. Using template $paramod$8d3760b3ff77c63d560cd2d77b98b57ee2135ad3\$lut for cells of type $lut. Using template $paramod$4fc6efaec5bd8994232500ce8f8be9cb357522d5\$lut for cells of type $lut. Using template $paramod$2d314d9550b6f36486216e207c2796805a009034\$lut for cells of type $lut. Using template $paramod$9d97d87b86d3f588730de47fd9f36e9d70f98a88\$lut for cells of type $lut. Using template $paramod$73d3ad4079724b80535c506a091cf6296d7d3490\$lut for cells of type $lut. Using template $paramod$4d6bebab0ab7c9b76c6ad30bbdaf715044d47fe2\$lut for cells of type $lut. Using template $paramod$3695d535bd5e07ddddab7096eefa3ec858c59e82\$lut for cells of type $lut. Using template $paramod$151cc61869e7cf4cf4bd07f6ebd8187604529cbc\$lut for cells of type $lut. Using template $paramod$1f6d79798d5d95877d7c39722aefd3ddc609f3cf\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut. Using template $paramod$6d0acfde0c3c07c438470d6539519b1a9bf419f2\$lut for cells of type $lut. Using template $paramod$cddc9c76b2a2e89a802e09ce282bf86ed986e108\$lut for cells of type $lut. Using template $paramod$e3050ab490a1a555fbe2616e0e5fd01c2350872f\$lut for cells of type $lut. Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. Using template $paramod$f6f4600e046d91e02084a6ad1e64b7879fa20eed\$lut for cells of type $lut. Using template $paramod$b36e8c789eb0e1af40fe6a99ca0350e875770d4e\$lut for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod$6ea83e8030d17877c5557192fae23916073c5d41\$lut for cells of type $lut. Using template $paramod$a878b8a67a8af65341e9a7f4162423383aba95b1\$lut for cells of type $lut. Using template $paramod$ca98655986e3ec50e137f6ef372c9087d5e1a4ca\$lut for cells of type $lut. Using template $paramod$0deb0b9fbf181987dcbbafa5608ac45f8ad453cc\$lut for cells of type $lut. Using template $paramod$775c5d2c09f1af0715d238fd589316e920592dbb\$lut for cells of type $lut. Using template $paramod$9941486833a43c3bf06ee5aedd09d646f56984bf\$lut for cells of type $lut. Using template $paramod$6b62468353a716e43972563d3074fa328b3ddcae\$lut for cells of type $lut. Using template $paramod$184cc4d1a21ffdaab9f51bd678a8002afa0d20c9\$lut for cells of type $lut. Using template $paramod$10c0209c10555dcb32a29b40e1081e27777db4ad\$lut for cells of type $lut. Using template $paramod$58dc4823ea02868b09677fc95b28c364014de1e6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. Using template $paramod$685a4d85e9d0417e8668d0b7cb7628b664b60314\$lut for cells of type $lut. Using template $paramod$d462c1036b159cddae3de55d4cd2ced9cedf9818\$lut for cells of type $lut. Using template $paramod$ed2f176f3b718a0b8bd875282f344ab5cb19a18f\$lut for cells of type $lut. Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1\$lut for cells of type $lut. Using template $paramod$89aea6f41684f26e35e028b911db0010aa348140\$lut for cells of type $lut. Using template $paramod$c20e9cdb8ce0b0008600da6cf3b4e69036652cf2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. Using template $paramod$e513324e1fc3277044dd5c18986986b74f021c77\$lut for cells of type $lut. Using template $paramod$6146b1b6231192ed81225fb31e5e76dd0f64a8e2\$lut for cells of type $lut. Using template $paramod$612a36b8ed208360b5a9f1b4119ff0e83e0a1712\$lut for cells of type $lut. Using template $paramod$9228ebb8ea9d94243fdbc23926305726086c4966\$lut for cells of type $lut. Using template $paramod$63c21a63caf7b85f1f888b02cf745b7d3944fb57\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut. Using template $paramod$0d26e42822227428593a6f2ed183ae9b22d4b575\$lut for cells of type $lut. Using template $paramod$a8a911473276b59ddac002e64b8cc2467599eec5\$lut for cells of type $lut. Using template $paramod$9b48aed7527a05741b4eea49b9111c9e1e24ef9b\$lut for cells of type $lut. Using template $paramod$0be53b8984503ac8b9e4bcbbc5fa4e4c042cbbf4\$lut for cells of type $lut. Using template $paramod$2bdcbb14b544e1a84c0f91683ebbbb6334863ca2\$lut for cells of type $lut. Using template $paramod$f87bcf1791971b4eaa30f3f28437044fef878a04\$lut for cells of type $lut. Using template $paramod$86964567e05da5df19920639abaa027ab611a230\$lut for cells of type $lut. Using template $paramod$7d813eb49700f971f2635a434700eafdfa816bc3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$89de210e11c16138f89688ab911d555676147dc8\$lut for cells of type $lut. Using template $paramod$11c86b7a6cb6e98dcfb16c5f4d4cc1052b93d8a4\$lut for cells of type $lut. Using template $paramod$977490006f4a840fd1689395e12c974fb072d2ed\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod$437ab5b4eef7bd332f6e3ba6b53b0c0d8db408c9\$lut for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod$8af87c443b78497491432cb6a477122fa6e8e8b9\$lut for cells of type $lut. Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. Using template $paramod$7f4ebac96145db16248c56cebeb420d7b29cec07\$lut for cells of type $lut. Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut. Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut. Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut. Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut. Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut. Using template $paramod$d91f2c77527e9694b85d36d0f1950ff959f1027b\$lut for cells of type $lut. Using template $paramod$ec173ef91bfbc04d4288e21a9b350ab5b41aa93e\$lut for cells of type $lut. Using template $paramod$aeb27cd9efe624def2282ecf09671da132bf31e8\$lut for cells of type $lut. Using template $paramod$35ad0309f3a755120643ff92cf0417dee37d3052\$lut for cells of type $lut. Using template $paramod$468b533db43e1d51541164934c575d48165782eb\$lut for cells of type $lut. Using template $paramod$d8d2ec1a15d3078e24fb8b00becceb654b88cff2\$lut for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut. Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f\$lut for cells of type $lut. Using template $paramod$413ecff2169cca174c4f720a30193c4f19f89c68\$lut for cells of type $lut. Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut. Using template $paramod$448496cb53eb7c1242b5786d67bd117d88f563fb\$lut for cells of type $lut. Using template $paramod$234997bee759301806c8ada31f0c044884c8f8c5\$lut for cells of type $lut. Using template $paramod$7a0b348a7069d0c8f44afe945e212fcf3f3fd64c\$lut for cells of type $lut. Using template $paramod$dd091041be455612934bb13bfe851569d81ed6b5\$lut for cells of type $lut. Using template $paramod$efc60783c939ae41b2f3555af407b17c007b27f8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut. Using template $paramod$cfca0d60a5530b0ba2f6892ecc3e0931abb488df\$lut for cells of type $lut. Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut. Using template $paramod$b5caae141dfb3c259f904e31e72e1e60d0f53123\$lut for cells of type $lut. Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. Using template $paramod$b7685cb0c8a6753256bc84bc31d36a443c15fab7\$lut for cells of type $lut. Using template $paramod$7b0d2a2ffb3b8f28d614fe2eb48a97cfa46f63f9\$lut for cells of type $lut. Using template $paramod$3fd3cd243a8b2f71b0ffe04bdaebf6ad83bcc78e\$lut for cells of type $lut. Using template $paramod$ce15874c299a587dd16825ec2d2d2759b547554e\$lut for cells of type $lut. Using template $paramod$34ccb0403abd26609d9a7a8ea9a44b40cc4b3caf\$lut for cells of type $lut. Using template $paramod$95fd88e52bdf7b75849b7ff2a7ddd0826b821d7d\$lut for cells of type $lut. Using template $paramod$3b376feceba3cbf386e5772ad57f96d9c978ae73\$lut for cells of type $lut. Using template $paramod$66f476b5322da6a457769f356c73a5789643c02f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut. Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11\$lut for cells of type $lut. Using template $paramod$1ff59098186d09c458e0f22c1d98337abecef52a\$lut for cells of type $lut. Using template $paramod$a3077fa2cf8e48a37d410abdac8a7cce2583fbf3\$lut for cells of type $lut. Using template $paramod$902ed43dcaa6101b2d051ad26600288d910a8996\$lut for cells of type $lut. Using template $paramod$4fd3428c4b8b1accf8f8fb4bb88555a2b5fa688d\$lut for cells of type $lut. Using template $paramod$855b2c1d6931bc7ac39a5e8ecd8eb6e90ffc6baf\$lut for cells of type $lut. Using template $paramod$eec1548a9d643066307b3a0c79478fd2345bc818\$lut for cells of type $lut. Using template $paramod$7b4be8d87578c2c5a0c7163e1563fb1da9910167\$lut for cells of type $lut. Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut. Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut. Using template $paramod$f840a6057f1d372c3e6a8a9fa5382749feb221f5\$lut for cells of type $lut. Using template $paramod$bb77114e0053100f1d25a6add99e03bc7709baac\$lut for cells of type $lut. Using template $paramod$a2f01eec25eb92d08608e73046bdb01195b11a42\$lut for cells of type $lut. Using template $paramod$50b346de51932b5361b03bf7cccf1f78a14220ac\$lut for cells of type $lut. Using template $paramod$532360adae43850ddbc296855a05432fb25c5f76\$lut for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$660a72f63d46a844bb0ddab189b65027c878fc6b\$lut for cells of type $lut. Using template $paramod$6e4a86e6f1a5dc8f826898a131e83cdba4a4fc9e\$lut for cells of type $lut. Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut. Using template $paramod$fd07eb7f99e54a746962fc799757bfd810aaa44c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut. Using template $paramod$547ac4d3aa2d0cc2dd61462e70e48b5e3e336609\$lut for cells of type $lut. Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut. Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut. Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut. Using template $paramod$6ffaa13445c33f3193b27ae6b9f5de8e6953d01b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut. Using template $paramod$39825c5ed3d135e502be79829033166f1762d78b\$lut for cells of type $lut. Using template $paramod$994d90e9e38bc4b3e41611c486bc42235dc97a88\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut. Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\$lut for cells of type $lut. Using template $paramod$1c7d8014a4d7918ee35a20538945662d20569ae6\$lut for cells of type $lut. Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824\$lut for cells of type $lut. Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut. Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut. Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut. Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$dd37cd23134cff028f2f6c89a8b24252334214d8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$62a1e3d9d0d18536688b76ea015149db25c5001f\$lut for cells of type $lut. Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut. Using template $paramod$d6a246575d0ba3dcbbccd768ad41b602f82ff057\$lut for cells of type $lut. Using template $paramod$e8b1383c6901b56df73ac402d78a5e0a42461be0\$lut for cells of type $lut. Using template $paramod$01b636f2759ab594c2741266b3c22685988e291c\$lut for cells of type $lut. Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut. Using template $paramod$3a25a8f1460b199f9dbf12b0e9e9b3c7361977cb\$lut for cells of type $lut. Using template $paramod$d9853ff2490df53fce5a9d4f28feefba5bd0df0e\$lut for cells of type $lut. Using template $paramod$44564e561ca97b191c1fcf64a0945d7a9a3cdd8d\$lut for cells of type $lut. Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut. Using template $paramod$d2cd5a6be592af5fc8743be1720ae2614eccb743\$lut for cells of type $lut. Using template $paramod$b72a8f2de24246ce4849a2f268af738b65f795ca\$lut for cells of type $lut. Using template $paramod$51307cdec77060d17363ea3d60427c9afef1ddc2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut. Using template $paramod$c7eaad6a588218ef0ba5a17502d003bdff2bbd3e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut. Using template $paramod$da27ce749ce856995fd279277b2a527920cae876\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. Using template $paramod$eea9f3bfa234687410071a547d41b806cab7d4e0\$lut for cells of type $lut. Using template $paramod$f77583acb34df9d57ac9134750234d5941ef8946\$lut for cells of type $lut. Using template $paramod$c4fe0d52e4fa3d649d75cb9587992cb08e44f263\$lut for cells of type $lut. Using template $paramod$4d7dc822e6ac78c7574e16060f5e26124cddca40\$lut for cells of type $lut. Using template $paramod$e4b832d686d12318ec0715f027fe549b42e45c20\$lut for cells of type $lut. Using template $paramod$3e895991b845b8c620b8c9e0068c52e372d1fbc1\$lut for cells of type $lut. Using template $paramod$4f4b8fc203f5e5f28456abb41eaf0848d148a9cd\$lut for cells of type $lut. Using template $paramod$d68c955eab3e0ff857c6b60afe14ca397531beeb\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut. Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut. Using template $paramod$325e90edf97670f9dea57833ae1f51a5e8bcddea\$lut for cells of type $lut. Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d\$lut for cells of type $lut. Using template $paramod$28631ea31bcfd68fa8733f2a19e8bea1c38b6af8\$lut for cells of type $lut. Using template $paramod$1f9991b7d220a1444c81118371531284fe6401b3\$lut for cells of type $lut. Using template $paramod$ba7c22fadfbf9ee7abcb895a21403114111dd201\$lut for cells of type $lut. Using template $paramod$bcbfb3b09702fd4745ace03c93b2e7969a3187a8\$lut for cells of type $lut. Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut. Using template $paramod$04aa8cf6303288ecfc4b6cd5e76db773783323d8\$lut for cells of type $lut. Using template $paramod$8b81775fb73b10ccf3a57c39fc26126ef8a47ddb\$lut for cells of type $lut. Using template $paramod$752ded9808d1c906ab3bd636a57258225c02b860\$lut for cells of type $lut. Using template $paramod$ef61f4d3f0b02780c975501e20e4eb9348892d57\$lut for cells of type $lut. Using template $paramod$036039c4659e4d703381df713f816c33474a7d74\$lut for cells of type $lut. Using template $paramod$7527980cd122f262063442137eba0bfa6f6d4c48\$lut for cells of type $lut. Using template $paramod$b61e0fdba4a735ed16d21e65fc617fc083973f6d\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut. Using template $paramod$221832ea6a41a3208cd6f3411a952b5811695f4c\$lut for cells of type $lut. Using template $paramod$5b845d3335908b5c4976dbc63690b6cfc712e0cf\$lut for cells of type $lut. Using template $paramod$a8f73f261b38d60c80110a0cf51da19a163ab89f\$lut for cells of type $lut. Using template $paramod$fb4ed309581bcd972f41afa8566ae8b9812c7f6c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. Using template $paramod$19e5b38cca183d8b6b3a15d20dc995c09cd71893\$lut for cells of type $lut. Using template $paramod$c506f2c444efce9b750bd027c026315e148d2023\$lut for cells of type $lut. Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut. Using template $paramod$db8d333bf66c0cdffe51960a4478272318cfbbaa\$lut for cells of type $lut. Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806\$lut for cells of type $lut. Using template $paramod$adc0b354bb960519a616db7423a6274fc380540e\$lut for cells of type $lut. Using template $paramod$ee415e17c2ba58cf57b92387964286f4c3fb39fc\$lut for cells of type $lut. Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut. Using template $paramod$c71ed138d834112b80a85f4478e2e21f72e5c48b\$lut for cells of type $lut. Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut. Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut. Using template $paramod$319ce194b2f6853993288353f3f0eda953821250\$lut for cells of type $lut. Using template $paramod$59601b4481617ef8784cc027d3c1241388c1c653\$lut for cells of type $lut. Using template $paramod$c5e9409d868ac22b0d04fa66386bddf5c7c8858c\$lut for cells of type $lut. Using template $paramod$2ec8f29aaefa9ad1d4da5302e7ba45db24c7c81c\$lut for cells of type $lut. Using template $paramod$f672f1e5ea7eaf40630014635549af40fc023a51\$lut for cells of type $lut. Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut. Using template $paramod$2b32bb54e617ed260ab04db591b24e2267923a52\$lut for cells of type $lut. Using template $paramod$53734b6248504341cde8aaff29d0e2cd855efa5a\$lut for cells of type $lut. Using template $paramod$f9ade28f1669c608093cfc771d07571aec15660d\$lut for cells of type $lut. Using template $paramod$d7816c8fe91c91c2deadbc0f27110529e1999027\$lut for cells of type $lut. Using template $paramod$f452822cad0895193e92c906a2d6170cb3736d1d\$lut for cells of type $lut. Using template $paramod$a5810b3064bbc05b2c453025774af99926f05666\$lut for cells of type $lut. Using template $paramod$89646083e67b28b097fddb409d19c5a00d8b5424\$lut for cells of type $lut. Using template $paramod$6eda15bb58da4c3830ffd6f1120bae560d82837f\$lut for cells of type $lut. Using template $paramod$c75ac5344dbecc512a68e989406d397ace07f1f8\$lut for cells of type $lut. Using template $paramod$2c65864d30076f22eb540a0df0131d6fe065cd4b\$lut for cells of type $lut. Using template $paramod$366fdab02540f832931903fdc5b997ab655b7ae0\$lut for cells of type $lut. Using template $paramod$34130a2583c0530ca8b8853e64a2a0ddd2e81d2e\$lut for cells of type $lut. Using template $paramod$857512ea84a5fe5464efcd374b77666399ea78e1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut. Using template $paramod$c66e7b215e6f80c1915bda1df6f2ae95d0bda68c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod$7ca4db46d3cd57dbe2541a389808e6d33af02319\$lut for cells of type $lut. Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut. Using template $paramod$b66783b1d2a461c9a163dcffab9aab94b30482b1\$lut for cells of type $lut. Using template $paramod$bbf8d2391d746c2af3dbc28034fca9f58de66064\$lut for cells of type $lut. Using template $paramod$02f222530db39a8a31d75f48a5f0ca4b0932388c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$8c14e6d85060218e346675600ae1194fdf5a803e\$lut for cells of type $lut. Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod$c9b834dc9c2f376b2a44311c706cb34f7f0a4014\$lut for cells of type $lut. Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c\$lut for cells of type $lut. Using template $paramod$27dd7ea71d2126c74d85758e5a06b7f432d9242f\$lut for cells of type $lut. Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut. Using template $paramod$7991e43c533565df3969b82a304afcde859daeba\$lut for cells of type $lut. Using template $paramod$2f17e1be43f3ac07ddcc5afec3b8e6a34320bd15\$lut for cells of type $lut. Using template $paramod$1787ccda58a5cc8148b54583009ad9e384e8c47e\$lut for cells of type $lut. Using template $paramod$a4bbe892a28ec0471eac4c548ab7ee6abbaf1e36\$lut for cells of type $lut. Using template $paramod$f6205ea4d16154fcc0de4d21dff0bd55a57f1ba0\$lut for cells of type $lut. Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod$5f02601f56714fedf7eba7077977bc09804bd1a4\$lut for cells of type $lut. Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut. Using template $paramod$86e4f8dc174bffe67be67c76d807ba01e8833c96\$lut for cells of type $lut. Using template $paramod$200337237619ba4c0bed9a492562f1d1b57fb569\$lut for cells of type $lut. Using template $paramod$dba07f312012fa7fd7154ebb73c28f79f08648ee\$lut for cells of type $lut. Using template $paramod$b37f456815ea21f4ae8fe81abd8ac64e904dcd02\$lut for cells of type $lut. Using template $paramod$82ed25b11a6a11eb861f4dd3d46f5fc9aa1eebaf\$lut for cells of type $lut. Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut. Using template $paramod$884ee90c6be4e5f49991ef2b3b7bf061af61648b\$lut for cells of type $lut. Using template $paramod$f43a0527e9a389b1157191d959e9086f07f7dd06\$lut for cells of type $lut. Using template $paramod$c8b5b5544248950dd31e8e8314e1a314f0de374d\$lut for cells of type $lut. Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut. Using template $paramod$9ea34eb01f9b75f8b9132856d9e5332a707924f2\$lut for cells of type $lut. Using template $paramod$5fa3c93efa758de1b949f4ff7ec9c33e1b232006\$lut for cells of type $lut. Using template $paramod$c5641d12ca62d6ba15f3fd53589c132e35178a80\$lut for cells of type $lut. Using template $paramod$b7712ad66490a50bf0f0eb1278d478652991d6c1\$lut for cells of type $lut. Using template $paramod$1fae3165af73fd57991a698f9b12667874a60281\$lut for cells of type $lut. Using template $paramod$6792bd0e885291cd8037dc0774ee2cf0027255e0\$lut for cells of type $lut. Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut. Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. Using template $paramod$b431bfd938e35871dd0b7668e1503c7e8b9d491c\$lut for cells of type $lut. Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut. Using template $paramod$3258fabf91107b4a007ae89b2246a16c31e8ae28\$lut for cells of type $lut. Using template $paramod$354f3bb6c7f817682a8a2833bc15b4473ffa6e71\$lut for cells of type $lut. Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut. Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut. Using template $paramod$1a809b3ae5f6fe79536cda9b3fec39117abdd1a2\$lut for cells of type $lut. Using template $paramod$896ed47860542f5b317e8ecb6db17e90c36ffa18\$lut for cells of type $lut. Using template $paramod$26918802e6ed329b7afdcbcae3efbad76693779f\$lut for cells of type $lut. Using template $paramod$d9c92eaa06487aaab304e6247c6379261ae37aa5\$lut for cells of type $lut. Using template $paramod$81475bdb287829ccc4f12531b677c4b473601548\$lut for cells of type $lut. Using template $paramod$7f4670b933e9d0d313fe2dbe752fa82b1cf04d5c\$lut for cells of type $lut. Using template $paramod$fe1fadedaeb6156c0ee01cb7fe4cd32590d54069\$lut for cells of type $lut. Using template $paramod$a191129d10a368b82781b98ff31865427345b51c\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut. Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut. Using template $paramod$3db826965e677cc72a454d5e910d68e35d246aa3\$lut for cells of type $lut. Using template $paramod$f8d5d066d4e5f7165e8ed9a8f737e8a8d3ad99fa\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut. Using template $paramod$1a441877fe507d6e3773ef1f291c342ba1351ff8\$lut for cells of type $lut. Using template $paramod$74c0f3179b5cebe485563ea55e9b637e7ee5c0c3\$lut for cells of type $lut. Using template $paramod$eaea85d27cc0950ed001348e061727a194f5cf9c\$lut for cells of type $lut. Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67\$lut for cells of type $lut. Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut. Using template $paramod$2d70e360329f2b83357618532825d0cf30a325f3\$lut for cells of type $lut. Using template $paramod$707701b498a5cd123a043548b93e61e0b6bdc440\$lut for cells of type $lut. Using template $paramod$e332cff882edd417f410bab5fe07a0f88572cce3\$lut for cells of type $lut. Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed\$lut for cells of type $lut. Using template $paramod$b8c12e9f20286ec99dd92b2fd58c920f7e7cec0f\$lut for cells of type $lut. Using template $paramod$a02abd7feaaac868d189a2856ea429c7022ceb43\$lut for cells of type $lut. Using template $paramod$9b8ad6ec287ad078c7ff8f3a8ca4083f5a7cb8c9\$lut for cells of type $lut. Using template $paramod$ca357517489332a2cf261ee222c33ad12293e4d5\$lut for cells of type $lut. Using template $paramod$f62bf7b9bf368c5a044dd284e6192cdfb023ea0f\$lut for cells of type $lut. Using template $paramod$43b461943b12dfb42f7a583a5559e88d7024dd00\$lut for cells of type $lut. Using template $paramod$248bbae3c20e4aaa8f9bfd919f2b92c0e7a41402\$lut for cells of type $lut. Using template $paramod$ce4ec03c44eb9f723efc2447e971d53a692885b6\$lut for cells of type $lut. Using template $paramod$f7cbd8f5974233f70d25c33ef6a692898e4f6377\$lut for cells of type $lut. Using template $paramod$94590782de849ac3f1512d9a660ffcf1af2ef7f6\$lut for cells of type $lut. Using template $paramod$18547e11c96625146c35eafd47c496890b881d03\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut. Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut. Using template $paramod$69f79d8ba7203c383d96ac8e821ddf28918012ac\$lut for cells of type $lut. Using template $paramod$903905cca899aab473483ca27c3db12d7108e3a5\$lut for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. Using template $paramod$4f18f5741816cab2d35aac6f58668ae7f485bf34\$lut for cells of type $lut. Using template $paramod$4fa9a26668e375db5ea4b1f36e0b7e0f2ece2472\$lut for cells of type $lut. Using template $paramod$eadbfb46c348c82b7975ec20f659a19c59a68112\$lut for cells of type $lut. Using template $paramod$7cbac1a3bd960f1d1684833f777a326aa3b979aa\$lut for cells of type $lut. Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut. Using template $paramod$0e7ce19e5da99c6675c7a5220f7cc55270b24ac0\$lut for cells of type $lut. Using template $paramod$48711206e3015c8ba5c8bdf766a8d500f1a5a3a4\$lut for cells of type $lut. Using template $paramod$099af7f70fcc70b41da4ec1f8df6dd0abf473cb5\$lut for cells of type $lut. Using template $paramod$f72217d55e8c28cbf17aa2ad60621cb2e1a5c998\$lut for cells of type $lut. Using template $paramod$aee74f618cbfa8e8f7bbcd8daf30bd026f2e7309\$lut for cells of type $lut. Using template $paramod$27190b166827ead7a5b229ee873e4b91ee0faf61\$lut for cells of type $lut. Using template $paramod$82a00bf0f959a345aaec45c197de61b70ee9c703\$lut for cells of type $lut. Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a\$lut for cells of type $lut. Using template $paramod$e4d8586819b0b1d9c948f388992ceb4a466c9b1a\$lut for cells of type $lut. Using template $paramod$20f9a90a9b58ed3dd945872642992a9d4f2cfd6f\$lut for cells of type $lut. Using template $paramod$726027ccd48b645c8c549794f36e8291816e7e5e\$lut for cells of type $lut. Using template $paramod$928de89363c1709229b8424c852686f29a7adbd4\$lut for cells of type $lut. Using template $paramod$4141960aebbb170b39a6f37867599c6a2713639b\$lut for cells of type $lut. Using template $paramod$0d3200f93b938cf1e34c11f3af787586726d6ff0\$lut for cells of type $lut. Using template $paramod$bccf3118124a092bb66ebea50db45c9537c9e3de\$lut for cells of type $lut. Using template $paramod$c417fb7a504830b1b376bddf306db19485172973\$lut for cells of type $lut. Using template $paramod$f7693ed52bb867c9e1efe1a997a6c51460b596a4\$lut for cells of type $lut. Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut. Using template $paramod$653ed1fca2cbea6092fc92115114dddd9158d22d\$lut for cells of type $lut. Using template $paramod$8c11a155773d2e4aba9b1022fc059160b55313e8\$lut for cells of type $lut. Using template $paramod$e6062a78edaf68ec0dbea59d4c8352dcb2ce0366\$lut for cells of type $lut. Using template $paramod$57845085f548dde890ceb6797fd0e4b4e66d8f55\$lut for cells of type $lut. Using template $paramod$5f052487744fa74eaa9d46cff4fd071cc979988f\$lut for cells of type $lut. Using template $paramod$25f4c29da5c7377f61ba4ef7ba6db95053b6905e\$lut for cells of type $lut. Using template $paramod$d7856980c8e3df62f97c26ab34037f33a9e831b5\$lut for cells of type $lut. Using template $paramod$812a4253ca4017c24f8fc639664219e9e154eb5d\$lut for cells of type $lut. Using template $paramod$1c7c470b8570da208ae80dc65e565e8e9c8f7a96\$lut for cells of type $lut. Using template $paramod$10545774f8d9e1fdfec3572ab5028aa595722911\$lut for cells of type $lut. Using template $paramod$62cb0bde107d495ad687cc3bafac2f55e5a9fd32\$lut for cells of type $lut. Using template $paramod$36e77cf68e95b3b8cccf1bb5b64409630f2c88d1\$lut for cells of type $lut. Using template $paramod$e83bf7c0c3c0d5e421dec51cce06d0c8f957c1a1\$lut for cells of type $lut. Using template $paramod$71a4e0f87a3a2969e00435e12b6f1cfce1795a4f\$lut for cells of type $lut. Using template $paramod$bfb199caef76fb241d166d9d961a064b97aed5e5\$lut for cells of type $lut. Using template $paramod$c08a774c89ef1ea6ee2ef4d8c3b071eb141d4259\$lut for cells of type $lut. Using template $paramod$734cd1512f671d92bc4f41153da0d9781801dd98\$lut for cells of type $lut. Using template $paramod$2de2d43405e1a4de9ea196e358576ef316052274\$lut for cells of type $lut. Using template $paramod$fe5b6043e65e98368b275f38e2ca7ec95af2534a\$lut for cells of type $lut. Using template $paramod$20db8e8195c71b8649e624b9f7bbe840d2be7c66\$lut for cells of type $lut. Using template $paramod$ab2d8c2b9d8aa7f76721394c261b87284f763090\$lut for cells of type $lut. Using template $paramod$d158f2a539c9d3cb6e76a9e6e7de3ce0b0b34ab9\$lut for cells of type $lut. Using template $paramod$9111d68cf2c15cd98e35433450e2eb92b679070f\$lut for cells of type $lut. Using template $paramod$2fbe21387801c1cf084ec0b8205f27d049db857d\$lut for cells of type $lut. Using template $paramod$f52df4b90f46c2ab9e801e1f39516c9cb1bb6ae7\$lut for cells of type $lut. Using template $paramod$38c832d763dbdf73a2199fbb6082c8bed38930f2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut. Using template $paramod$b60bf12111393250ce644d3bcf234c32f15777f5\$lut for cells of type $lut. Using template $paramod$081731f04a21dbe14a1e4ab9df6fa97a1c54989f\$lut for cells of type $lut. Using template $paramod$6beb19f034ba8a9f1d8164d7717f918ab32b6c19\$lut for cells of type $lut. Using template $paramod$87160e3580faf95511efd7367e30f8225a63eb41\$lut for cells of type $lut. Using template $paramod$62df6ac12ad0e629972260e5160446caf430e8e9\$lut for cells of type $lut. Using template $paramod$693ca68c8945cd675151b3b9c400517dda392982\$lut for cells of type $lut. Using template $paramod$778bf176b0d2623565ec40ed53ed2ae2b9cada5e\$lut for cells of type $lut. Using template $paramod$4b8324809148df6161610ef5b5bd73df0086e19e\$lut for cells of type $lut. Using template $paramod$2df8302c9571d3f0d6217a28dcd3251e19c0ce40\$lut for cells of type $lut. Using template $paramod$381611b500514811fb8bbbfdb6c4a52e262017a4\$lut for cells of type $lut. Using template $paramod$655e7cdf1fce9923e771969f28446489197085e2\$lut for cells of type $lut. Using template $paramod$9a4ea434ccbd1d5eaafbb86dedd857da15284084\$lut for cells of type $lut. Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8\$lut for cells of type $lut. Using template $paramod$b6bebbb9c5c57f80fe5120f7d8ba223d855d6939\$lut for cells of type $lut. Using template $paramod$9c609afe5ee491636819079add47d847f98b110f\$lut for cells of type $lut. Using template $paramod$54547f135b82f26ee65e46d936963ca9612b5d29\$lut for cells of type $lut. Using template $paramod$a6c4b96e6b1b94e2147efb879419a63581de33ca\$lut for cells of type $lut. Using template $paramod$a8be0f7a7f5ac7db2ae294a0dbc8b581353a6807\$lut for cells of type $lut. Using template $paramod$77c2a0573790d304ab2299da6d598e8d2e184867\$lut for cells of type $lut. Using template $paramod$51b138c6601401861f3f66aa30cc9212c6a6619a\$lut for cells of type $lut. Using template $paramod$bd656038040ed233e4b823cadcd55b2d8f507aa0\$lut for cells of type $lut. Using template $paramod$c3e9404bbee96227485bbf320e921a029449f50a\$lut for cells of type $lut. Using template $paramod$6375ab94b303a3f3c8d7ca6946328cb3c0b443a7\$lut for cells of type $lut. Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut. Using template $paramod$9891217114ca63a6e9d48073351d843bb1d46faf\$lut for cells of type $lut. Using template $paramod$4fa54c26ed1828223450420ca53d4097fddd10ed\$lut for cells of type $lut. Using template $paramod$853ba78e0cb8f18964f1199b616e821e74fc4676\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut. Using template $paramod$286ed3273cbe066b6afe10d043ec3b66405aa78e\$lut for cells of type $lut. Using template $paramod$a36debbcfde9e32a01ea5076ccf3d75225452c4d\$lut for cells of type $lut. Using template $paramod$f4c73d849f7d47805ca1aefb950c4e26e4eae9d0\$lut for cells of type $lut. Using template $paramod$5a1eaa80ca14df43152a6d347d05d64234d760d2\$lut for cells of type $lut. Using template $paramod$1b48bc962a0c1e178183f21032378372adc5e26c\$lut for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut. Using template $paramod$3751cff910103888107374559f35d9f1f2f94946\$lut for cells of type $lut. Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut. Using template $paramod$b943ac90d1ace5df93c1966ade0bc9c90e2a88b7\$lut for cells of type $lut. Using template $paramod$1114d560ed98e9182fe073c9893577168d869f6b\$lut for cells of type $lut. Using template $paramod$d198edb0aa72a2a2ee3d3b445b4460d9c0289c4f\$lut for cells of type $lut. Using template $paramod$06af8e98b1ee32760d0eff675cf4988d49cbfdfa\$lut for cells of type $lut. Using template $paramod$3c62f105dde711d59a52f5f1a1848aba80d4bfb2\$lut for cells of type $lut. Using template $paramod$56be3be0d09f7de8119eab1ef7402866e7a4be2c\$lut for cells of type $lut. Using template $paramod$5b03766cb9771ccdc85150fc30ea27f836aeb96a\$lut for cells of type $lut. Using template $paramod$70a6f8b5e7c26d543ee5df54b2e21d28a007a4bc\$lut for cells of type $lut. Using template $paramod$59e04c327ab279582331305d096b2b54e1d5ac0e\$lut for cells of type $lut. Using template $paramod$f628d3ba9b6b2a0c6b29d38bbe55599d07f4123b\$lut for cells of type $lut. Using template $paramod$edfdd002d369b276282ba114ad80081aeb01c009\$lut for cells of type $lut. Using template $paramod$66cfa457f3bf0a90e11a4f3cf9336b993db8c18a\$lut for cells of type $lut. Using template $paramod$f8bdf6006e1c7ec021007d9edcfa21d987c0e538\$lut for cells of type $lut. Using template $paramod$ce30f56610a96d32d91fd2f87033a828c72039e8\$lut for cells of type $lut. Using template $paramod$b83f3445232c787f29babc4885ab974d82f975d9\$lut for cells of type $lut. Using template $paramod$3764437467e0d2c156bffb0129838c3c9ec97701\$lut for cells of type $lut. Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut. Using template $paramod$fc31732417b7be9ad8ea4524b9939a4cc422dcee\$lut for cells of type $lut. Using template $paramod$cf93df6a751c015d454aef52e32716809f254f3e\$lut for cells of type $lut. Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut. Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037\$lut for cells of type $lut. Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut. Using template $paramod$09244871c4b5bfde1862f3870962d986eba7a18e\$lut for cells of type $lut. Using template $paramod$88a379586ab99d22384fb6ffdcafb4a7aae8da78\$lut for cells of type $lut. Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut. Using template $paramod$955dccdb07d87d8d9bd6e10a90269640cf31c331\$lut for cells of type $lut. Using template $paramod$704764af530ef44f2e14b5731adcdbcae46200fa\$lut for cells of type $lut. Using template $paramod$57cf7fbf84518d9e7604ec42b59ba9511e1f3caf\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut. Using template $paramod$9accec461bdf9de30d8ae592852e822e78be8a49\$lut for cells of type $lut. Using template $paramod$df009efd57e0360a9d9a6fba6fba9b2b381f2547\$lut for cells of type $lut. Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut. Using template $paramod$a6b2d4693fada6bebbe4480262641915d709d280\$lut for cells of type $lut. Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut. Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut. Using template $paramod$fe07503be663f9fa136093aa0dea361797ccf48d\$lut for cells of type $lut. Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut. Using template $paramod$accf50a247cd8bba7db1ad1f71c658b6b8d28bae\$lut for cells of type $lut. Using template $paramod$4ddd7e0638e6b5725b440c8a7420b38f19257d36\$lut for cells of type $lut. Using template $paramod$830602801e244f439802b1407aaf0cccf03608da\$lut for cells of type $lut. Using template $paramod$728e616c918eb05878d70b2bb240e381ea2847b9\$lut for cells of type $lut. Using template $paramod$0331e023d83b8009e60defb446ce9fa640b122c7\$lut for cells of type $lut. Using template $paramod$289881d2b6e6cf41a28fea810ee5b94f8ad2ea88\$lut for cells of type $lut. Using template $paramod$e5758a88c2c156ccb3037f71a73d1b15af5b310d\$lut for cells of type $lut. Using template $paramod$5a621b016c894274d07edef48c49b401a15fd796\$lut for cells of type $lut. Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut. Using template $paramod$f2df19336d959c05259151d4084b5b8bd08b836e\$lut for cells of type $lut. Using template $paramod$77eba90f08fef1f04e121480501078ac12ffbebb\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod$34536926332939882b8ff52380fffc08ed1f405f\$lut for cells of type $lut. Using template $paramod$7eab9f11ffd6f8a4fdc230bc363623954e15c1ce\$lut for cells of type $lut. Using template $paramod$4d5fa0c21aaa9745a301eda7465c650b5896bed0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. Using template $paramod$bab0ea0d717fb03593996e2a9f716c39db2520fb\$lut for cells of type $lut. Using template $paramod$8cbea7472fe8ec8b0d9b301f17edad7f1c398048\$lut for cells of type $lut. Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut. Using template $paramod$43526719abd92ef1dcf092f5ae5632bfd65b96d8\$lut for cells of type $lut. Using template $paramod$b419810ab1d51da1962917a1949cecc5f27935eb\$lut for cells of type $lut. Using template $paramod$70f68cc10fbeada9b6fa90c3bb75475e348ca467\$lut for cells of type $lut. Using template $paramod$c24d0e2a94559837d969df5b5aaf84188feaf3d8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut. Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut. Using template $paramod$b637cf4714c2e93484bb499728e176a6ab69c910\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut. Using template $paramod$9593357af708d790f5d5fb4d4c37a261c19a1c76\$lut for cells of type $lut. Using template $paramod$c6a234b1fd9b047d8452094c01e2bc4b0dcb4298\$lut for cells of type $lut. Using template $paramod$c78b28b0674e1f0605658e28384d11f25f372de7\$lut for cells of type $lut. Using template $paramod$cce6b847e730f5f1cfb4a8ef6c78f9f44e4f1145\$lut for cells of type $lut. Using template $paramod$8be603794459732f9a374f76041b510fc63b115b\$lut for cells of type $lut. Using template $paramod$e7acaad2d79ca9d6583d9edc46f9553c36f919ec\$lut for cells of type $lut. Using template $paramod$eec195054a78d1ea75a9d59c16f66aed583c2317\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. Using template $paramod$882c239751b2df23cf5dc46828a0b0262af28949\$lut for cells of type $lut. Using template $paramod$5a05aceb4b3a5e65f91bcffb0fccca72a8307af8\$lut for cells of type $lut. Using template $paramod$b18f60dfd13c21d3e472b89652353f3f5342b450\$lut for cells of type $lut. Using template $paramod$38d08dcb0f5f548ae47b9a5d4fe494c3498dd604\$lut for cells of type $lut. Using template $paramod$44236511622e197854fa4814b088d63bb24df320\$lut for cells of type $lut. Using template $paramod$9664b2f5fd61944d7798b30cde43b99ccda87303\$lut for cells of type $lut. Using template $paramod$d50aaf7bc91b84437dde85e30486261cdbeeccac\$lut for cells of type $lut. Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut. Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut. Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut. Using template $paramod$850f48dac4014f6ce06187aa7664648cd494a38b\$lut for cells of type $lut. Using template $paramod$6eaa285474ca0c16a33be004e48a6a32f35674a1\$lut for cells of type $lut. Using template $paramod$4588a4f49882bd0d469353fbcf8d94b903b1cf75\$lut for cells of type $lut. Using template $paramod$ab4188c7524eec831e9177bc675d62b21a3ccd8b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut. Using template $paramod$bf60f6ec407ee294958b6566514fc3125ec42258\$lut for cells of type $lut. Using template $paramod$6c543b558919ff57a92ac09985ad349c5934cfed\$lut for cells of type $lut. Using template $paramod$bb4fff1cc3b827238aa40993cafede1c5beecbe3\$lut for cells of type $lut. Using template $paramod$d98f7cae393e2fb5f134f7da3a0376cfdd41f123\$lut for cells of type $lut. Using template $paramod$f9b715fbf1040e81e900b2461c2390d17ed5e988\$lut for cells of type $lut. Using template $paramod$5d91ae8bf13f169f64fe2e993cae12295d19d8d3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$e098d38d00670bf1f66f3fff32b3e8f0f799bc39\$lut for cells of type $lut. Using template $paramod$ff7b4776e95c73ef189816542c3a84d65b50b8d8\$lut for cells of type $lut. Using template $paramod$17c27ffdda03355f95b2ba5edc73ca082237c935\$lut for cells of type $lut. Using template $paramod$686c3a61e478baf572ab8cdb36800066d07b2c60\$lut for cells of type $lut. Using template $paramod$fddfaafad20e385d20971828336f8fb14f3d4f32\$lut for cells of type $lut. Using template $paramod$1b5b90eea6a280f57e378b7d6f316817b9f60f1b\$lut for cells of type $lut. Using template $paramod$40935cbbff7193309e46390a22de6aecab3f8ae2\$lut for cells of type $lut. Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut. Using template $paramod$bf298935e13ec34aa997b726573dea69ee94d196\$lut for cells of type $lut. Using template $paramod$0cb239a8c56a25a1280f4f9fdbfbfe1afcf3c051\$lut for cells of type $lut. No more expansions possible. <suppressed ~13455 debug messages> 17.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in processorci_top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$26013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$26013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$26013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$26013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$26013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$26013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$25532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$25532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$25312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$25312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$25312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$25312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$25312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$25085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$25085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$25049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$24006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$24006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$24006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$24006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$24006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$23812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$22909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$22909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$22891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$22666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$22666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$21507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$21500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$21500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$20649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$20649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$20516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$20504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$20380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$19788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$19486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$19171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$18948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$18437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$18139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$18139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$18070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$18003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$18003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$18003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$17856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17761.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$17397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$17028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$17028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$17028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$17028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$17028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$16747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$16298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$15530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$15393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$15355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$15050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$14922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$14606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$14568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$14568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$14568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$14561.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14508.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$14478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$14471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$14471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$14456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$13711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$12745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$12745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$12745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$12745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$12736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$12720.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$12205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$12174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$12169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11455.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$10889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$10795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$10795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$10757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$10757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$10740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142251.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142251.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142229.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$10781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$10596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142229.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$10889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$10968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$10985.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142259.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142263.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$11687.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11087.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$11696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11721.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11800.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$11980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$11987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$12123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$12154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$12180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$12253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$12282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$12299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$12303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12333.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$12487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$12510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$12521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$12532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$12571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$12609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$12648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$12694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$12694.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$12736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$12736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$12745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$12745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$12913.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$12926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$12968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13083.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$13146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$13181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$13397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13481.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$13773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$13932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$13937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$13997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$14203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$14436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$14471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$14478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$14522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$14548.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$14606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$14626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$14897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14911.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$14927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$14948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$14989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$15195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$15195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$15211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$15242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$15271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15275.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$15361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$15368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15382.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$15398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$15419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15492.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$15785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$15951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$15967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$16133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$16233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$16278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$16278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$16288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$16367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$16382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$16386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$16390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$16447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$16580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$16688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16731.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$16747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$16754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16764.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16771.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$16816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$16925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$16944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$16998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$17028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$17036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$17434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$17794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$17867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$17996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$18003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$18003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$18010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$18208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$18278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$18313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$18330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18345.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$18412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$18442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$18463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18467.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$18589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$18607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$18678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$18695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18710.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$18752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$18888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$18988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19345.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$19357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19417.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19553.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$19689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19704.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$19886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$19956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$20191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$20328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20353.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20393.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20488.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$20603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$20649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$20931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$20983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$20999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$21055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$21139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$21156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$21199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$21268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$21322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$21373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$21495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$21500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$21507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$21668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$21908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$22034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$22068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$22085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$22173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$22247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$22284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$22298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$22454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$22460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$22473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$22490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$22508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$22595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$22725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$22799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$22806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$22823.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$22830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$22891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$22977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22989.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$22996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$23304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23860.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$23884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$23940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$24272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$24673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24699.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$24951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$25003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$25049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$25113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$25127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$25192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$25201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$25262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$25296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$25312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$25329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$25392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$aiger141871$25467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$25770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$25939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$26007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$26013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$26056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$26074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$26127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut$auto$fsm_map.cc:170:map_fsm$4378[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$auto$fsm_map.cc:170:map_fsm$4918[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$22226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$21268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut$auto$opt_dff.cc:219:make_patterns_logic$5400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$auto$opt_dff.cc:219:make_patterns_logic$5489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$auto$opt_dff.cc:219:make_patterns_logic$5679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut$auto$opt_dff.cc:219:make_patterns_logic$5410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$flatten\Controller.\Interpreter.$procmux$2002.Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$23265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Controller.Memory.write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut\Controller.Memory.write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$25055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$aiger141871$24006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut\Controller.Memory.write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$141872$lut$auto$fsm_map.cc:170:map_fsm$3741[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$141872$lut\Controller.Memory.write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut$aiger141871$23812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut\Controller.Memory.write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$19179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut\Riscado_V.registerFile.dataIn[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141893.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141882.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141985.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141993.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142013.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142053.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142067.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$141872$lut$aiger141871$12759.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142229.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142251.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142257.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Removed 0 unused cells and 15163 unused wires. 17.45. Executing AUTONAME pass. Renamed 432681 objects in module processorci_top (247 iterations). <suppressed ~18931 debug messages> 17.46. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `processorci_top'. Setting top module to processorci_top. 17.46.1. Analyzing design hierarchy.. Top module: \processorci_top 17.46.2. Analyzing design hierarchy.. Top module: \processorci_top Removed 0 unused modules. Module processorci_top directly or indirectly displays text -> setting "keep" attribute. 17.47. Printing statistics. === processorci_top === Number of wires: 8855 Number of wire bits: 24231 Number of public wires: 8855 Number of public wire bits: 24231 Number of ports: 10 Number of port bits: 10 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 11401 $print 11 $scopeinfo 21 CCU2C 236 L6MUX21 515 LUT4 7198 PFUMX 1555 TRELLIS_DPR16X4 1060 TRELLIS_FF 805 17.48. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Found and reported 0 problems. 17.49. Executing JSON backend. Warnings: 35 unique messages, 35 total End of script. Logfile hash: 9e70061d5b, CPU: user 51.36s system 0.28s, MEM: 323.42 MB peak Time spent: 40% 1x abc9_exe (20 sec), 12% 11x techmap (6 sec), ... /eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \ --lpf /eda/processor_ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \ --speed 6 --lpf-allow-unconstrained --ignore-loops /eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config --bit colorlight_i9.bit [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) [Pipeline] dir Running in /var/jenkins_home/workspace/riscado-v/riscado-v [Pipeline] { [Pipeline] echo Flashing FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b colorlight_i9 -l Final configuration file generated at /var/jenkins_home/workspace/riscado-v/riscado-v/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 (null) Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE Loading: [==== ] 7.39% Loading: [======== ] 14.78% Loading: [============ ] 22.18% Loading: [=============== ] 29.57% Loading: [=================== ] 37.25% Loading: [======================= ] 44.64% Loading: [=========================== ] 52.03% Loading: [============================== ] 59.42% Loading: [================================== ] 66.81% Loading: [====================================== ] 74.21% Loading: [========================================= ] 81.60% Loading: [============================================= ] 88.99% Loading: [================================================= ] 96.67% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test colorlight_i9) [Pipeline] echo Testing FPGA colorlight_i9. [Pipeline] dir Running in /var/jenkins_home/workspace/riscado-v/riscado-v [Pipeline] { [Pipeline] sh + echo Test for FPGA in /dev/ttyACM0 Test for FPGA in /dev/ttyACM0 [Pipeline] sh + python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0 Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'} [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Final configuration file generated at /var/jenkins_home/workspace/riscado-v/riscado-v/build_digilent_arty_a7_100t.tcl Makefile executed successfully. Makefile output: Building the Design... /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/riscado-v/riscado-v/build_digilent_arty_a7_100t.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096" ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source /var/jenkins_home/workspace/riscado-v/riscado-v/build_digilent_arty_a7_100t.tcl # read_verilog /var/jenkins_home/workspace/riscado-v/riscado-v/alu.v read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1318.535 ; gain = 0.023 ; free physical = 1523 ; free virtual = 24385 # read_verilog /var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v # read_verilog /var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v # read_verilog /var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v # read_verilog /var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v # read_verilog /var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v # read_verilog /eda/processor_ci/rtl/riscado-v.v # read_verilog /eda/processor-ci-controller/modules/uart.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v # read_verilog /eda/processor-ci-controller/src/fifo.v # read_verilog /eda/processor-ci-controller/src/reset.v # read_verilog /eda/processor-ci-controller/src/clk_divider.v # read_verilog /eda/processor-ci-controller/src/memory.v # read_verilog /eda/processor-ci-controller/src/interpreter.v # read_verilog /eda/processor-ci-controller/src/controller.v # set ID [lindex $argv 0] # set CLOCK_FREQ [lindex $argv 1] # set MEMORY_SIZE [lindex $argv 2] # set HIGH_CLK 1 # read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc" # set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] # synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE \ # -verilog_define $HIGH_CLK Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096 -verilog_define 1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 3507085 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2032.203 ; gain = 403.629 ; free physical = 543 ; free virtual = 23405 --------------------------------------------------------------------------------- CRITICAL WARNING: [Synth 8-9339] data object 'reset_o' is already declared [/eda/processor_ci/rtl/riscado-v.v:142] INFO: [Synth 8-6826] previous declaration of 'reset_o' is from here [/eda/processor_ci/rtl/riscado-v.v:29] CRITICAL WARNING: [Synth 8-11152] second declaration of 'reset_o' is ignored [/eda/processor_ci/rtl/riscado-v.v:142] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16] WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15] WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16] WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17] WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84] WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85] INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/riscado-v.v:1] INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer Parameter ID bound to: 0 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1] Parameter COUNTER_BITS bound to: 32 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1] INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter ID bound to: 0 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213] INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1] Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1] INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1] INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1] Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1] WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268] INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1] INFO: [Synth 8-6157] synthesizing module 'RISCV' [/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:7] INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:7] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:256] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:298] INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (0#1) [/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:7] INFO: [Synth 8-6157] synthesizing module 'LoadStore' [/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:60] INFO: [Synth 8-6157] synthesizing module 'ByteWriter' [/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:35] INFO: [Synth 8-6155] done synthesizing module 'ByteWriter' (0#1) [/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:35] INFO: [Synth 8-6157] synthesizing module 'HalfWriter' [/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:47] INFO: [Synth 8-6155] done synthesizing module 'HalfWriter' (0#1) [/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:47] INFO: [Synth 8-6157] synthesizing module 'ByteReader' [/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:8] INFO: [Synth 8-6155] done synthesizing module 'ByteReader' (0#1) [/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:8] INFO: [Synth 8-6157] synthesizing module 'HalfReader' [/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:22] INFO: [Synth 8-6155] done synthesizing module 'HalfReader' (0#1) [/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:22] INFO: [Synth 8-6155] done synthesizing module 'LoadStore' (0#1) [/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:60] INFO: [Synth 8-6157] synthesizing module 'RegisterFile' [/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:5] INFO: [Synth 8-6155] done synthesizing module 'RegisterFile' (0#1) [/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:5] INFO: [Synth 8-6157] synthesizing module 'ProgramCounter' [/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:5] INFO: [Synth 8-6155] done synthesizing module 'ProgramCounter' (0#1) [/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:5] INFO: [Synth 8-6157] synthesizing module 'ALU' [/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:7] INFO: [Synth 8-6155] done synthesizing module 'ALU' (0#1) [/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:7] INFO: [Synth 8-6155] done synthesizing module 'RISCV' (0#1) [/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:7] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1] Parameter CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1] WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/riscado-v.v:146] WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/riscado-v.v:146] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/riscado-v.v:146] INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/riscado-v.v:1] WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25] WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/riscado-v.v:21] WARNING: [Synth 8-7129] Port dataIn[31] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[30] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[29] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[28] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[27] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[26] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[25] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[24] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[23] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[22] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[21] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[20] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[19] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[18] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[17] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[16] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[15] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[14] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[13] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[12] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[11] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[10] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[9] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[8] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[7] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[6] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[5] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[4] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[3] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[2] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[1] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[0] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[24] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[23] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[22] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[21] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[20] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[19] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[18] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[17] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[16] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[15] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[11] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[10] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[9] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[8] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port ir[7] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2135.141 ; gain = 506.566 ; free physical = 429 ; free virtual = 23291 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2152.953 ; gain = 524.379 ; free physical = 425 ; free virtual = 23288 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2152.953 ; gain = 524.379 ; free physical = 425 ; free virtual = 23288 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2152.953 ; gain = 0.000 ; free physical = 424 ; free virtual = 23286 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2306.703 ; gain = 0.000 ; free physical = 404 ; free virtual = 23266 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2306.738 ; gain = 0.000 ; free physical = 399 ; free virtual = 23261 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 405 ; free virtual = 23267 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 405 ; free virtual = 23267 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 405 ; free virtual = 23267 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 READ | 001 | 0001 COPY_READ_BUFFER | 010 | 0100 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 COPY_WRITE_BUFFER | 001 | 0100 WRITE | 010 | 0001 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 0001 | 00 iSTATE0 | 0010 | 01 iSTATE1 | 0100 | 10 iSTATE2 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RESET_COUNTER | 00 | 01 IDLE | 01 | 10 INIT | 10 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 393 ; free virtual = 23256 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 2 2 Input 32 Bit Adders := 7 3 Input 32 Bit Adders := 1 2 Input 24 Bit Adders := 2 2 Input 10 Bit Adders := 2 2 Input 8 Bit Adders := 1 2 Input 6 Bit Adders := 4 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---XORs : 2 Input 32 Bit XORs := 1 +---Registers : 64 Bit Registers := 2 32 Bit Registers := 15 24 Bit Registers := 5 10 Bit Registers := 2 8 Bit Registers := 11 6 Bit Registers := 1 4 Bit Registers := 3 3 Bit Registers := 3 2 Bit Registers := 4 1 Bit Registers := 36 +---RAMs : 32K Bit (1024 X 32 bit) RAMs := 2 1024 Bit (32 X 32 bit) RAMs := 1 64 Bit (8 X 8 bit) RAMs := 2 +---Muxes : 4 Input 64 Bit Muxes := 1 2 Input 64 Bit Muxes := 1 48 Input 64 Bit Muxes := 2 2 Input 32 Bit Muxes := 23 5 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 3 48 Input 24 Bit Muxes := 1 2 Input 16 Bit Muxes := 2 48 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 4 4 Input 8 Bit Muxes := 1 24 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 2 2 Input 6 Bit Muxes := 4 3 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 7 8 Input 4 Bit Muxes := 1 9 Input 4 Bit Muxes := 1 7 Input 4 Bit Muxes := 1 6 Input 4 Bit Muxes := 1 5 Input 3 Bit Muxes := 4 2 Input 3 Bit Muxes := 17 10 Input 3 Bit Muxes := 1 9 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 2 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 26 48 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 4 3 Input 2 Bit Muxes := 2 7 Input 2 Bit Muxes := 2 5 Input 2 Bit Muxes := 2 6 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 114 48 Input 1 Bit Muxes := 22 3 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 8 5 Input 1 Bit Muxes := 11 10 Input 1 Bit Muxes := 5 6 Input 1 Bit Muxes := 5 9 Input 1 Bit Muxes := 4 7 Input 1 Bit Muxes := 2 8 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met WARNING: [Synth 8-7129] Port dataIn[31] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[30] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[29] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[28] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[27] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[26] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[25] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[24] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[23] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[22] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[21] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[20] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[19] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[18] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[17] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[16] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[15] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[14] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[13] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[12] in module ControlUnit is either unconnected or has no load WARNING: [Synth 8-7129] Port dataIn[11] in module ControlUnit is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:11 ; elapsed = 00:01:13 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 361 ; free virtual = 23231 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------+---------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+---------------------+---------------+----------------+ |Interpreter | memory_mux_selector | 256x1 | LUT | |Interpreter | memory_mux_selector | 256x1 | LUT | +------------+---------------------+---------------+----------------+ Distributed RAM: Preliminary Mapping Report (see note below) +------------+----------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+----------------------------+-----------+----------------------+------------------+ |Controller | Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |Controller | Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |Riscado_V | registerFile/registers_reg | Implied | 32 x 32 | RAM32M x 12 | +------------+----------------------------+-----------+----------------------+------------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 360 ; free virtual = 23231 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:48 ; elapsed = 00:01:50 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 179 ; free virtual = 23220 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------+----------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+----------------------------+-----------+----------------------+------------------+ |Controller | Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |Controller | Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |Controller | Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |Riscado_V | registerFile/registers_reg | Implied | 32 x 32 | RAM32M x 12 | +------------+----------------------------+-----------+----------------------+------------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:01:52 ; elapsed = 00:01:54 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 190 ; free virtual = 23220 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:02:03 ; elapsed = 00:02:04 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 187 ; free virtual = 23217 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:02:03 ; elapsed = 00:02:05 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 187 ; free virtual = 23217 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:04 ; elapsed = 00:02:06 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 192 ; free virtual = 23222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:02:04 ; elapsed = 00:02:06 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 192 ; free virtual = 23222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:02:04 ; elapsed = 00:02:06 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 192 ; free virtual = 23222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:02:04 ; elapsed = 00:02:06 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 192 ; free virtual = 23222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 2| |2 |CARRY4 | 108| |3 |LUT1 | 34| |4 |LUT2 | 242| |5 |LUT3 | 409| |6 |LUT4 | 245| |7 |LUT5 | 364| |8 |LUT6 | 858| |9 |MUXF7 | 75| |10 |RAM256X1S | 256| |11 |RAM32M | 12| |12 |RAM32X1D | 8| |13 |FDRE | 785| |14 |FDSE | 7| |15 |IBUF | 2| |16 |OBUF | 1| |17 |OBUFT | 2| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:02:04 ; elapsed = 00:02:06 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 192 ; free virtual = 23222 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 80 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:01:59 ; elapsed = 00:02:01 . Memory (MB): peak = 2306.738 ; gain = 524.379 ; free physical = 192 ; free virtual = 23222 Synthesis Optimization Complete : Time (s): cpu = 00:02:05 ; elapsed = 00:02:06 . Memory (MB): peak = 2306.738 ; gain = 678.164 ; free physical = 192 ; free virtual = 23222 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2306.738 ; gain = 0.000 ; free physical = 470 ; free virtual = 23500 INFO: [Netlist 29-17] Analyzing 459 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2370.734 ; gain = 0.000 ; free physical = 473 ; free virtual = 23503 INFO: [Project 1-111] Unisim Transformation Summary: A total of 276 instances were transformed. RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 12 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 8 instances Synth Design complete | Checksum: 34d8cef3 INFO: [Common 17-83] Releasing license: Synthesis 72 Infos, 119 Warnings, 4 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:02:23 ; elapsed = 00:02:20 . Memory (MB): peak = 2370.770 ; gain = 1052.234 ; free physical = 472 ; free virtual = 23503 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2075.719; main = 1782.746; forked = 435.255 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3257.027; main = 2370.738; forked = 982.336 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2434.766 ; gain = 63.996 ; free physical = 351 ; free virtual = 23382 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 13547d605 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2526.578 ; gain = 91.812 ; free physical = 423 ; free virtual = 23453 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 13547d605 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2771.516 ; gain = 0.000 ; free physical = 170 ; free virtual = 23178 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 13547d605 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2771.516 ; gain = 0.000 ; free physical = 170 ; free virtual = 23178 Phase 1 Initialization | Checksum: 13547d605 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2771.516 ; gain = 0.000 ; free physical = 170 ; free virtual = 23178 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 13547d605 Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2771.516 ; gain = 0.000 ; free physical = 169 ; free virtual = 23178 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 13547d605 Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2771.516 ; gain = 0.000 ; free physical = 169 ; free virtual = 23178 Phase 2 Timer Update And Timing Data Collection | Checksum: 13547d605 Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2771.516 ; gain = 0.000 ; free physical = 169 ; free virtual = 23178 Phase 3 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 1a698c3ff Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.7 . Memory (MB): peak = 2771.516 ; gain = 0.000 ; free physical = 169 ; free virtual = 23178 Retarget | Checksum: 1a698c3ff INFO: [Opt 31-389] Phase Retarget created 1 cells and removed 1 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 1f8f2149c Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.8 . Memory (MB): peak = 2771.516 ; gain = 0.000 ; free physical = 169 ; free virtual = 23178 Constant propagation | Checksum: 1f8f2149c INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 1559abc03 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.94 . Memory (MB): peak = 2771.516 ; gain = 0.000 ; free physical = 169 ; free virtual = 23178 Sweep | Checksum: 1559abc03 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 1559abc03 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2803.531 ; gain = 32.016 ; free physical = 169 ; free virtual = 23178 BUFG optimization | Checksum: 1559abc03 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 1559abc03 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2803.531 ; gain = 32.016 ; free physical = 169 ; free virtual = 23178 Shift Register Optimization | Checksum: 1559abc03 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 1559abc03 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2803.531 ; gain = 32.016 ; free physical = 169 ; free virtual = 23178 Post Processing Netlist | Checksum: 1559abc03 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 190840547 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2803.531 ; gain = 32.016 ; free physical = 169 ; free virtual = 23178 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2803.531 ; gain = 0.000 ; free physical = 169 ; free virtual = 23178 Phase 9.2 Verifying Netlist Connectivity | Checksum: 190840547 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2803.531 ; gain = 32.016 ; free physical = 169 ; free virtual = 23178 Phase 9 Finalization | Checksum: 190840547 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2803.531 ; gain = 32.016 ; free physical = 169 ; free virtual = 23178 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 1 | 1 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 190840547 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2803.531 ; gain = 32.016 ; free physical = 169 ; free virtual = 23178 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.531 ; gain = 0.000 ; free physical = 169 ; free virtual = 23178 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 190840547 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2803.531 ; gain = 0.000 ; free physical = 169 ; free virtual = 23178 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 190840547 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2803.531 ; gain = 0.000 ; free physical = 169 ; free virtual = 23178 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.531 ; gain = 0.000 ; free physical = 169 ; free virtual = 23178 Ending Netlist Obfuscation Task | Checksum: 190840547 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.531 ; gain = 0.000 ; free physical = 169 ; free virtual = 23178 INFO: [Common 17-83] Releasing license: Implementation 18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 2803.531 ; gain = 432.762 ; free physical = 169 ; free virtual = 23178 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.547 ; gain = 0.000 ; free physical = 181 ; free virtual = 23172 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3588040 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2835.547 ; gain = 0.000 ; free physical = 181 ; free virtual = 23172 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.547 ; gain = 0.000 ; free physical = 181 ; free virtual = 23172 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 97f38989 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2835.547 ; gain = 0.000 ; free physical = 186 ; free virtual = 23177 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 16f94a29e Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 194 ; free virtual = 23184 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 16f94a29e Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 194 ; free virtual = 23184 Phase 1 Placer Initialization | Checksum: 16f94a29e Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 194 ; free virtual = 23184 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: a1193bad Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 200 ; free virtual = 23191 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: f01e559b Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 194 ; free virtual = 23185 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: f01e559b Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 194 ; free virtual = 23185 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 182a00b7a Time (s): cpu = 00:00:58 ; elapsed = 00:00:35 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 176 ; free virtual = 23166 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 42 LUTNM shape to break, 85 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 4, two critical 38, total 42, new lutff created 2 INFO: [Physopt 32-1138] End 1 Pass. Optimized 82 nets or LUTs. Breaked 42 LUTs, combined 40 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.574 ; gain = 0.000 ; free physical = 175 ; free virtual = 23165 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 42 | 40 | 82 | 0 | 1 | 00:00:01 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 42 | 40 | 82 | 0 | 9 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1a5924c48 Time (s): cpu = 00:01:01 ; elapsed = 00:00:38 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 166 ; free virtual = 23157 Phase 2.4 Global Placement Core | Checksum: 15b642fdf Time (s): cpu = 00:01:36 ; elapsed = 00:00:56 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 183 ; free virtual = 23174 Phase 2 Global Placement | Checksum: 15b642fdf Time (s): cpu = 00:01:36 ; elapsed = 00:00:56 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 183 ; free virtual = 23173 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 142f97e92 Time (s): cpu = 00:01:38 ; elapsed = 00:00:58 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 183 ; free virtual = 23173 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 203ac3648 Time (s): cpu = 00:01:44 ; elapsed = 00:01:02 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 178 ; free virtual = 23168 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 260a19483 Time (s): cpu = 00:01:44 ; elapsed = 00:01:02 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 181 ; free virtual = 23171 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1976179d4 Time (s): cpu = 00:01:44 ; elapsed = 00:01:02 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 181 ; free virtual = 23171 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 18c5ec685 Time (s): cpu = 00:02:00 ; elapsed = 00:01:15 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 188 ; free virtual = 23178 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 1badb663c Time (s): cpu = 00:02:03 ; elapsed = 00:01:18 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 184 ; free virtual = 23174 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 1f39c763e Time (s): cpu = 00:02:03 ; elapsed = 00:01:18 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 184 ; free virtual = 23174 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 249e1cc08 Time (s): cpu = 00:02:03 ; elapsed = 00:01:18 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 184 ; free virtual = 23174 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: eacdae09 Time (s): cpu = 00:02:27 ; elapsed = 00:01:39 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 170 ; free virtual = 23161 Phase 3 Detail Placement | Checksum: eacdae09 Time (s): cpu = 00:02:27 ; elapsed = 00:01:39 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 166 ; free virtual = 23156 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1237d6031 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-7.431 | TNS=-15634.119 | Phase 1 Physical Synthesis Initialization | Checksum: 159ca67f4 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2842.574 ; gain = 0.000 ; free physical = 182 ; free virtual = 23173 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 159ca67f4 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2842.574 ; gain = 0.000 ; free physical = 175 ; free virtual = 23165 Phase 4.1.1.1 BUFG Insertion | Checksum: 1237d6031 Time (s): cpu = 00:02:35 ; elapsed = 00:01:44 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 170 ; free virtual = 23161 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=-5.985. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1fa128d88 Time (s): cpu = 00:04:22 ; elapsed = 00:03:30 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 693 ; free virtual = 23645 Time (s): cpu = 00:04:22 ; elapsed = 00:03:30 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 693 ; free virtual = 23645 Phase 4.1 Post Commit Optimization | Checksum: 1fa128d88 Time (s): cpu = 00:04:22 ; elapsed = 00:03:30 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 695 ; free virtual = 23647 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1fa128d88 Time (s): cpu = 00:04:22 ; elapsed = 00:03:30 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 692 ; free virtual = 23644 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 2x2| |___________|___________________|___________________| | East| 1x1| 2x2| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1fa128d88 Time (s): cpu = 00:04:23 ; elapsed = 00:03:30 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 693 ; free virtual = 23645 Phase 4.3 Placer Reporting | Checksum: 1fa128d88 Time (s): cpu = 00:04:23 ; elapsed = 00:03:30 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 691 ; free virtual = 23643 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.574 ; gain = 0.000 ; free physical = 691 ; free virtual = 23643 Time (s): cpu = 00:04:23 ; elapsed = 00:03:30 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 691 ; free virtual = 23643 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d6e32e7b Time (s): cpu = 00:04:23 ; elapsed = 00:03:30 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 691 ; free virtual = 23643 Ending Placer Task | Checksum: e194d5b4 Time (s): cpu = 00:04:23 ; elapsed = 00:03:31 . Memory (MB): peak = 2842.574 ; gain = 7.027 ; free physical = 688 ; free virtual = 23640 37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:04:25 ; elapsed = 00:03:32 . Memory (MB): peak = 2842.574 ; gain = 39.043 ; free physical = 694 ; free virtual = 23646 # report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt # report_utilization -file digilent_arty_a7_utilization_place.rpt # report_io -file digilent_arty_a7_io.rpt report_io: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2842.574 ; gain = 0.000 ; free physical = 695 ; free virtual = 23647 # report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2842.574 ; gain = 0.000 ; free physical = 695 ; free virtual = 23647 # report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: 8f9de23d ConstDB: 0 ShapeSum: 51f6f377 RouteDB: 0 Post Restoration Checksum: NetGraph: f1f4200a | NumContArr: 198e180 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 278def6c4 Time (s): cpu = 00:01:19 ; elapsed = 00:01:10 . Memory (MB): peak = 2842.574 ; gain = 0.000 ; free physical = 663 ; free virtual = 23615 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 278def6c4 Time (s): cpu = 00:01:19 ; elapsed = 00:01:10 . Memory (MB): peak = 2842.574 ; gain = 0.000 ; free physical = 668 ; free virtual = 23620 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 278def6c4 Time (s): cpu = 00:01:19 ; elapsed = 00:01:10 . Memory (MB): peak = 2842.574 ; gain = 0.000 ; free physical = 668 ; free virtual = 23620 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2ccad1389 Time (s): cpu = 00:01:29 ; elapsed = 00:01:15 . Memory (MB): peak = 2842.574 ; gain = 0.000 ; free physical = 634 ; free virtual = 23586 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.575 | TNS=-5089.677| WHS=-0.597 | THS=-75.833| Router Utilization Summary Global Vertical Routing Utilization = 0.0111851 % Global Horizontal Routing Utilization = 0.00625178 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 2608 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 2572 Number of Partially Routed Nets = 36 Number of Node Overlaps = 35 Phase 2 Router Initialization | Checksum: 30c8e7a0b Time (s): cpu = 00:01:33 ; elapsed = 00:01:17 . Memory (MB): peak = 2842.574 ; gain = 0.000 ; free physical = 634 ; free virtual = 23587 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 30c8e7a0b Time (s): cpu = 00:01:33 ; elapsed = 00:01:17 . Memory (MB): peak = 2842.574 ; gain = 0.000 ; free physical = 634 ; free virtual = 23587 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 18dce96e3 Time (s): cpu = 00:01:48 ; elapsed = 00:01:23 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 512 ; free virtual = 23464 Phase 3 Initial Routing | Checksum: 18dce96e3 Time (s): cpu = 00:01:48 ; elapsed = 00:01:23 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 512 ; free virtual = 23464 INFO: [Route 35-580] Design has 109 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +====================+===================+============================================================+ | Launch Setup Clock | Launch Hold Clock | Pin | +====================+===================+============================================================+ | sys_clk_pin | sys_clk_pin | Riscado_V/ir_reg[23]/D | | sys_clk_pin | sys_clk_pin | Riscado_V/registerFile/registers_reg_r1_0_31_0_5/RAMA_D1/I | | sys_clk_pin | sys_clk_pin | Riscado_V/registerFile/registers_reg_r2_0_31_0_5/RAMA_D1/I | | sys_clk_pin | sys_clk_pin | Riscado_V/ir_reg[31]/D | | sys_clk_pin | sys_clk_pin | Riscado_V/registerFile/registers_reg_r2_0_31_30_31/SP/I | +--------------------+-------------------+------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 1147 Number of Nodes with overlaps = 223 Number of Nodes with overlaps = 110 Number of Nodes with overlaps = 63 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-7.049 | TNS=-13574.186| WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 343cca4f4 Time (s): cpu = 00:02:42 ; elapsed = 00:02:08 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 487 ; free virtual = 23275 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 135 Number of Nodes with overlaps = 93 Number of Nodes with overlaps = 80 Number of Nodes with overlaps = 54 Number of Nodes with overlaps = 46 Number of Nodes with overlaps = 27 Number of Nodes with overlaps = 22 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-6.795 | TNS=-12543.307| WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 2122eed3e Time (s): cpu = 00:03:52 ; elapsed = 00:03:14 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 427 ; free virtual = 23216 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 179 Number of Nodes with overlaps = 317 Number of Nodes with overlaps = 167 Number of Nodes with overlaps = 119 Number of Nodes with overlaps = 96 Number of Nodes with overlaps = 73 Number of Nodes with overlaps = 43 Number of Nodes with overlaps = 26 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-6.403 | TNS=-11484.967| WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 2231c26b0 Time (s): cpu = 00:04:28 ; elapsed = 00:03:41 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 226 ; free virtual = 23016 Phase 4.4 Global Iteration 3 Number of Nodes with overlaps = 365 Number of Nodes with overlaps = 197 Number of Nodes with overlaps = 158 Number of Nodes with overlaps = 114 Number of Nodes with overlaps = 61 Number of Nodes with overlaps = 41 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 27 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-6.215 | TNS=-9809.238| WHS=N/A | THS=N/A | Phase 4.4 Global Iteration 3 | Checksum: 2ad559f66 Time (s): cpu = 00:05:09 ; elapsed = 00:04:14 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 243 ; free virtual = 23035 Phase 4.5 Global Iteration 4 Number of Nodes with overlaps = 694 Number of Nodes with overlaps = 289 Number of Nodes with overlaps = 137 Number of Nodes with overlaps = 100 Number of Nodes with overlaps = 43 Number of Nodes with overlaps = 28 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-6.257 | TNS=-10227.860| WHS=N/A | THS=N/A | Phase 4.5 Global Iteration 4 | Checksum: 2254cb509 Time (s): cpu = 00:05:44 ; elapsed = 00:04:39 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 234 ; free virtual = 23026 Phase 4 Rip-up And Reroute | Checksum: 2254cb509 Time (s): cpu = 00:05:44 ; elapsed = 00:04:39 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 234 ; free virtual = 23026 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 1d0fc3553 Time (s): cpu = 00:05:46 ; elapsed = 00:04:40 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 232 ; free virtual = 23024 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-6.215 | TNS=-9797.584| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 25d6b96d8 Time (s): cpu = 00:05:47 ; elapsed = 00:04:41 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 232 ; free virtual = 23024 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 25d6b96d8 Time (s): cpu = 00:05:47 ; elapsed = 00:04:41 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 232 ; free virtual = 23024 Phase 5 Delay and Skew Optimization | Checksum: 25d6b96d8 Time (s): cpu = 00:05:47 ; elapsed = 00:04:41 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 232 ; free virtual = 23024 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1fed6588e Time (s): cpu = 00:05:50 ; elapsed = 00:04:43 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 231 ; free virtual = 23023 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-6.215 | TNS=-9756.232| WHS=0.042 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 1cbf7a154 Time (s): cpu = 00:05:50 ; elapsed = 00:04:43 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 231 ; free virtual = 23023 Phase 6 Post Hold Fix | Checksum: 1cbf7a154 Time (s): cpu = 00:05:50 ; elapsed = 00:04:43 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 231 ; free virtual = 23023 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 1.03094 % Global Horizontal Routing Utilization = 1.368 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report North Dir 1x1 Area, Max Cong = 67.5676%, No Congested Regions. South Dir 1x1 Area, Max Cong = 58.5586%, No Congested Regions. East Dir 1x1 Area, Max Cong = 77.9412%, No Congested Regions. West Dir 1x1 Area, Max Cong = 75%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 7 Route finalize | Checksum: 1cbf7a154 Time (s): cpu = 00:05:50 ; elapsed = 00:04:43 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 231 ; free virtual = 23023 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1cbf7a154 Time (s): cpu = 00:05:50 ; elapsed = 00:04:43 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 231 ; free virtual = 23023 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 282ebd081 Time (s): cpu = 00:05:52 ; elapsed = 00:04:44 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 231 ; free virtual = 23023 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=-6.215 | TNS=-9756.232| WHS=0.042 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 10 Post Router Timing | Checksum: 282ebd081 Time (s): cpu = 00:05:54 ; elapsed = 00:04:45 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 227 ; free virtual = 23019 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 1a2493398 Time (s): cpu = 00:05:54 ; elapsed = 00:04:46 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 222 ; free virtual = 23014 Ending Routing Task | Checksum: 1a2493398 Time (s): cpu = 00:05:54 ; elapsed = 00:04:46 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 225 ; free virtual = 23017 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 17 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:05:57 ; elapsed = 00:04:48 . Memory (MB): peak = 2927.559 ; gain = 84.984 ; free physical = 228 ; free virtual = 23020 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (1) 6. checking no_output_delay (1) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (1) ------------------------------ There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (1) ------------------------------- There is 1 port with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -6.215 -9658.051 5290 12934 0.042 0.000 0 12934 3.750 0.000 0 1930 Timing constraints are not met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sck {0.000 50.000} 100.000 10.000 sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin -6.215 -9658.051 5290 12934 0.042 0.000 0 12934 3.750 0.000 0 1930 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_arty_a7_route_status.rpt # report_drc -file digilent_arty_a7_drc.rpt Command: report_drc -file digilent_arty_a7_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/riscado-v/riscado-v/digilent_arty_a7_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_arty_a7_power.rpt Command: report_power -file digilent_arty_a7_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "digilent_arty_a7_100t.bit" Command: write_bitstream -force digilent_arty_a7_100t.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./digilent_arty_a7_100t.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 3162.629 ; gain = 147.008 ; free physical = 165 ; free virtual = 22786 # exit INFO: [Common 17-206] Exiting Vivado at Fri Apr 4 23:16:04 2025... [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) [Pipeline] dir Running in /var/jenkins_home/workspace/riscado-v/riscado-v [Pipeline] { [Pipeline] echo Flashing FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b digilent_arty_a7_100t -l Final configuration file generated at /var/jenkins_home/workspace/riscado-v/riscado-v/build_digilent_arty_a7_100t.tcl Makefile executed successfully. Makefile output: Flashing the FPGA... /eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit empty Jtag frequency : requested 10.00MHz -> real 10.00MHz Open file DONE Parse file DONE load program Load SRAM: [=============== ] 30.00% Load SRAM: [=============================== ] 61.00% Load SRAM: [============================================== ] 92.00% Load SRAM: [===================================================] 100.00% Done Shift IR 35 ir: 1 isc_done 1 isc_ena 0 init 1 done 1 [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) [Pipeline] echo Testing FPGA digilent_arty_a7_100t. [Pipeline] dir Running in /var/jenkins_home/workspace/riscado-v/riscado-v [Pipeline] { [Pipeline] sh + echo Test for FPGA in /dev/ttyUSB1 Test for FPGA in /dev/ttyUSB1 [Pipeline] sh + python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1 Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'} [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 39130003-221c-4161-b64c-f1c5878b08a7 hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: No test report files were found. Configuration error? Finished: FAILURE