Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/nerv
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf nerv
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/YosysHQ/nerv nerv
Cloning into 'nerv'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/nerv/nerv
[Pipeline] {
[Pipeline] echo
simulation not supported for System Verilog files
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/nerv/nerv
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/nerv/nerv -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
WARNING: No LICENSE files found.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
Resource [colorlight_i9] did not exist. Created.
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
Resource [digilent_arty_a7_100t] did not exist. Created.
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/nerv/nerv
[Pipeline] {
[Pipeline] dir
Running in /var/jenkins_home/workspace/nerv/nerv
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA colorlight_i9.
[Pipeline] sh
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p nerv -b colorlight_i9
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p nerv -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/nerv/nerv/build_colorlight_i9.tcl
Makefile executed successfully.
Makefile output:
/eda/oss-cad-suite/bin/synlig -c /var/jenkins_home/workspace/nerv/nerv/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096

-- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' --

1. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/nerv/nerv/slpp_all/surelog.log".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:685:9: Unused macro argument "ADDR".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:685:9: Unused macro argument "VALUE".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:691:9: Unused macro argument "ADDR".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:691:9: Unused macro argument "VALUE".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:697:9: Unused macro argument "ADDR".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:697:9: Unused macro argument "VALUE".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:702:9: Unused macro argument "ARRAY".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:702:9: Unused macro argument "DEPTH".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:703:9: Unused macro argument "ARRAY".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:703:9: Unused macro argument "INDEX".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:723:9: Unused macro argument "ADDR".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:723:9: Unused macro argument "VALUE".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:727:9: Unused macro argument "ADDR".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:727:9: Unused macro argument "NAME".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:727:9: Unused macro argument "VALUE".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:728:9: Unused macro argument "ADDR".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:728:9: Unused macro argument "NAME".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:728:9: Unused macro argument "VALUE".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:738:9: Unused macro argument "ADDR".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:738:9: Unused macro argument "ARRAY".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:738:9: Unused macro argument "INDEX".
[WRN:PP0113] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:738:9: Unused macro argument "NAME".
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 22
[   NOTE] : 0

2. Executing Verilog-2005 frontend: /eda/processor_ci/rtl/nerv.v
Parsing Verilog input from `/eda/processor_ci/rtl/nerv.v' to AST representation.
Generating RTLIL representation for module `\processorci_top'.
Successfully finished Verilog frontend.

3. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/nerv/nerv/slpp_all/surelog.log".
[INF:CP0300] Compilation...
[INF:CP0303] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:298:1: Compile module "work@nerv".
[NTE:CP0309] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:305:9: Implicit port type (wire) for "trap",
there are 5 more instances of this message.
[INF:EL0526] Design Elaboration...
[NTE:EL0503] /var/jenkins_home/workspace/nerv/nerv/nerv.sv:298:1: Top level module "work@nerv".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 1.
[NTE:EL0510] Nb instances: 1.
[NTE:EL0511] Nb leaf instances: 0.
[INF:UH0706] Creating UHDM Model...
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 6
Generating RTLIL representation for module `\nerv'.
Warning: wire '\hpm_counter_idx' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:730.8-730.25.
Warning: wire '\hpm_counter_idx' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:730.49-730.82.
Warning: wire '\hpm_counterh_idx' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:730.8-730.26.
Warning: wire '\hpm_counterh_idx' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:730.51-730.86.
Warning: wire '\hpm_event_idx' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:730.8-730.23.
Warning: wire '\hpm_event_idx' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:730.45-730.74.
Warning: wire '\hpm_idx' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:747.8-747.17.
Warning: wire '\hpm_idx' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:747.33-747.50.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:749.22-749.39.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:750.24-750.41.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.
Warning: wire '\hpm_event' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:752.6-752.56.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:755.32-755.49.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:756.38-756.69.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:757.32-757.71.
Warning: wire '\hpm_increment' is assigned in a block at /var/jenkins_home/workspace/nerv/nerv/nerv.sv:760.6-760.23.

4. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_rx'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tx'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v
Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v
Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v
Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v
Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v
Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation.
Generating RTLIL representation for module `\Interpreter'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v
Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation.
Generating RTLIL representation for module `\Controller'.
Successfully finished Verilog frontend.

13. Executing SYNTH_ECP5 pass.

13.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_sim.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

13.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_bb.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

13.3. Executing HIERARCHY pass (managing design hierarchy).

13.3.1. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     \ResetBootSystem
Used module:     \nerv
Used module:     \Controller
Used module:         \Memory
Used module:         \UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \CYCLES = 20

13.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

13.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

13.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

13.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20

13.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12

13.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12
Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

13.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

13.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

13.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

13.3.11. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \nerv
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         \Memory
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

13.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20

13.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32

13.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32
Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'.

13.3.15. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \nerv
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

13.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

13.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

13.3.18. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \nerv
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider

13.3.19. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \nerv
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Removing unused module `\Controller'.
Removing unused module `\Interpreter'.
Removing unused module `\Memory'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removing unused module `\FIFO'.
Removing unused module `\uart_tx'.
Removing unused module `\uart_rx'.
Removing unused module `\UART'.
Removed 14 unused modules.

13.4. Executing PROC pass (convert processes to netlists).

13.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$1081'.
Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$1263'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$1263'.
Cleaned up 2 empty switches.

13.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1188 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1140 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1082 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$1443 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$1435 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1636 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1634 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1626 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1623 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1617 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1612 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1607 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1598 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1585 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1583 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1575 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1561 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1555 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1550 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1537 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1528 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1492 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1484 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1484 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1479 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1474 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$1469 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$1252 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$1241 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$1191 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1112$419 in module nerv.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1101$416 in module nerv.
Marked 93 switch rules as full_case in process $proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32 in module nerv.
Marked 19 switch rules as full_case in process $proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:629$31 in module nerv.
Removed a total of 1 dead cases.

13.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 4 redundant assignments.
Promoted 335 assignments to connections.

13.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1189'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1468'.
  Set init value: \read_ptr = 6'000000
  Set init value: \write_ptr = 6'000000
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1638'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1591'.
  Set init value: \i = 0
Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1543'.
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
  Set init value: \pulse_counter = 0
Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1521'.
  Set init value: \state = 8'00000000
  Set init value: \counter = 8'00000000
  Set init value: \read_buffer = 0
  Set init value: \timeout = 0
  Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1491'.
  Set init value: \read_response = 1'0
  Set init value: \write_response = 1'0
  Set init value: \read_data = 0
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
  Set init value: \counter_write = 3'000
  Set init value: \counter_read = 3'000
  Set init value: \state_read = 4'0000
  Set init value: \state_write = 4'0000
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$1198'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000

13.4.5. Executing PROC_ARST pass (detect async resets in processes).

13.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~224 debug messages>

13.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1189'.
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1188'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1140'.
     1/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1139_EN[3:0]$1146
     2/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1139_DATA[3:0]$1145
     3/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1139_ADDR[3:0]$1144
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1082'.
     1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1080_EN[3:0]$1088
     2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1080_DATA[3:0]$1087
     3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1080_ADDR[3:0]$1086
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$1081'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1468'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1443'.
     1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1455
     2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_DATA[7:0]$1454
     3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_ADDR[5:0]$1453
     4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1449
     5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_DATA[7:0]$1448
     6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_ADDR[5:0]$1447
     7/7: $0\write_ptr[5:0]
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1435'.
     1/2: $0\read_ptr[5:0]
     2/2: $0\read_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1638'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1636'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1634'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1626'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1623'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1617'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1612'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1607'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1598'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1591'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1585'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1583'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1575'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1561'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1555'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1550'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1543'.
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1537'.
     1/1: $0\pulse_counter[31:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1528'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1521'.
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
     1/28: $0\state[7:0]
     2/28: $0\reset_bus[0:0]
     3/28: $0\memory_write[0:0]
     4/28: $0\memory_read[0:0]
     5/28: $0\write_pulse[0:0]
     6/28: $0\core_reset[0:0]
     7/28: $0\communication_write[0:0]
     8/28: $0\communication_read[0:0]
     9/28: $0\temp_buffer[63:0]
    10/28: $0\accumulator[63:0]
    11/28: $0\timeout_counter[31:0]
    12/28: $0\timeout[31:0]
    13/28: $0\read_buffer[31:0]
    14/28: $0\communication_buffer[31:0]
    15/28: $0\num_of_positions[23:0]
    16/28: $0\num_of_pages[23:0]
    17/28: $0\return_state[7:0]
    18/28: $0\memory_page_number[23:0]
    19/28: $0\memory_mux_selector[0:0]
    20/28: $0\end_position[31:0]
    21/28: $0\memory_page_size[23:0]
    22/28: $0\bus_mode[0:0]
    23/28: $0\num_of_cycles_to_pulse[31:0]
    24/28: $0\core_clk_enable[0:0]
    25/28: $0\communication_write_data[31:0]
    26/28: $0\counter[7:0]
    27/28: $0\write_data[31:0]
    28/28: $0\address[31:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1491'.
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1484'.
     1/4: $0\tx_fifo_read[0:0]
     2/4: $0\uart_tx_en[0:0]
     3/4: $0\tx_fifo_read_state[1:0]
     4/4: $0\uart_tx_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1479'.
     1/2: $0\rx_fifo_write[0:0]
     2/2: $0\rx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1474'.
     1/6: $0\tx_fifo_write[0:0]
     2/6: $0\write_response[0:0]
     3/6: $0\state_write[3:0]
     4/6: $0\counter_write[2:0]
     5/6: $0\write_data_buffer[31:0]
     6/6: $0\tx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1469'.
     1/5: $0\read_response[0:0]
     2/5: $0\rx_fifo_read[0:0]
     3/5: $0\state_read[3:0]
     4/5: $0\counter_read[2:0]
     5/5: $0\read_data[31:0]
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1262'.
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1252'.
     1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1261
     2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_DATA[31:0]$1260
     3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_ADDR[31:0]$1259
     4/4: $0\read_sync[31:0]
Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1241'.
     1/1: $0\finish_execution[0:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$1198'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1191'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:409$682'.
     1/4: $0\mem_wr_enable_q[0:0]
     2/4: $0\mem_rd_func_q[4:0]
     3/4: $0\mem_rd_reg_q[4:0]
     4/4: $0\mem_rd_enable_q[0:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1112$419'.
     1/4: $1$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$427
     2/4: $1$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_DATA[31:0]$426
     3/4: $1$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_ADDR[4:0]$425
     4/4: $0\pc[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1101$416'.
     1/1: $1\mem_rdata[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
     1/225: $3\mem_wr_enable[0:0]
     2/225: $3\mem_rd_enable[0:0]
     3/225: $7\next_wr[0:0]
     4/225: $15\csr_mstatus_next[3:3]
     5/225: $16\csr_mstatus_next[7:7]
     6/225: $5\csr_mcause_wdata[31:0]
     7/225: $8\csr_mcause_next[31:0]
     8/225: $20\npc[31:0]
     9/225: $8\csr_mepc_next[31:2]
    10/225: $5\cycle_trap[0:0]
    11/225: $5\cycle_insn[0:0]
    12/225: $7\csr_mepc_next[31:0] [31:2]
    13/225: $7\csr_mepc_next[31:0] [1:0]
    14/225: $4\cycle_intr[0:0]
    15/225: $13\csr_mstatus_next[3:3]
    16/225: $14\csr_mstatus_next[7:7]
    17/225: $18\npc[31:0]
    18/225: $7\csr_mcause_next[31:0]
    19/225: $19\npc[31:0]
    20/225: $4\csr_mcause_wdata[31:0]
    21/225: $4\cycle_trap[0:0]
    22/225: $4\cycle_insn[0:0]
    23/225: $9\next_rd[31:0]
    24/225: $3\wr_rd[4:0]
    25/225: $3\cycle_late_wr[0:0]
    26/225: $17\npc[31:0]
    27/225: $6\csr_mcause_next[31:0]
    28/225: $3\csr_mcause_wdata[31:0]
    29/225: $6\csr_mepc_next[31:0]
    30/225: $12\csr_mstatus_next[7:7]
    31/225: $11\csr_mstatus_next[3:3]
    32/225: $3\cycle_trap[0:0]
    33/225: $3\cycle_insn[0:0]
    34/225: $3\cycle_intr[0:0]
    35/225: $16\npc[31:0]
    36/225: $5\csr_mcause_next[31:0]
    37/225: $2\csr_mcause_wdata[31:0]
    38/225: $5\csr_mepc_next[31:0]
    39/225: $10\csr_mstatus_next[7:7]
    40/225: $9\csr_mstatus_next[3:3]
    41/225: $2\cycle_late_wr[0:0]
    42/225: $2\cycle_trap[0:0]
    43/225: $2\cycle_insn[0:0]
    44/225: $2\cycle_intr[0:0]
    45/225: $2\wr_rd[4:0]
    46/225: $8\next_rd[31:0]
    47/225: $7\csr_mstatus_next[3:3]
    48/225: $15\npc[31:0]
    49/225: $4\csr_mcause_next[31:0]
    50/225: $1\csr_mcause_wdata[31:0]
    51/225: $4\csr_mepc_next[31:0]
    52/225: $8\csr_mstatus_next[7:7]
    53/225: $1\cycle_late_wr[0:0]
    54/225: $1\cycle_trap[0:0]
    55/225: $1\cycle_insn[0:0]
    56/225: $1\cycle_intr[0:0]
    57/225: $1\wr_rd[4:0]
    58/225: $7\next_rd[31:0]
    59/225: $6\next_rd[31:0]
    60/225: $6\next_wr[0:0]
    61/225: $13\illinsn[0:0]
    62/225: $5\csr_mstatus_next[3:3]
    63/225: $6\csr_mstatus_next[7:7]
    64/225: $3\csr_mcause_next[31:0]
    65/225: $14\npc[31:0]
    66/225: $3\csr_mepc_next[31:0]
    67/225: $12\illinsn[0:0]
    68/225: $2\csr_mcause_next[31:0]
    69/225: $2\csr_mepc_next[31:0]
    70/225: $4\csr_mstatus_next[7:7]
    71/225: $3\csr_mstatus_next[3:3]
    72/225: $11\illinsn[0:0]
    73/225: $13\npc[31:0]
    74/225: $5\next_rd[31:0]
    75/225: $5\next_wr[0:0]
    76/225: $4\next_rd[31:0]
    77/225: $4\next_wr[0:0]
    78/225: $10\illinsn[0:0]
    79/225: $3\next_rd[31:0]
    80/225: $3\next_wr[0:0]
    81/225: $9\illinsn[0:0]
    82/225: $3\mem_wr_strb[3:0]
    83/225: $2\mem_wr_addr[31:0]
    84/225: $2\mem_wr_strb[3:0]
    85/225: $2\mem_wr_data[31:0]
    86/225: $2\mem_wr_enable[0:0]
    87/225: $8\illinsn[0:0]
    88/225: $2\mem_rd_addr[31:0]
    89/225: $2\mem_rd_func[4:0]
    90/225: $2\mem_rd_reg[4:0]
    91/225: $2\mem_rd_enable[0:0]
    92/225: $7\illinsn[0:0]
    93/225: $12\npc[31:0]
    94/225: $6\illinsn[0:0]
    95/225: $11\npc[31:0]
    96/225: $10\npc[31:0]
    97/225: $9\npc[31:0]
    98/225: $8\npc[31:0]
    99/225: $7\npc[31:0]
   100/225: $6\npc[31:0]
   101/225: $5\npc[31:0]
   102/225: $5\illinsn[0:0]
   103/225: $4\npc[31:0]
   104/225: $4\illinsn[0:0]
   105/225: $3\npc[31:0]
   106/225: $2\next_rd[31:0]
   107/225: $2\next_wr[0:0]
   108/225: $3\illinsn[0:0]
   109/225: $2\npc[31:0]
   110/225: $2\illinsn[0:0]
   111/225: $1\next_rd[31:0]
   112/225: $1\next_wr[0:0]
   113/225: $1\csr_mcause_next[31:0]
   114/225: $1\csr_mepc_next[31:0]
   115/225: $2\csr_mstatus_next[7:7]
   116/225: $1\csr_mstatus_next[3:3]
   117/225: $1\illinsn[0:0]
   118/225: $1\npc[31:0]
   119/225: $1\mem_rd_func[4:0]
   120/225: $1\mem_rd_reg[4:0]
   121/225: $1\mem_rd_addr[31:0]
   122/225: $1\mem_rd_enable[0:0]
   123/225: $1\mem_wr_data[31:0]
   124/225: $1\mem_wr_strb[3:0]
   125/225: $1\mem_wr_addr[31:0]
   126/225: $1\mem_wr_enable[0:0]
   127/225: $32\hpm_increment[31:0]
   128/225: $32\csr_hpm_event_next[1023:992]
   129/225: $32\hpm_event[31:0]
   130/225: $31\hpm_increment[31:0]
   131/225: $31\csr_hpm_event_next[991:960]
   132/225: $31\hpm_event[31:0]
   133/225: $30\hpm_increment[31:0]
   134/225: $30\csr_hpm_event_next[959:928]
   135/225: $30\hpm_event[31:0]
   136/225: $29\hpm_increment[31:0]
   137/225: $29\csr_hpm_event_next[927:896]
   138/225: $29\hpm_event[31:0]
   139/225: $28\hpm_increment[31:0]
   140/225: $28\csr_hpm_event_next[895:864]
   141/225: $28\hpm_event[31:0]
   142/225: $27\hpm_increment[31:0]
   143/225: $27\csr_hpm_event_next[863:832]
   144/225: $27\hpm_event[31:0]
   145/225: $26\hpm_increment[31:0]
   146/225: $26\csr_hpm_event_next[831:800]
   147/225: $26\hpm_event[31:0]
   148/225: $25\hpm_increment[31:0]
   149/225: $25\csr_hpm_event_next[799:768]
   150/225: $25\hpm_event[31:0]
   151/225: $24\hpm_increment[31:0]
   152/225: $24\csr_hpm_event_next[767:736]
   153/225: $24\hpm_event[31:0]
   154/225: $23\hpm_increment[31:0]
   155/225: $23\csr_hpm_event_next[735:704]
   156/225: $23\hpm_event[31:0]
   157/225: $22\hpm_increment[31:0]
   158/225: $22\csr_hpm_event_next[703:672]
   159/225: $22\hpm_event[31:0]
   160/225: $21\hpm_increment[31:0]
   161/225: $21\csr_hpm_event_next[671:640]
   162/225: $21\hpm_event[31:0]
   163/225: $20\hpm_increment[31:0]
   164/225: $20\csr_hpm_event_next[639:608]
   165/225: $20\hpm_event[31:0]
   166/225: $19\hpm_increment[31:0]
   167/225: $19\csr_hpm_event_next[607:576]
   168/225: $19\hpm_event[31:0]
   169/225: $18\hpm_increment[31:0]
   170/225: $18\csr_hpm_event_next[575:544]
   171/225: $18\hpm_event[31:0]
   172/225: $17\hpm_increment[31:0]
   173/225: $17\csr_hpm_event_next[543:512]
   174/225: $17\hpm_event[31:0]
   175/225: $16\hpm_increment[31:0]
   176/225: $16\csr_hpm_event_next[511:480]
   177/225: $16\hpm_event[31:0]
   178/225: $15\hpm_increment[31:0]
   179/225: $15\csr_hpm_event_next[479:448]
   180/225: $15\hpm_event[31:0]
   181/225: $14\hpm_increment[31:0]
   182/225: $14\csr_hpm_event_next[447:416]
   183/225: $14\hpm_event[31:0]
   184/225: $13\hpm_increment[31:0]
   185/225: $13\csr_hpm_event_next[415:384]
   186/225: $13\hpm_event[31:0]
   187/225: $12\hpm_increment[31:0]
   188/225: $12\csr_hpm_event_next[383:352]
   189/225: $12\hpm_event[31:0]
   190/225: $11\hpm_increment[31:0]
   191/225: $11\csr_hpm_event_next[351:320]
   192/225: $11\hpm_event[31:0]
   193/225: $10\hpm_increment[31:0]
   194/225: $10\csr_hpm_event_next[319:288]
   195/225: $10\hpm_event[31:0]
   196/225: $9\hpm_increment[31:0]
   197/225: $9\csr_hpm_event_next[287:256]
   198/225: $9\hpm_event[31:0]
   199/225: $8\hpm_increment[31:0]
   200/225: $8\csr_hpm_event_next[255:224]
   201/225: $8\hpm_event[31:0]
   202/225: $7\hpm_increment[31:0]
   203/225: $7\csr_hpm_event_next[223:192]
   204/225: $7\hpm_event[31:0]
   205/225: $6\hpm_increment[31:0]
   206/225: $6\csr_hpm_event_next[191:160]
   207/225: $6\hpm_event[31:0]
   208/225: $5\hpm_increment[31:0]
   209/225: $5\csr_hpm_event_next[159:128]
   210/225: $5\hpm_event[31:0]
   211/225: $4\hpm_increment[31:0]
   212/225: $4\csr_hpm_event_next[127:96]
   213/225: $4\hpm_event[31:0]
   214/225: $3\hpm_increment[31:0]
   215/225: $3\csr_hpm_event_next[95:64]
   216/225: $3\hpm_event[31:0]
   217/225: $2\hpm_increment[31:0]
   218/225: $2\csr_hpm_event_next[63:32]
   219/225: $2\hpm_event[31:0]
   220/225: $1\hpm_increment[31:0]
   221/225: $1\csr_hpm_event_next[31:0]
   222/225: $1\hpm_event[31:0]
   223/225: $1\csr_next[31:0]
   224/225: $1\csr_rdval[31:0]
   225/225: $1\csr_ack[0:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:629$31'.
     1/19: $19\irq_num[4:0]
     2/19: $18\irq_num[4:0]
     3/19: $17\irq_num[4:0]
     4/19: $16\irq_num[4:0]
     5/19: $15\irq_num[4:0]
     6/19: $14\irq_num[4:0]
     7/19: $13\irq_num[4:0]
     8/19: $12\irq_num[4:0]
     9/19: $11\irq_num[4:0]
    10/19: $10\irq_num[4:0]
    11/19: $9\irq_num[4:0]
    12/19: $8\irq_num[4:0]
    13/19: $7\irq_num[4:0]
    14/19: $6\irq_num[4:0]
    15/19: $5\irq_num[4:0]
    16/19: $4\irq_num[4:0]
    17/19: $3\irq_num[4:0]
    18/19: $2\irq_num[4:0]
    19/19: $1\irq_num[4:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$29'.
     1/1: $0\csr_custom_value[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:598$27'.
     1/1: $0\csr_hpm_event_value[1023:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:598$25'.
     1/1: $0\csr_hpm_counterh_value[1023:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:598$23'.
     1/1: $0\csr_hpm_counter_value[1023:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$21'.
     1/1: $0\csr_mip_value[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$19'.
     1/1: $0\csr_mtval_value[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$17'.
     1/1: $0\csr_mcause_value[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$15'.
     1/1: $0\csr_mepc_value[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$13'.
     1/1: $0\csr_mscratch_value[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$11'.
     1/1: $0\csr_mstatush_value[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$9'.
     1/1: $0\csr_mtvec_value[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$7'.
     1/1: $0\csr_mie_value[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$5'.
     1/1: $0\csr_misa_value[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$3'.
     1/1: $0\csr_mstatus_value[31:0]
Creating decoders for process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:435$2'.

13.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1607'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1550'.
No latch inferred for signal `\nerv.\mem_rdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1101$416'.
No latch inferred for signal `\nerv.\hpm_counterh_idx' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\hpm_event_idx' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\mem_wr_enable' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\mem_wr_addr' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\hpm_counter_idx' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\hpm_event' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\hpm_increment' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\hpm_idx' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\mem_wr_strb' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\mem_wr_data' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\mem_rd_enable' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\mem_rd_addr' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\mem_rd_reg' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\mem_rd_func' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\npc' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\next_wr' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\next_rd' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\wr_rd' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\illinsn' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\cycle_intr' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\cycle_insn' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\cycle_trap' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\cycle_late_wr' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_ack' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_rdval' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mstatus_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mstatus_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_misa_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_misa_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mie_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mie_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mtvec_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mtvec_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mstatush_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mstatush_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mscratch_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mscratch_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mepc_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mepc_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mcause_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mcause_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mtval_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mtval_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mip_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_mip_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_hpm_counter_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_hpm_counter_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_hpm_counterh_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_hpm_counterh_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_hpm_event_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_hpm_event_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_custom_wdata' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\csr_custom_next' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
No latch inferred for signal `\nerv.\irq_num' from process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:629$31'.

13.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1188'.
  created $dff cell `$procdff$5571' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1124_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1125_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1126_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1127_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1128_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1129_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1130_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1131_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1132_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1133_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1134_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1135_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1136_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1137_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1138_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1139_ADDR' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1140'.
  created $dff cell `$procdff$5572' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1139_DATA' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1140'.
  created $dff cell `$procdff$5573' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1139_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1140'.
  created $dff cell `$procdff$5574' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1064_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1065_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1066_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1067_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1068_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1069_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1070_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1071_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1072_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1073_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1074_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1075_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1076_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1077_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1078_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1079_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1080_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1082'.
  created $dff cell `$procdff$5575' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1080_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1082'.
  created $dff cell `$procdff$5576' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1080_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1082'.
  created $dff cell `$procdff$5577' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$1081'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1443'.
  created $dff cell `$procdff$5578' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1443'.
  created $dff cell `$procdff$5579' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1443'.
  created $dff cell `$procdff$5580' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1443'.
  created $dff cell `$procdff$5581' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1435'.
  created $dff cell `$procdff$5582' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1435'.
  created $dff cell `$procdff$5583' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1636'.
  created $dff cell `$procdff$5584' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1636'.
  created $dff cell `$procdff$5585' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1634'.
  created $dff cell `$procdff$5586' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1626'.
  created $dff cell `$procdff$5587' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1623'.
  created $dff cell `$procdff$5588' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1617'.
  created $dff cell `$procdff$5589' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1612'.
  created $dff cell `$procdff$5590' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1612'.
  created $dff cell `$procdff$5591' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1598'.
  created $dff cell `$procdff$5592' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1585'.
  created $dff cell `$procdff$5593' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1583'.
  created $dff cell `$procdff$5594' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1575'.
  created $dff cell `$procdff$5595' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1561'.
  created $dff cell `$procdff$5596' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1555'.
  created $dff cell `$procdff$5597' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1555'.
  created $dff cell `$procdff$5598' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1537'.
  created $dff cell `$procdff$5599' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1528'.
  created $dff cell `$procdff$5600' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1528'.
  created $dff cell `$procdff$5601' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5602' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5603' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5604' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5605' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5606' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5607' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5608' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5609' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5610' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5611' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5612' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5613' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5614' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5615' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5616' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5617' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5618' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5619' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5620' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5621' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5622' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5623' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5624' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5625' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5626' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5627' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5628' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
  created $dff cell `$procdff$5629' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1484'.
  created $dff cell `$procdff$5630' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1484'.
  created $dff cell `$procdff$5631' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1484'.
  created $dff cell `$procdff$5632' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1484'.
  created $dff cell `$procdff$5633' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1479'.
  created $dff cell `$procdff$5634' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1479'.
  created $dff cell `$procdff$5635' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1474'.
  created $dff cell `$procdff$5636' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1474'.
  created $dff cell `$procdff$5637' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1474'.
  created $dff cell `$procdff$5638' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1474'.
  created $dff cell `$procdff$5639' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1474'.
  created $dff cell `$procdff$5640' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1474'.
  created $dff cell `$procdff$5641' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1469'.
  created $dff cell `$procdff$5642' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1469'.
  created $dff cell `$procdff$5643' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1469'.
  created $dff cell `$procdff$5644' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1469'.
  created $dff cell `$procdff$5645' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1469'.
  created $dff cell `$procdff$5646' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1262'.
  created $dff cell `$procdff$5647' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1262'.
  created $dff cell `$procdff$5648' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1252'.
  created $dff cell `$procdff$5649' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1252'.
  created $dff cell `$procdff$5650' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1252'.
  created $dff cell `$procdff$5651' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1252'.
  created $dff cell `$procdff$5652' with positive edge clock.
Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1241'.
  created $dff cell `$procdff$5653' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1191'.
  created $dff cell `$procdff$5654' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1191'.
  created $dff cell `$procdff$5655' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1191'.
  created $dff cell `$procdff$5656' with positive edge clock.
Creating register for signal `\nerv.\mem_rd_enable_q' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:409$682'.
  created $dff cell `$procdff$5657' with positive edge clock.
Creating register for signal `\nerv.\mem_rd_reg_q' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:409$682'.
  created $dff cell `$procdff$5658' with positive edge clock.
Creating register for signal `\nerv.\mem_rd_func_q' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:409$682'.
  created $dff cell `$procdff$5659' with positive edge clock.
Creating register for signal `\nerv.\mem_wr_enable_q' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:409$682'.
  created $dff cell `$procdff$5660' with positive edge clock.
Creating register for signal `\nerv.\pc' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1112$419'.
  created $dff cell `$procdff$5661' with positive edge clock.
Creating register for signal `\nerv.\reset_q' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1112$419'.
  created $dff cell `$procdff$5662' with positive edge clock.
Creating register for signal `\nerv.$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_ADDR' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1112$419'.
  created $dff cell `$procdff$5663' with positive edge clock.
Creating register for signal `\nerv.$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_DATA' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1112$419'.
  created $dff cell `$procdff$5664' with positive edge clock.
Creating register for signal `\nerv.$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1112$419'.
  created $dff cell `$procdff$5665' with positive edge clock.
Creating register for signal `\nerv.\csr_custom_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$29'.
  created $dff cell `$procdff$5666' with positive edge clock.
Creating register for signal `\nerv.\csr_hpm_event_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:598$27'.
  created $dff cell `$procdff$5667' with positive edge clock.
Creating register for signal `\nerv.\csr_hpm_counterh_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:598$25'.
  created $dff cell `$procdff$5668' with positive edge clock.
Creating register for signal `\nerv.\csr_hpm_counter_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:598$23'.
  created $dff cell `$procdff$5669' with positive edge clock.
Creating register for signal `\nerv.\csr_mip_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$21'.
  created $dff cell `$procdff$5670' with positive edge clock.
Creating register for signal `\nerv.\csr_mtval_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$19'.
  created $dff cell `$procdff$5671' with positive edge clock.
Creating register for signal `\nerv.\csr_mcause_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$17'.
  created $dff cell `$procdff$5672' with positive edge clock.
Creating register for signal `\nerv.\csr_mepc_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$15'.
  created $dff cell `$procdff$5673' with positive edge clock.
Creating register for signal `\nerv.\csr_mscratch_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$13'.
  created $dff cell `$procdff$5674' with positive edge clock.
Creating register for signal `\nerv.\csr_mstatush_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$11'.
  created $dff cell `$procdff$5675' with positive edge clock.
Creating register for signal `\nerv.\csr_mtvec_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$9'.
  created $dff cell `$procdff$5676' with positive edge clock.
Creating register for signal `\nerv.\csr_mie_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$7'.
  created $dff cell `$procdff$5677' with positive edge clock.
Creating register for signal `\nerv.\csr_misa_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$5'.
  created $dff cell `$procdff$5678' with positive edge clock.
Creating register for signal `\nerv.\csr_mstatus_value' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$3'.
  created $dff cell `$procdff$5679' with positive edge clock.
Creating register for signal `\nerv.\imem_addr_q' using process `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:435$2'.
  created $dff cell `$procdff$5680' with positive edge clock.

13.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

13.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1189'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1188'.
Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1188'.
Removing empty process `DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1163'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1140'.
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1106'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1082'.
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$1081'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1468'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1443'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1443'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1435'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1435'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1638'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1636'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1636'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1634'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1634'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1626'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1626'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1623'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1623'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1617'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1617'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1612'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1612'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1607'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1607'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1598'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1598'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1591'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1585'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1585'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1583'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1583'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1575'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1575'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1561'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1561'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1555'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1555'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1550'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1550'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1543'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1537'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1537'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1528'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1528'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1521'.
Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1492'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1491'.
Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1484'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1484'.
Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1479'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1479'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1474'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1474'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1469'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1469'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1262'.
Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1252'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1252'.
Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1241'.
Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1241'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$1198'.
Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1191'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1191'.
Found and cleaned up 2 empty switches in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:409$682'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:409$682'.
Found and cleaned up 2 empty switches in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1112$419'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1112$419'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1101$416'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1101$416'.
Found and cleaned up 93 empty switches in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:652$32'.
Found and cleaned up 19 empty switches in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:629$31'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:629$31'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$29'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$29'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:598$27'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:598$27'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:598$25'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:598$25'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:598$23'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:598$23'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$21'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$21'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$19'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$19'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$17'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$17'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$15'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$15'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$13'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$13'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$11'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$11'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$9'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$9'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$7'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$7'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$5'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$5'.
Found and cleaned up 1 empty switch in `\nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$3'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:577$3'.
Removing empty process `nerv.$proc$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:435$2'.
Cleaned up 224 empty switches.

13.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~5 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
<suppressed ~9 debug messages>
Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
<suppressed ~15 debug messages>
Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
<suppressed ~24 debug messages>
Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
<suppressed ~3 debug messages>
Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
<suppressed ~26 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~8 debug messages>
Optimizing module nerv.
<suppressed ~315 debug messages>
Optimizing module processorci_top.

13.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module nerv.
<suppressed ~12 debug messages>

13.6. Executing TRIBUF pass.

13.7. Executing DEMINOUT pass (demote inout ports to input or output).

13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~105 debug messages>

13.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 140 unused cells and 1980 unused wires.
<suppressed ~173 debug messages>

13.10. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Warning: Wire processorci_top.\miso is used but has no driver.
Warning: Wire processorci_top.\intr is used but has no driver.
Warning: Wire processorci_top.\cpu.insn_opcode [6] is used but has no driver.
Warning: Wire processorci_top.\cpu.insn_opcode [5] is used but has no driver.
Warning: Wire processorci_top.\cpu.insn_opcode [4] is used but has no driver.
Warning: Wire processorci_top.\cpu.insn_opcode [3] is used but has no driver.
Warning: Wire processorci_top.\cpu.insn_opcode [2] is used but has no driver.
Warning: Wire processorci_top.\cpu.insn_opcode [1] is used but has no driver.
Warning: Wire processorci_top.\cpu.insn_opcode [0] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [31] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [30] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [29] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [28] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [27] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [26] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [25] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [24] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [23] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [22] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [21] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [20] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [19] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [18] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [17] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [16] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [15] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [14] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [13] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [12] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [11] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [10] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [9] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [8] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [7] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [6] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [5] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [4] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_mip_next [3] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [2] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [1] is used but has no driver.
Warning: Wire processorci_top.\cpu.irq [0] is used but has no driver.
Warning: Wire processorci_top.\cpu.imem_data [7] is used but has no driver.
Warning: Wire processorci_top.\cpu.imem_data [11] is used but has no driver.
Warning: Wire processorci_top.\cpu.imem_data [10] is used but has no driver.
Warning: Wire processorci_top.\cpu.imem_data [9] is used but has no driver.
Warning: Wire processorci_top.\cpu.imem_data [8] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_addr [11] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_addr [10] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_addr [9] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_addr [8] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_addr [7] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_addr [6] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_addr [5] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_addr [4] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_addr [3] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_addr [2] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_addr [1] is used but has no driver.
Warning: Wire processorci_top.\cpu.csr_addr [0] is used but has no driver.
Warning: Wire processorci_top.\cpu.imm_j_sext [19] is used but has no driver.
Warning: Wire processorci_top.\cpu.imm_j_sext [18] is used but has no driver.
Warning: Wire processorci_top.\cpu.imm_j_sext [17] is used but has no driver.
Warning: Wire processorci_top.\cpu.imm_j_sext [16] is used but has no driver.
Warning: Wire processorci_top.\cpu.imm_j_sext [15] is used but has no driver.
Warning: Wire processorci_top.\cpu.imem_data [14] is used but has no driver.
Warning: Wire processorci_top.\cpu.imem_data [13] is used but has no driver.
Warning: Wire processorci_top.\cpu.imem_data [12] is used but has no driver.
Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver.
Found and reported 67 problems.

13.11. Executing OPT pass (performing simple optimizations).

13.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~1407 debug messages>
Removed a total of 469 cells.

13.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1666.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1672.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1678.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3012.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3015.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3021.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3027.
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    dead port 1/2 on $mux $flatten\cpu.$procmux$3117.
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    dead port 1/2 on $mux $flatten\cpu.$procmux$3132.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3138.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3144.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3150.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3168.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3174.
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    dead port 1/2 on $mux $flatten\cpu.$procmux$3186.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3192.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3198.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3204.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3210.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3216.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3219.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3225.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3255.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3261.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3270.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3279.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3288.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3297.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3306.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3324.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3333.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3342.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3360.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3375.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3381.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3393.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3399.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3405.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3411.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3423.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3435.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3441.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3444.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3450.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3456.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3459.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3484.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3486.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3493.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3495.
    dead port 1/2 on $mux $flatten\cpu.$procmux$3502.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3504.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3514.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3516.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3526.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3528.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3538.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3540.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3550.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3552.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3562.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3564.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3574.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3576.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3582.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3588.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3594.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3600.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3606.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3612.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3618.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3624.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3640.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3656.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3672.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3688.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3704.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3720.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3743.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1672.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3761.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3770.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1678.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3779.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3789.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3799.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3809.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3819.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3829.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3840.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3851.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3863.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3865.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3878.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3880.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3894.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3896.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3911.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3913.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3929.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3931.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3948.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3950.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3982.
    dead port 2/2 on $mux $flatten\cpu.$procmux$3994.
    dead port 2/2 on $mux $flatten\cpu.$procmux$4006.
    dead port 2/2 on $mux $flatten\cpu.$procmux$4030.
    dead port 2/2 on $mux $flatten\cpu.$procmux$4042.
    dead port 2/2 on $mux $flatten\cpu.$procmux$4054.
    dead port 2/2 on $mux $flatten\cpu.$procmux$4067.
    dead port 2/2 on $mux $flatten\cpu.$procmux$4080.
    dead port 1/4 on $pmux $flatten\cpu.$procmux$4502.
    dead port 3/4 on $pmux $flatten\cpu.$procmux$4502.
    dead port 4/4 on $pmux $flatten\cpu.$procmux$4502.
    dead port 1/4 on $pmux $flatten\cpu.$procmux$4507.
    dead port 3/4 on $pmux $flatten\cpu.$procmux$4507.
    dead port 4/4 on $pmux $flatten\cpu.$procmux$4507.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1666.
    dead port 1/4 on $pmux $flatten\cpu.$procmux$4524.
    dead port 2/4 on $pmux $flatten\cpu.$procmux$4524.
    dead port 4/4 on $pmux $flatten\cpu.$procmux$4524.
    dead port 1/4 on $pmux $flatten\cpu.$procmux$4529.
    dead port 2/4 on $pmux $flatten\cpu.$procmux$4529.
    dead port 4/4 on $pmux $flatten\cpu.$procmux$4529.
    dead port 1/2 on $mux $flatten\cpu.$procmux$4977.
    dead port 1/2 on $mux $flatten\cpu.$procmux$4980.
    dead port 1/2 on $mux $flatten\cpu.$procmux$4983.
    dead port 1/2 on $mux $flatten\cpu.$procmux$4986.
    dead port 1/2 on $mux $flatten\cpu.$procmux$4989.
    dead port 1/2 on $mux $flatten\cpu.$procmux$4992.
    dead port 1/2 on $mux $flatten\cpu.$procmux$4995.
    dead port 1/2 on $mux $flatten\cpu.$procmux$4998.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5001.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5004.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5007.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5010.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5013.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5016.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5019.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5022.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5025.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5028.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5034.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5037.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5040.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5043.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5046.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5049.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5052.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5055.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5058.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5061.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5064.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5067.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5070.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5073.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5076.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5079.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5082.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5088.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5091.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5094.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5097.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5100.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5103.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5106.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5109.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5112.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5115.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5118.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5121.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5124.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5127.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5130.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5133.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5139.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5142.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5145.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5148.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5151.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5154.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5157.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5160.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5163.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5166.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5169.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5172.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5175.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5178.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5181.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5187.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5190.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5193.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5196.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5199.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5202.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5205.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5208.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5211.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5214.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5217.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5220.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5223.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5226.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5232.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5235.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5238.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5241.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5244.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5247.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5250.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5253.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5256.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5259.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5262.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5265.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5268.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5274.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5277.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5280.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5283.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5286.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5289.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5292.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5295.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5298.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5301.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5304.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5307.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5313.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5316.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5319.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5322.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5325.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5328.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5331.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5334.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5337.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5340.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5343.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5349.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5352.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5355.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5358.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5361.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5364.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5367.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5370.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5373.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5376.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5382.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5385.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5388.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5391.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5394.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5397.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5400.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5403.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5406.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5412.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5415.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5418.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5421.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5424.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5427.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5430.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5433.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5439.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5442.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5445.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5448.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5451.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5454.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5457.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5463.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5466.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5469.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5472.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5475.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5478.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5484.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5487.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5490.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5493.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5496.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5502.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5505.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5508.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5511.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5517.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5520.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5523.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5529.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5532.
    dead port 1/2 on $mux $flatten\cpu.$procmux$5538.
    dead port 1/2 on $mux $flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:756$252.
    dead port 2/2 on $mux $flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:756$252.
    dead port 1/2 on $mux $flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:757$253.
    dead port 2/2 on $mux $flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:757$253.
    dead port 1/2 on $mux $flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:757$259.
    dead port 2/2 on $mux $flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:757$259.
Removed 315 multiplexer ports.
<suppressed ~279 debug messages>

13.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2102: $auto$opt_reduce.cc:137:opt_pmux$5697
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2126: $auto$opt_reduce.cc:137:opt_pmux$5699
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2148: $auto$opt_reduce.cc:137:opt_pmux$5701
    Consolidated identical input bits for $mux cell $flatten\cpu.$procmux$2983:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422
      New ports: A=1'0, B=1'1, Y=$flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0]
      New connections: $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [31:1] = { $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] $flatten\cpu.$0$memwr$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1119$1_EN[31:0]$422 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1663:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1663_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1663_Y [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1663_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1663_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1663_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1663_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1663_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1663_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1663_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1663_Y [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2159: $auto$opt_reduce.cc:137:opt_pmux$5703
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$3510: { $auto$opt_reduce.cc:137:opt_pmux$5705 $flatten\cpu.$procmux$3511_CMP }
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$3523: $auto$opt_reduce.cc:137:opt_pmux$5707
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2207: $auto$opt_reduce.cc:137:opt_pmux$5709
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2249: $auto$opt_reduce.cc:137:opt_pmux$5711
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$3546: { $auto$opt_reduce.cc:137:opt_pmux$5713 $flatten\cpu.$procmux$3511_CMP }
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$3559: $auto$opt_reduce.cc:137:opt_pmux$5715
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2274: { $flatten\Controller.\Interpreter.$procmux$2042_CMP $auto$opt_reduce.cc:137:opt_pmux$5717 $flatten\Controller.\Interpreter.$procmux$2032_CMP }
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$3569: $auto$opt_reduce.cc:137:opt_pmux$5719
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2327: { $auto$opt_reduce.cc:137:opt_pmux$5723 $auto$opt_reduce.cc:137:opt_pmux$5721 }
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$3645: $auto$opt_reduce.cc:137:opt_pmux$5725
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2396: $auto$opt_reduce.cc:137:opt_pmux$5727
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2421: { $flatten\Controller.\Interpreter.$procmux$2042_CMP $auto$opt_reduce.cc:137:opt_pmux$5729 $flatten\Controller.\Interpreter.$procmux$2032_CMP }
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$3661: $auto$opt_reduce.cc:137:opt_pmux$5731
    Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2912:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0]
      New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2449: { $flatten\Controller.\Interpreter.$procmux$2028_CMP $flatten\Controller.\Interpreter.$procmux$2021_CMP $flatten\Controller.\Interpreter.$procmux$2010_CMP $flatten\Controller.\Interpreter.$procmux$2004_CMP $auto$opt_reduce.cc:137:opt_pmux$5733 }
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$3694: $auto$opt_reduce.cc:137:opt_pmux$5735
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$3710: $auto$opt_reduce.cc:137:opt_pmux$5737
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2481: { $auto$opt_reduce.cc:137:opt_pmux$5741 $auto$opt_reduce.cc:137:opt_pmux$5739 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2563: { $flatten\Controller.\Interpreter.$procmux$2022_CMP $auto$opt_reduce.cc:137:opt_pmux$5743 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2574: { $flatten\Controller.\Interpreter.$procmux$2163_CMP $flatten\Controller.\Interpreter.$procmux$2062_CMP $auto$opt_reduce.cc:137:opt_pmux$5745 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2584: { $flatten\Controller.\Interpreter.$procmux$2061_CMP $auto$opt_reduce.cc:137:opt_pmux$5749 $auto$opt_reduce.cc:137:opt_pmux$5747 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2660: { $auto$opt_reduce.cc:137:opt_pmux$5751 $flatten\Controller.\Interpreter.$procmux$2061_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2002: { $flatten\Controller.\Interpreter.$procmux$2096_CMP $flatten\Controller.\Interpreter.$procmux$2092_CMP $flatten\Controller.\Interpreter.$procmux$2088_CMP $flatten\Controller.\Interpreter.$procmux$2062_CMP $flatten\Controller.\Interpreter.$procmux$2061_CMP $flatten\Controller.\Interpreter.$procmux$2057_CMP $flatten\Controller.\Interpreter.$procmux$2056_CMP $flatten\Controller.\Interpreter.$procmux$2052_CMP $flatten\Controller.\Interpreter.$procmux$2042_CMP $flatten\Controller.\Interpreter.$procmux$2038_CMP $auto$opt_reduce.cc:137:opt_pmux$5759 $flatten\Controller.\Interpreter.$procmux$2033_CMP $flatten\Controller.\Interpreter.$procmux$2032_CMP $auto$opt_reduce.cc:137:opt_pmux$5757 $flatten\Controller.\Interpreter.$procmux$2027_CMP $flatten\Controller.\Interpreter.$procmux$2026_CMP $flatten\Controller.\Interpreter.$procmux$2021_CMP $flatten\Controller.\Interpreter.$procmux$2017_CMP $flatten\Controller.\Interpreter.$procmux$2016_CMP $auto$opt_reduce.cc:137:opt_pmux$5755 $flatten\Controller.\Interpreter.$procmux$2010_CMP $flatten\Controller.\Interpreter.$procmux$2009_CMP $flatten\Controller.\Interpreter.$procmux$2008_CMP $auto$opt_reduce.cc:137:opt_pmux$5753 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2684: { $flatten\Controller.\Interpreter.$procmux$2129_CMP $flatten\Controller.\Interpreter.$procmux$2128_CMP $auto$opt_reduce.cc:137:opt_pmux$5761 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2710: { $auto$opt_reduce.cc:137:opt_pmux$5763 $flatten\Controller.\Interpreter.$procmux$2128_CMP $flatten\Controller.\Interpreter.$procmux$2047_CMP $flatten\Controller.\Interpreter.$procmux$2042_CMP $flatten\Controller.\Interpreter.$procmux$2032_CMP }
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$3975: $auto$opt_reduce.cc:137:opt_pmux$5765
    Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2912:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0]
      New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_EN[31:0]$1255 [0] }
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4092: { $auto$opt_reduce.cc:137:opt_pmux$5767 $flatten\cpu.$procmux$3995_CMP $flatten\cpu.$procmux$3689_CMP $flatten\cpu.$procmux$3641_CMP $flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:565$450_Y }
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4113: { $auto$opt_reduce.cc:137:opt_pmux$5769 $flatten\cpu.$procmux$4068_CMP $flatten\cpu.$procmux$3995_CMP $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3790_CMP $flatten\cpu.$procmux$3744_CMP $flatten\cpu.$procmux$3689_CMP $flatten\cpu.$procmux$3641_CMP $flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:565$450_Y }
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4188: $auto$opt_reduce.cc:137:opt_pmux$5771
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4199: $auto$opt_reduce.cc:137:opt_pmux$5773
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4210: $auto$opt_reduce.cc:137:opt_pmux$5775
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4221: $auto$opt_reduce.cc:137:opt_pmux$5777
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2780: $auto$opt_reduce.cc:137:opt_pmux$5779
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4232: $auto$opt_reduce.cc:137:opt_pmux$5781
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4243: $auto$opt_reduce.cc:137:opt_pmux$5783
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4254: $auto$opt_reduce.cc:137:opt_pmux$5785
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4265: $auto$opt_reduce.cc:137:opt_pmux$5787
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4276: $auto$opt_reduce.cc:137:opt_pmux$5789
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4287: $auto$opt_reduce.cc:137:opt_pmux$5791
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4298: $auto$opt_reduce.cc:137:opt_pmux$5793
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4309: $auto$opt_reduce.cc:137:opt_pmux$5795
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4320: $auto$opt_reduce.cc:137:opt_pmux$5797
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4331: $auto$opt_reduce.cc:137:opt_pmux$5799
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2844: $auto$opt_reduce.cc:137:opt_pmux$5801
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4342: $auto$opt_reduce.cc:137:opt_pmux$5803
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4353: $auto$opt_reduce.cc:137:opt_pmux$5805
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4364: $auto$opt_reduce.cc:137:opt_pmux$5807
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4375: $auto$opt_reduce.cc:137:opt_pmux$5809
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4386: $auto$opt_reduce.cc:137:opt_pmux$5811
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4397: $auto$opt_reduce.cc:137:opt_pmux$5813
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4408: $auto$opt_reduce.cc:137:opt_pmux$5815
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4419: $auto$opt_reduce.cc:137:opt_pmux$5817
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4430: $auto$opt_reduce.cc:137:opt_pmux$5819
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4441: $auto$opt_reduce.cc:137:opt_pmux$5821
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4452: $auto$opt_reduce.cc:137:opt_pmux$5823
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4463: $auto$opt_reduce.cc:137:opt_pmux$5825
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4474: $auto$opt_reduce.cc:137:opt_pmux$5827
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4485: $auto$opt_reduce.cc:137:opt_pmux$5829
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4496: $auto$opt_reduce.cc:137:opt_pmux$5831
    New ctrl vector for $pmux cell $flatten\cpu.$procmux$4518: $auto$opt_reduce.cc:137:opt_pmux$5833
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1663:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1663_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1663_Y [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1663_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1663_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1663_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1663_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1663_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1663_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1663_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1663_Y [0] }
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1681:
      Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1455, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446
      New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1663_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1681:
      Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1455, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446
      New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1663_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_EN[7:0]$1446 [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 70 changes.

13.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~210 debug messages>
Removed a total of 70 cells.

13.11.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 1 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 2 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 3 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 4 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 5 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 6 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 7 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 8 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 9 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 10 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 11 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 12 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 13 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 14 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 15 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 16 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 17 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 18 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 19 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 20 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 21 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 22 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 23 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 24 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 25 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 26 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 27 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 28 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 29 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 30 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.
Setting constant 0-bit at position 31 on $flatten\cpu.$procdff$5675 ($dff) from module processorci_top.

13.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 827 unused wires.
<suppressed ~13 debug messages>

13.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.11.9. Rerunning OPT passes. (Maybe there is more to do..)

13.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~279 debug messages>

13.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2274: { $auto$opt_reduce.cc:137:opt_pmux$5717 $auto$opt_reduce.cc:137:opt_pmux$5835 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2421: { $auto$opt_reduce.cc:137:opt_pmux$5717 $auto$opt_reduce.cc:137:opt_pmux$5837 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2710: { $auto$opt_reduce.cc:137:opt_pmux$5763 $flatten\Controller.\Interpreter.$procmux$2128_CMP $flatten\Controller.\Interpreter.$procmux$2047_CMP $auto$opt_reduce.cc:137:opt_pmux$5839 }
  Optimizing cells in module \processorci_top.
Performed a total of 3 changes.

13.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

13.11.13. Executing OPT_DFF pass (perform DFF optimizations).

13.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

13.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.11.16. Rerunning OPT passes. (Maybe there is more to do..)

13.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~279 debug messages>

13.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

13.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.11.20. Executing OPT_DFF pass (perform DFF optimizations).

13.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

13.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.11.23. Finished OPT passes. (There is nothing left to do.)

13.12. Executing FSM pass (extract and optimize FSM).

13.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking processorci_top.Controller.Interpreter.return_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state.
Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking processorci_top.Controller.Uart.state_read as FSM state register:
    Register has an initialization value.
Not marking processorci_top.Controller.Uart.state_write as FSM state register:
    Register has an initialization value.
Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state.
Not marking processorci_top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking processorci_top.cpu.csr_mip_value as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking processorci_top.cpu.mem_rd_reg_q as FSM state register:
    Users of register don't seem to benefit from recoding.

13.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$5586
  root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1602_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1615_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1628_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1614_Y
  found state code: 3'000
  found ctrl input: \Controller.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \Controller.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1628_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1619_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1615_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1614_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1602_Y
  ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done }
  ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1602_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1614_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1615_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1619_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1628_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'00-- ->      3'001 8'01010001
  transition:      3'000 4'01-- ->      3'000 8'01010000
  transition:      3'000 4'1--- ->      3'000 8'01010000
  transition:      3'010 4'0--0 ->      3'010 8'00100010
  transition:      3'010 4'0--1 ->      3'011 8'00100011
  transition:      3'010 4'1--- ->      3'000 8'00100000
  transition:      3'001 4'0-0- ->      3'001 8'00011001
  transition:      3'001 4'0-1- ->      3'010 8'00011010
  transition:      3'001 4'1--- ->      3'000 8'00011000
  transition:      3'011 4'0-0- ->      3'011 8'10010011
  transition:      3'011 4'0-1- ->      3'000 8'10010000
  transition:      3'011 4'1--- ->      3'000 8'10010000
Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.$procdff$5633
  root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.$procmux$2741_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2736_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2743_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2730_CMP
  found state code: 2'00
  found state code: 2'11
  found state code: 2'10
  found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1488_Y
  found state code: 2'01
  found ctrl output: $flatten\Controller.\Uart.$procmux$2730_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2736_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2741_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2743_CMP
  ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1488_Y }
  ctrl outputs: { $flatten\Controller.\Uart.$procmux$2743_CMP $flatten\Controller.\Uart.$procmux$2741_CMP $flatten\Controller.\Uart.$procmux$2736_CMP $flatten\Controller.\Uart.$procmux$2730_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] }
  transition:       2'00 2'00 ->       2'00 6'000100
  transition:       2'00 2'01 ->       2'01 6'000101
  transition:       2'00 2'1- ->       2'00 6'000100
  transition:       2'10 2'0- ->       2'11 6'001011
  transition:       2'10 2'1- ->       2'00 6'001000
  transition:       2'01 2'0- ->       2'10 6'100010
  transition:       2'01 2'1- ->       2'00 6'100000
  transition:       2'11 2'0- ->       2'00 6'010000
  transition:       2'11 2'1- ->       2'00 6'010000

13.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5847' from module `\processorci_top'.
  Merging pattern 2'0- and 2'1- from group (3 0 6'010000).
  Merging pattern 2'1- and 2'0- from group (3 0 6'010000).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5840' from module `\processorci_top'.

13.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 15 unused cells and 15 unused wires.
<suppressed ~16 debug messages>

13.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5840' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5847' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2741_CMP.
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2743_CMP.

13.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5840' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---
Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5847' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> ---1
  10 -> --1-
  01 -> -1--
  11 -> 1---

13.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5840' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$5840 (\Controller.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \Controller.Uart.i_uart_rx.payload_done
    1: \Controller.Uart.i_uart_rx.next_bit
    2: \Controller.Uart.i_uart_rx.rxd_reg
    3: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1628_Y
    1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1619_Y
    2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1615_Y
    3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1614_Y
    4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1602_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'01--   ->     0 5'01010
      1:     0 4'1---   ->     0 5'01010
      2:     0 4'00--   ->     2 5'01010
      3:     1 4'1---   ->     0 5'00100
      4:     1 4'0--0   ->     1 5'00100
      5:     1 4'0--1   ->     3 5'00100
      6:     2 4'1---   ->     0 5'00011
      7:     2 4'0-1-   ->     1 5'00011
      8:     2 4'0-0-   ->     2 5'00011
      9:     3 4'0-1-   ->     0 5'10010
     10:     3 4'1---   ->     0 5'10010
     11:     3 4'0-0-   ->     3 5'10010

-------------------------------------

FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5847' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$5847 (\Controller.Uart.tx_fifo_read_state):

  Number of input signals:    2
  Number of output signals:   2
  Number of state bits:       4

  Input signals:
    0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1488_Y
    1: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.$procmux$2730_CMP
    1: $flatten\Controller.\Uart.$procmux$2736_CMP

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'00   ->     0 2'01
      1:     0 2'1-   ->     0 2'01
      2:     0 2'01   ->     2 2'01
      3:     1 2'1-   ->     0 2'10
      4:     1 2'0-   ->     3 2'10
      5:     2 2'1-   ->     0 2'00
      6:     2 2'0-   ->     1 2'00
      7:     3 2'--   ->     0 2'00

-------------------------------------

13.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5840' from module `\processorci_top'.
Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5847' from module `\processorci_top'.

13.13. Executing OPT pass (performing simple optimizations).

13.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~9 debug messages>

13.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

13.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~277 debug messages>

13.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

13.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\cpu.$procdff$5679 ($dff) from module processorci_top (D = { \cpu.csr_mstatus_next [7] \cpu.csr_mstatus_next [3] }, Q = { \cpu.csr_mstatus_value [7] \cpu.csr_mstatus_value [3] }, rval = 2'00).
Adding SRST signal on $flatten\cpu.$procdff$5677 ($dff) from module processorci_top (D = { \cpu.csr_mie_wdata [31:16] \cpu.csr_mie_wdata [11] \cpu.csr_mie_wdata [7] \cpu.csr_mie_wdata [3] }, Q = { \cpu.csr_mie_value [31:16] \cpu.csr_mie_value [11] \cpu.csr_mie_value [7] \cpu.csr_mie_value [3] }, rval = 19'0000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$5921 ($sdff) from module processorci_top (D = { \cpu.csr_next [31:16] \cpu.csr_next [11] \cpu.csr_next [7] \cpu.csr_next [3] }, Q = { \cpu.csr_mie_value [31:16] \cpu.csr_mie_value [11] \cpu.csr_mie_value [7] \cpu.csr_mie_value [3] }).
Adding SRST signal on $flatten\cpu.$procdff$5676 ($dff) from module processorci_top (D = { \cpu.csr_mtvec_wdata [31:2] \cpu.csr_mtvec_wdata [0] }, Q = { \cpu.csr_mtvec_value [31:2] \cpu.csr_mtvec_value [0] }, rval = 31'0000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$5924 ($sdff) from module processorci_top (D = { \cpu.csr_next [31:2] \cpu.csr_next [0] }, Q = { \cpu.csr_mtvec_value [31:2] \cpu.csr_mtvec_value [0] }).
Adding SRST signal on $flatten\cpu.$procdff$5674 ($dff) from module processorci_top (D = \cpu.csr_mscratch_next, Q = \cpu.csr_mscratch_value, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$5927 ($sdff) from module processorci_top (D = \cpu.csr_next, Q = \cpu.csr_mscratch_value).
Adding SRST signal on $flatten\cpu.$procdff$5673 ($dff) from module processorci_top (D = \cpu.csr_mepc_next, Q = \cpu.csr_mepc_value, rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5672 ($dff) from module processorci_top (D = \cpu.csr_mcause_next, Q = \cpu.csr_mcause_value, rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5671 ($dff) from module processorci_top (D = \cpu.csr_mtval_next, Q = \cpu.csr_mtval_value, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$5931 ($sdff) from module processorci_top (D = \cpu.csr_next, Q = \cpu.csr_mtval_value).
Adding SRST signal on $flatten\cpu.$procdff$5670 ($dff) from module processorci_top (D = { \cpu.csr_mip_next [31:16] \cpu.csr_mip_next [11] \cpu.csr_mip_next [7] \cpu.csr_mip_next [3] }, Q = { \cpu.csr_mip_value [31:16] \cpu.csr_mip_value [11] \cpu.csr_mip_value [7] \cpu.csr_mip_value [3] }, rval = 19'0000000000000000000).
Adding SRST signal on $flatten\cpu.$procdff$5669 ($dff) from module processorci_top (D = \cpu.csr_hpm_counter_next, Q = \cpu.csr_hpm_counter_value, rval = 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000).
Adding SRST signal on $flatten\cpu.$procdff$5668 ($dff) from module processorci_top (D = \cpu.csr_hpm_counterh_next, Q = \cpu.csr_hpm_counterh_value, rval = 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_hpm_event_next [63:32], Q = \cpu.csr_hpm_event_value [63:32], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent3_wdata, Q = \cpu.csr_hpm_event_value [127:96], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent4_wdata, Q = \cpu.csr_hpm_event_value [159:128], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent5_wdata, Q = \cpu.csr_hpm_event_value [191:160], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent6_wdata, Q = \cpu.csr_hpm_event_value [223:192], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent7_wdata, Q = \cpu.csr_hpm_event_value [255:224], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent8_wdata, Q = \cpu.csr_hpm_event_value [287:256], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent9_wdata, Q = \cpu.csr_hpm_event_value [319:288], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent10_wdata, Q = \cpu.csr_hpm_event_value [351:320], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent11_wdata, Q = \cpu.csr_hpm_event_value [383:352], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent12_wdata, Q = \cpu.csr_hpm_event_value [415:384], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent13_wdata, Q = \cpu.csr_hpm_event_value [447:416], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent14_wdata, Q = \cpu.csr_hpm_event_value [479:448], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent15_wdata, Q = \cpu.csr_hpm_event_value [511:480], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent16_wdata, Q = \cpu.csr_hpm_event_value [543:512], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent17_wdata, Q = \cpu.csr_hpm_event_value [575:544], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent18_wdata, Q = \cpu.csr_hpm_event_value [607:576], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent19_wdata, Q = \cpu.csr_hpm_event_value [639:608], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent20_wdata, Q = \cpu.csr_hpm_event_value [671:640], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent21_wdata, Q = \cpu.csr_hpm_event_value [703:672], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent22_wdata, Q = \cpu.csr_hpm_event_value [735:704], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent23_wdata, Q = \cpu.csr_hpm_event_value [767:736], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent24_wdata, Q = \cpu.csr_hpm_event_value [799:768], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent25_wdata, Q = \cpu.csr_hpm_event_value [831:800], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent26_wdata, Q = \cpu.csr_hpm_event_value [863:832], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent27_wdata, Q = \cpu.csr_hpm_event_value [895:864], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent28_wdata, Q = \cpu.csr_hpm_event_value [927:896], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent29_wdata, Q = \cpu.csr_hpm_event_value [959:928], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent30_wdata, Q = \cpu.csr_hpm_event_value [991:960], rval = 0).
Adding SRST signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = \cpu.csr_mhpmevent31_wdata, Q = \cpu.csr_hpm_event_value [1023:992], rval = 0).
Adding EN signal on $flatten\cpu.$procdff$5667 ($dff) from module processorci_top (D = 64'0000000000000000000000000000000000000000000000000000000000000000, Q = { \cpu.csr_hpm_event_value [95:64] \cpu.csr_hpm_event_value [31:0] }).
Adding EN signal on $auto$ff.cc:266:slice$5937 ($sdff) from module processorci_top (D = 0, Q = \cpu.csr_hpm_event_value [63:32]).
Adding SRST signal on $flatten\cpu.$procdff$5666 ($dff) from module processorci_top (D = \cpu.csr_custom_next, Q = \cpu.csr_custom_value, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6086 ($sdff) from module processorci_top (D = \cpu.csr_next, Q = \cpu.csr_custom_value).
Adding SRST signal on $flatten\cpu.$procdff$5657 ($dff) from module processorci_top (D = \cpu.mem_rd_enable, Q = \cpu.mem_rd_enable_q, rval = 1'0).
Adding EN signal on $flatten\ResetBootSystem.$procdff$5656 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$5654 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5598 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1952_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1946_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1937_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1928_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1919_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1910_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1892_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1901_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6105 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$6105 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1946_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1937_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1928_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1919_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1910_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1892_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1901_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5596 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1868_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$6110 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1868_Y, Q = \Controller.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5595 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1857_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$6116 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1582_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5594 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5593 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1846_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$6121 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1846_Y, Q = \Controller.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5592 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1835_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6127 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5590 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1812_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1803_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1794_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1785_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1776_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1767_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1749_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1758_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6129 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5589 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1731_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$6133 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1622_Y, Q = \Controller.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5588 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1726_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6137 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5587 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1718_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$6139 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1633_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5585 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5584 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$5583 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1695_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$6145 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1442_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$5582 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1439_DATA, Q = \Controller.Uart.TX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$5578 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1690_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$6152 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1458_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$5583 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1695_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$6154 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1442_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$5582 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1439_DATA, Q = \Controller.Uart.RX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$5578 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1690_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$6161 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1458_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5646 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2866_Y, Q = \Controller.Uart.state_read, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$6163 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2866_Y, Q = \Controller.Uart.state_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5645 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2891_Y, Q = \Controller.Uart.counter_read, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$6167 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2891_Y, Q = \Controller.Uart.counter_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5644 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2855_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5643 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2906_Y, Q = \Controller.Uart.read_data, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6184 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2904_Y, Q = \Controller.Uart.read_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5642 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2844_Y, Q = \Controller.Uart.read_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5641 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2788_Y, Q = \Controller.Uart.state_write, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$6191 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2788_Y, Q = \Controller.Uart.state_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5640 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2810_Y, Q = \Controller.Uart.counter_write, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$6195 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2810_Y, Q = \Controller.Uart.counter_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5639 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2824_Y, Q = \Controller.Uart.write_data_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6205 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2824_Y, Q = \Controller.Uart.write_data_buffer).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5638 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2838_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6215 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5637 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2770_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5636 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2780_Y, Q = \Controller.Uart.write_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5635 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2761_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6229 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5634 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2756_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5632 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2751_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6232 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5631 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2727_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5630 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2735_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5629 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2274_Y, Q = \Controller.Interpreter.temp_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5628 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2317_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$6249 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2317_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]).
Adding EN signal on $auto$ff.cc:266:slice$6249 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2317_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5627 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2327_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6264 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2327_Y, Q = \Controller.Interpreter.timeout_counter).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5626 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5625 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2368_Y, Q = \Controller.Interpreter.read_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5624 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2396_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6280 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5623 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2421_Y, Q = \Controller.Interpreter.num_of_positions).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5622 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2443_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$6291 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5621 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2449_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6293 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2449_Y, Q = \Controller.Interpreter.return_state).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5620 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2473_Y, Q = \Controller.Interpreter.memory_page_number).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5619 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2481_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6308 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2481_Y, Q = \Controller.Interpreter.memory_mux_selector).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5618 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2521_Y, Q = \Controller.Interpreter.end_position, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6312 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2521_Y, Q = \Controller.Interpreter.end_position).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5616 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2563_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6316 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2563_Y, Q = \Controller.Interpreter.bus_mode).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5615 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2102_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5614 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2574_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5613 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2207_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5612 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2584_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6329 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2584_Y, Q = \Controller.Interpreter.core_clk_enable).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5611 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5610 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2226_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5609 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2249_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5608 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2159_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5607 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2660_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6345 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2660_Y, Q = \Controller.Interpreter.counter).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5606 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2002_Y, Q = \Controller.Interpreter.state, rval = 8'00000000).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5605 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2684_Y, Q = \Controller.Interpreter.write_data).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5604 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2710_Y, Q = \Controller.Interpreter.address).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5603 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2126_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5602 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2148_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$5599 ($dff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1976_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6368 ($sdff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1976_Y, Q = \Controller.ClkDivider.pulse_counter).
Adding SRST signal on $flatten\Controller.$procdff$5653 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2927_Y, Q = \Controller.finish_execution, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6376 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2927_Y, Q = \Controller.finish_execution).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6085 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6268 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6268 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6268 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6268 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6268 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6268 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6268 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6268 ($dffe) from module processorci_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 33 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 34 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 35 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 36 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 37 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 38 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 39 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 40 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 41 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 42 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 43 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 44 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 45 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 46 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 47 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 48 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 49 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 50 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 51 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 52 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 53 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 54 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 55 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 56 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 57 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 58 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 59 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 60 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 61 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 62 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.
Setting constant 0-bit at position 63 on $auto$ff.cc:266:slice$6084 ($dffe) from module processorci_top.

13.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 169 unused cells and 147 unused wires.
<suppressed ~176 debug messages>

13.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~31 debug messages>

13.13.9. Rerunning OPT passes. (Maybe there is more to do..)

13.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/4 on $pmux $flatten\cpu.$procmux$4513.
    dead port 2/4 on $pmux $flatten\cpu.$procmux$4513.
    dead port 3/4 on $pmux $flatten\cpu.$procmux$4513.
Removed 3 multiplexer ports.
<suppressed ~246 debug messages>

13.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$6135: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 1 changes.

13.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~60 debug messages>
Removed a total of 20 cells.

13.13.13. Executing OPT_DFF pass (perform DFF optimizations).

13.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 25 unused wires.
<suppressed ~2 debug messages>

13.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

13.13.16. Rerunning OPT passes. (Maybe there is more to do..)

13.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~245 debug messages>

13.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

13.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.13.20. Executing OPT_DFF pass (perform DFF optimizations).

13.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
<suppressed ~1 debug messages>

13.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.13.23. Rerunning OPT passes. (Maybe there is more to do..)

13.13.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~245 debug messages>

13.13.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

13.13.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.13.27. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $auto$ff.cc:266:slice$5936 ($sdff) from module processorci_top (D = \cpu.csr_hpm_counterh_value [63:32], Q = \cpu.csr_hpm_counterh_value [63:32]).
Handling D = Q on $auto$ff.cc:266:slice$6385 ($sdffe) from module processorci_top (conecting SRST instead).
Adding EN signal on $auto$ff.cc:266:slice$5935 ($sdff) from module processorci_top (D = \cpu.csr_hpm_counter_value [63:32], Q = \cpu.csr_hpm_counter_value [63:32]).
Handling D = Q on $auto$ff.cc:266:slice$6389 ($sdffe) from module processorci_top (conecting SRST instead).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6389 ($dffe) from module processorci_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6385 ($dffe) from module processorci_top.

13.13.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 2 unused cells and 2 unused wires.
<suppressed ~3 debug messages>

13.13.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.13.30. Rerunning OPT passes. (Maybe there is more to do..)

13.13.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~245 debug messages>

13.13.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

13.13.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.13.34. Executing OPT_DFF pass (perform DFF optimizations).

13.13.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

13.13.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.13.37. Finished OPT passes. (There is nothing left to do.)

13.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$5682 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1249 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$5682 (Controller.Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1249 (Controller.Memory.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$5681 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1439 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$5681 (Controller.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1439 (Controller.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5887 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5912 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5862 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1540 ($gt).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1497 ($eq).
Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1501 ($add).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1504 ($add).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1513 ($lt).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1518 ($eq).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1520 ($ge).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2003_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2004_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2006 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2008_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2009_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2010_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2011_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2012_CMP0 ($eq).
Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2014 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2016_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2017_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2019 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2021_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2022_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2026_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2027_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2028_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2030 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2032_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2033_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2034_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2036 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2038_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2040 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2042_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2043_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2044_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2045_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2046_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2047_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2048_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2050 ($mux).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2052_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2054 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2056_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2057_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2059 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2061_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2062_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2065_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2064 ($pmux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2066_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2067_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2068_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2069_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2070_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2071_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2072_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2073_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2074_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2075_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2076_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2077_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2078_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2079_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2080_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2081_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2082_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2083_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2084_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2085_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2086_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2087_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2088_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2090 ($mux).
Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2092_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2094 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2128_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2129_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2130_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2163_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2318_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2319_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2320_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2363_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2489_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2522_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2523_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2596_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2597_CMP0 ($eq).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$1471 ($lt).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1476 ($lt).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2775_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2781_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2782_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2794_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2796 ($mux).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2845_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2846_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2860_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2868_CMP0 ($eq).
Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2876 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1687 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1675 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1459 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1459 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1458 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1457 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1456 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1442 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1441 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1440 ($eq).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1687 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1675 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1459 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1459 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1458 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1457 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1456 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1442 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1441 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1440 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5873 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1611 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1610 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1609 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1608 ($mux).
Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1603 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1601 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1577 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1569 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1567 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1564 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1563 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1559 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1554 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1553 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1552 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1551 ($mux).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1547 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1545 ($eq).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2918 ($mux).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2918 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$1226 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1210 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1209 ($mux).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6381 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6371 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6095 ($ne).
Removed top 3 bits (of 5) from mux cell processorci_top.$flatten\cpu.$procmux$4974 ($mux).
Removed top 2 bits (of 5) from mux cell processorci_top.$flatten\cpu.$procmux$5031 ($mux).
Removed top 1 bits (of 5) from mux cell processorci_top.$flatten\cpu.$procmux$5085 ($mux).
Removed cell processorci_top.$flatten\cpu.$procmux$5551 ($mux).
Removed cell processorci_top.$flatten\cpu.$procmux$5563 ($mux).
Removed cell processorci_top.$flatten\cpu.$procmux$5565 ($mux).
Removed top 19 bits (of 32) from mux cell processorci_top.$flatten\cpu.$procmux$5569 ($mux).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\cpu.$procmux$4538_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4494_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4493_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4492_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4483_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4482_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4481_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4472_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4471_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4470_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4461_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4460_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4459_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4450_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4449_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4448_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4439_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4438_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4437_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4428_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4427_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4426_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4417_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4416_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4415_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4406_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4405_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4404_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4395_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4394_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4393_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4384_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4383_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4382_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4373_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4372_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4371_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4362_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4361_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4360_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4351_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4350_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4349_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4340_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4339_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4338_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4329_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4328_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4327_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4318_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4317_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4316_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4307_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4306_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4305_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4296_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4295_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4294_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4285_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4284_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4283_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4274_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4273_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4272_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4263_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4262_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4261_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4252_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4251_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4250_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4241_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4240_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4239_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4230_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4229_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4228_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4219_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4218_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4217_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4208_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4207_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4206_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4197_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4196_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4195_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4186_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4185_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$procmux$4184_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\cpu.$procmux$4090_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\cpu.$procmux$4089_CMP0 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\cpu.$procmux$4065 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\cpu.$procmux$3992 ($mux).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\cpu.$procmux$3930_CMP0 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\cpu.$procmux$3838 ($mux).
Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\cpu.$procmux$3790_CMP0 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\cpu.$procmux$3787 ($mux).
Removed top 1 bits (of 5) from port B of cell processorci_top.$flatten\cpu.$procmux$3788_CMP2 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\cpu.$procmux$3788_CMP1 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\cpu.$procmux$3744_CMP0 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\cpu.$procmux$3741 ($mux).
Removed top 1 bits (of 5) from port B of cell processorci_top.$flatten\cpu.$procmux$3742_CMP2 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\cpu.$procmux$3742_CMP1 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\cpu.$procmux$3689_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\cpu.$procmux$3686_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\cpu.$procmux$3685_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\cpu.$procmux$3641_CMP0 ($eq).
Removed top 1 bits (of 10) from port B of cell processorci_top.$flatten\cpu.$procmux$3638_CMP0 ($eq).
Removed top 9 bits (of 10) from port B of cell processorci_top.$flatten\cpu.$procmux$3637_CMP0 ($eq).
Removed top 8 bits (of 10) from port B of cell processorci_top.$flatten\cpu.$procmux$3636_CMP0 ($eq).
Removed top 8 bits (of 10) from port B of cell processorci_top.$flatten\cpu.$procmux$3635_CMP0 ($eq).
Removed top 7 bits (of 10) from port B of cell processorci_top.$flatten\cpu.$procmux$3634_CMP0 ($eq).
Removed top 7 bits (of 10) from port B of cell processorci_top.$flatten\cpu.$procmux$3633_CMP0 ($eq).
Removed top 1 bits (of 10) from port B of cell processorci_top.$flatten\cpu.$procmux$3632_CMP0 ($eq).
Removed top 7 bits (of 10) from port B of cell processorci_top.$flatten\cpu.$procmux$3631_CMP0 ($eq).
Removed top 7 bits (of 10) from port B of cell processorci_top.$flatten\cpu.$procmux$3630_CMP0 ($eq).
Removed top 3 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$procmux$3570_CMP0 ($eq).
Removed top 11 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$procmux$3512_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$procmux$3511_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\cpu.$procmux$2997_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$669 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$667 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$665 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$663 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$661 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$659 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$657 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$655 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$653 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$651 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$649 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$647 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$645 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$643 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$641 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$639 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$637 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$635 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$633 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$631 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$629 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$627 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$625 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$623 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$621 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$619 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$617 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$615 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:605$613 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:573$487 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:573$485 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:573$483 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:573$481 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:573$479 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:573$477 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:573$475 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:573$473 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:573$471 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:573$469 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:568$455 ($ne).
Removed top 31 bits (of 32) from port A of cell processorci_top.$flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1222$430 ($sub).
Removed top 29 bits (of 32) from mux cell processorci_top.$flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1222$429 ($mux).
Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1102$418 ($shr).
Removed top 25 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1059$409 ($add).
Removed top 20 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:944$382 ($lt).
Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:932$379 ($shl).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:757$256 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:756$255 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$254 ($add).
Removed cell processorci_top.$flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:724$148 ($mux).
Removed cell processorci_top.$flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:724$147 ($mux).
Removed top 24 bits (of 32) from mux cell processorci_top.$flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:724$145 ($mux).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:654$33 ($add).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2944_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$1196 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1195 ($add).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1195 ($add).
Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1194 ($lt).
Removed top 19 bits (of 30) from FF cell processorci_top.$auto$ff.cc:266:slice$5920 ($dff).
Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1209_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_ADDR[31:0]$1253.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2006_Y.
Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2014_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2019_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2030_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2036_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2040_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2050_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2054_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2059_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2064_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2090_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2094_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1247_ADDR[31:0]$1253.
Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2796_Y.
Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2876_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_ADDR[5:0]$1444.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_ADDR[5:0]$1453.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1441_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1457_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1458_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_ADDR[5:0]$1444.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1434_ADDR[5:0]$1453.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1441_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1457_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1442_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1458_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1608_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1609_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1610_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1611_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1551_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1552_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1553_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1554_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1195_Y.
Removed top 19 bits (of 32) from wire processorci_top.$flatten\cpu.$0\csr_mstatus_value[31:0].
Removed top 1 bits (of 5) from wire processorci_top.$flatten\cpu.$17\irq_num[4:0].
Removed top 2 bits (of 5) from wire processorci_top.$flatten\cpu.$18\irq_num[4:0].
Removed top 3 bits (of 5) from wire processorci_top.$flatten\cpu.$19\irq_num[4:0].
Removed top 31 bits (of 32) from wire processorci_top.$flatten\cpu.$3\hpm_increment[31:0].
Removed top 31 bits (of 32) from wire processorci_top.$flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:944$382_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:945$383_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:962$393_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:963$394_Y.
Removed top 29 bits (of 32) from wire processorci_top.$flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1222$429_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\cpu.$ternary$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:757$256_Y.

13.15. Executing PEEPOPT pass (run peephole optimizers).

13.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 51 unused wires.
<suppressed ~1 debug messages>

13.17. Executing SHARE pass (SAT-based resource sharing).
Found 12 cells in module processorci_top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\cpu.$sshr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:966$397 ($sshr):
    Found 2 activation_patterns using ctrl signal { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3641_CMP }.
    Found 1 candidates: $flatten\cpu.$sshr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:951$389
    Analyzing resource sharing with $flatten\cpu.$sshr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:951$389 ($sshr):
      Found 2 activation_patterns using ctrl signal { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3689_CMP }.
      Activation pattern for cell $flatten\cpu.$sshr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:966$397: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3641_CMP } = 5'01011
      Activation pattern for cell $flatten\cpu.$sshr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:966$397: { \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1111
      Activation pattern for cell $flatten\cpu.$sshr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:951$389: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3689_CMP } = 5'01011
      Activation pattern for cell $flatten\cpu.$sshr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:951$389: { \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1111
      Size of SAT problem: 0 cells, 8934 variables, 25168 clauses
      According to the SAT solver this pair of cells can be shared.
      Activation signal for $flatten\cpu.$sshr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:966$397: $auto$share.cc:987:make_cell_activation_logic$6444
      New cell: $auto$share.cc:667:make_supercell$6451 ($sshr)
  Analyzing resource sharing options for $auto$share.cc:667:make_supercell$6451 ($sshr):
    Found 4 activation_patterns using ctrl signal { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3641_CMP $flatten\cpu.$procmux$3689_CMP }.
    No candidates found.
  Analyzing resource sharing options for $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:965$396 ($shr):
    Found 2 activation_patterns using ctrl signal { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3641_CMP }.
    Found 2 candidates: $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:950$388 $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1102$418
    Analyzing resource sharing with $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:950$388 ($shr):
      Found 2 activation_patterns using ctrl signal { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3689_CMP }.
      Activation pattern for cell $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:965$396: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3641_CMP } = 5'01011
      Activation pattern for cell $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:965$396: { \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1111
      Activation pattern for cell $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:950$388: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3689_CMP } = 5'01011
      Activation pattern for cell $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:950$388: { \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1111
      Size of SAT problem: 0 cells, 8934 variables, 25168 clauses
      According to the SAT solver this pair of cells can be shared.
      Activation signal for $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:965$396: $auto$share.cc:987:make_cell_activation_logic$6457
      New cell: $auto$share.cc:667:make_supercell$6464 ($shr)
  Analyzing resource sharing options for $auto$share.cc:667:make_supercell$6464 ($shr):
    Found 4 activation_patterns using ctrl signal { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3641_CMP $flatten\cpu.$procmux$3689_CMP }.
    Found 1 candidates: $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1102$418
    Analyzing resource sharing with $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1102$418 ($shr):
      Found 5 activation_patterns using ctrl signal { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$2995_CMP $flatten\cpu.$procmux$2996_CMP $flatten\cpu.$procmux$2997_CMP $flatten\cpu.$procmux$2998_CMP }.
      Activation pattern for cell $auto$share.cc:667:make_supercell$6464: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3641_CMP } = 5'01011
      Activation pattern for cell $auto$share.cc:667:make_supercell$6464: { \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1111
      Activation pattern for cell $auto$share.cc:667:make_supercell$6464: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3689_CMP } = 5'01011
      Activation pattern for cell $auto$share.cc:667:make_supercell$6464: { \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1111
      Activation pattern for cell $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1102$418: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$2995_CMP $flatten\cpu.$procmux$2996_CMP $flatten\cpu.$procmux$2997_CMP $flatten\cpu.$procmux$2998_CMP } = 7'1100000
      Activation pattern for cell $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1102$418: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$2995_CMP } = 4'1101
      Activation pattern for cell $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1102$418: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$2996_CMP } = 4'1101
      Activation pattern for cell $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1102$418: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$2997_CMP } = 4'1101
      Activation pattern for cell $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1102$418: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$2998_CMP } = 4'1101
      Size of SAT problem: 0 cells, 8988 variables, 25342 clauses
      According to the SAT solver this pair of cells can be shared.
      Activation signal for $auto$share.cc:667:make_supercell$6464: $auto$share.cc:987:make_cell_activation_logic$6472
      New cell: $auto$share.cc:667:make_supercell$6479 ($shr)
  Analyzing resource sharing options for $auto$share.cc:667:make_supercell$6479 ($shr):
    Found 9 activation_patterns using ctrl signal { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$2995_CMP $flatten\cpu.$procmux$2996_CMP $flatten\cpu.$procmux$2997_CMP $flatten\cpu.$procmux$2998_CMP $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3641_CMP $flatten\cpu.$procmux$3689_CMP }.
    No candidates found.
  Analyzing resource sharing options for $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:961$392 ($shl):
    Found 2 activation_patterns using ctrl signal { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3641_CMP }.
    Found 2 candidates: $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:949$387 $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:932$379
    Analyzing resource sharing with $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:949$387 ($shl):
      Found 2 activation_patterns using ctrl signal { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3689_CMP }.
      Activation pattern for cell $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:961$392: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3641_CMP } = 5'01011
      Activation pattern for cell $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:961$392: { \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1111
      Activation pattern for cell $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:949$387: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3689_CMP } = 5'01011
      Activation pattern for cell $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:949$387: { \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1111
      Size of SAT problem: 0 cells, 8934 variables, 25168 clauses
      According to the SAT solver this pair of cells can be shared.
      Activation signal for $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:961$392: $auto$share.cc:987:make_cell_activation_logic$6485
      New cell: $auto$share.cc:667:make_supercell$6492 ($shl)
  Analyzing resource sharing options for $auto$share.cc:667:make_supercell$6492 ($shl):
    Found 4 activation_patterns using ctrl signal { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3641_CMP $flatten\cpu.$procmux$3689_CMP }.
    Found 1 candidates: $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:932$379
    Analyzing resource sharing with $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:932$379 ($shl):
      Found 1 activation_patterns using ctrl signal { \cpu.mem_wr_enable $flatten\cpu.$procmux$3742_CTRL $flatten\cpu.$procmux$3744_CMP \Controller.Data_Memory.memory_write \Controller.Interpreter.memory_mux_selector }.
      Activation pattern for cell $auto$share.cc:667:make_supercell$6492: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3641_CMP } = 5'01011
      Activation pattern for cell $auto$share.cc:667:make_supercell$6492: { \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1111
      Activation pattern for cell $auto$share.cc:667:make_supercell$6492: { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3689_CMP } = 5'01011
      Activation pattern for cell $auto$share.cc:667:make_supercell$6492: { \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1111
      Activation pattern for cell $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:932$379: { \cpu.mem_wr_enable $flatten\cpu.$procmux$3742_CTRL $flatten\cpu.$procmux$3744_CMP \Controller.Data_Memory.memory_write \Controller.Interpreter.memory_mux_selector } = 5'11111
      Size of SAT problem: 0 cells, 9001 variables, 25354 clauses
      According to the SAT solver this pair of cells can be shared.
      Activation signal for $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:932$379: $auto$share.cc:977:make_cell_activation_logic$6495
      New cell: $auto$share.cc:667:make_supercell$6502 ($shl)
  Analyzing resource sharing options for $auto$share.cc:667:make_supercell$6502 ($shl):
    Found 5 activation_patterns using ctrl signal { \cpu.mem_wr_enable \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3641_CMP $flatten\cpu.$procmux$3689_CMP $flatten\cpu.$procmux$3742_CTRL $flatten\cpu.$procmux$3744_CMP \Controller.Data_Memory.memory_write \Controller.Interpreter.memory_mux_selector }.
    No candidates found.
  Analyzing resource sharing options for $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435 ($memrd):
    Found 45 activation_patterns using ctrl signal { \cpu.mem_wr_enable \cpu.mem_rd_enable_q \cpu.next_wr \cpu.illinsn $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3485_CMP $flatten\cpu.$procmux$3630_CMP $flatten\cpu.$procmux$3631_CMP $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3634_CMP $flatten\cpu.$procmux$3635_CMP $flatten\cpu.$procmux$3636_CMP $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3638_CMP $flatten\cpu.$procmux$3639_CMP $flatten\cpu.$procmux$3641_CMP $flatten\cpu.$procmux$3682_CMP $flatten\cpu.$procmux$3683_CMP $flatten\cpu.$procmux$3684_CMP $flatten\cpu.$procmux$3742_CTRL $flatten\cpu.$procmux$3744_CMP $flatten\cpu.$procmux$3839_CMP $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3895_CMP $flatten\cpu.$procmux$3930_CMP \Controller.Data_Memory.memory_write \Controller.Interpreter.memory_mux_selector }.
    Found 1 candidates: $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432
    Analyzing resource sharing with $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432 ($memrd):
      Found 83 activation_patterns using ctrl signal { \cpu.imem_data [14] \cpu.mem_wr_enable \cpu.mem_rd_enable \cpu.mem_rd_enable_q \cpu.next_wr \cpu.illinsn \cpu.cycle_insn $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3485_CMP $flatten\cpu.$procmux$3630_CMP $flatten\cpu.$procmux$3631_CMP $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3634_CMP $flatten\cpu.$procmux$3635_CMP $flatten\cpu.$procmux$3636_CMP $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3638_CMP $flatten\cpu.$procmux$3639_CMP $flatten\cpu.$procmux$3641_CMP $flatten\cpu.$procmux$3682_CMP $flatten\cpu.$procmux$3683_CMP $flatten\cpu.$procmux$3684_CMP $flatten\cpu.$procmux$3685_CMP $flatten\cpu.$procmux$3686_CMP $flatten\cpu.$procmux$3689_CMP $flatten\cpu.$procmux$3742_CTRL $flatten\cpu.$procmux$3744_CMP $flatten\cpu.$procmux$3788_CTRL $flatten\cpu.$procmux$3790_CMP $flatten\cpu.$procmux$3839_CMP $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3895_CMP $flatten\cpu.$procmux$3930_CMP $flatten\cpu.$procmux$3993_CMP $flatten\cpu.$procmux$3995_CMP $flatten\cpu.$procmux$4536_CMP $flatten\cpu.$procmux$4537_CMP $flatten\cpu.$procmux$4538_CMP \Controller.Data_Memory.memory_write \Controller.Interpreter.memory_mux_selector }.
      Forbidden control signals for this pair of cells: { \cpu.mem_wr_enable \cpu.mem_rd_enable \cpu.next_wr \cpu.illinsn \cpu.cycle_insn $flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:887$361_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:888$363_Y $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:889$365_Y $flatten\cpu.$ge$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:890$367_Y $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:891$369_Y $flatten\cpu.$ge$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:892$371_Y $flatten\cpu.$procmux$3742_CTRL $flatten\cpu.$procmux$3788_CTRL $flatten\cpu.$procmux$3839_CMP $flatten\cpu.$procmux$3993_CMP $flatten\cpu.$procmux$4184_CMP $flatten\cpu.$procmux$4185_CMP $flatten\cpu.$procmux$4186_CMP $flatten\cpu.$procmux$4195_CMP $flatten\cpu.$procmux$4196_CMP $flatten\cpu.$procmux$4197_CMP $flatten\cpu.$procmux$4206_CMP $flatten\cpu.$procmux$4207_CMP $flatten\cpu.$procmux$4208_CMP $flatten\cpu.$procmux$4217_CMP $flatten\cpu.$procmux$4218_CMP $flatten\cpu.$procmux$4219_CMP $flatten\cpu.$procmux$4228_CMP $flatten\cpu.$procmux$4229_CMP $flatten\cpu.$procmux$4230_CMP $flatten\cpu.$procmux$4239_CMP $flatten\cpu.$procmux$4240_CMP $flatten\cpu.$procmux$4241_CMP $flatten\cpu.$procmux$4250_CMP $flatten\cpu.$procmux$4251_CMP $flatten\cpu.$procmux$4252_CMP $flatten\cpu.$procmux$4261_CMP $flatten\cpu.$procmux$4262_CMP $flatten\cpu.$procmux$4263_CMP $flatten\cpu.$procmux$4272_CMP $flatten\cpu.$procmux$4273_CMP $flatten\cpu.$procmux$4274_CMP $flatten\cpu.$procmux$4283_CMP $flatten\cpu.$procmux$4284_CMP $flatten\cpu.$procmux$4285_CMP $flatten\cpu.$procmux$4294_CMP $flatten\cpu.$procmux$4295_CMP $flatten\cpu.$procmux$4296_CMP $flatten\cpu.$procmux$4305_CMP $flatten\cpu.$procmux$4306_CMP $flatten\cpu.$procmux$4307_CMP $flatten\cpu.$procmux$4316_CMP $flatten\cpu.$procmux$4317_CMP $flatten\cpu.$procmux$4318_CMP $flatten\cpu.$procmux$4327_CMP $flatten\cpu.$procmux$4328_CMP $flatten\cpu.$procmux$4329_CMP $flatten\cpu.$procmux$4338_CMP $flatten\cpu.$procmux$4339_CMP $flatten\cpu.$procmux$4340_CMP $flatten\cpu.$procmux$4349_CMP $flatten\cpu.$procmux$4350_CMP $flatten\cpu.$procmux$4351_CMP $flatten\cpu.$procmux$4360_CMP $flatten\cpu.$procmux$4361_CMP $flatten\cpu.$procmux$4362_CMP $flatten\cpu.$procmux$4371_CMP $flatten\cpu.$procmux$4372_CMP $flatten\cpu.$procmux$4373_CMP $flatten\cpu.$procmux$4382_CMP $flatten\cpu.$procmux$4383_CMP $flatten\cpu.$procmux$4384_CMP $flatten\cpu.$procmux$4393_CMP $flatten\cpu.$procmux$4394_CMP $flatten\cpu.$procmux$4395_CMP $flatten\cpu.$procmux$4404_CMP $flatten\cpu.$procmux$4405_CMP $flatten\cpu.$procmux$4406_CMP $flatten\cpu.$procmux$4415_CMP $flatten\cpu.$procmux$4416_CMP $flatten\cpu.$procmux$4417_CMP $flatten\cpu.$procmux$4426_CMP $flatten\cpu.$procmux$4427_CMP $flatten\cpu.$procmux$4428_CMP $flatten\cpu.$procmux$4437_CMP $flatten\cpu.$procmux$4438_CMP $flatten\cpu.$procmux$4439_CMP $flatten\cpu.$procmux$4448_CMP $flatten\cpu.$procmux$4449_CMP $flatten\cpu.$procmux$4450_CMP $flatten\cpu.$procmux$4459_CMP $flatten\cpu.$procmux$4460_CMP $flatten\cpu.$procmux$4461_CMP $flatten\cpu.$procmux$4470_CMP $flatten\cpu.$procmux$4471_CMP $flatten\cpu.$procmux$4472_CMP $flatten\cpu.$procmux$4481_CMP $flatten\cpu.$procmux$4482_CMP $flatten\cpu.$procmux$4483_CMP $flatten\cpu.$procmux$4492_CMP $flatten\cpu.$procmux$4493_CMP $flatten\cpu.$procmux$4494_CMP $flatten\Controller.$eq$/eda/processor-ci-controller/src/controller.v:118$1243_Y $flatten\Controller.$logic_or$/eda/processor-ci-controller/src/controller.v:121$1246_Y \Controller.Data_Memory.memory_write }
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3634_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3634_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3638_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3638_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3744_CMP \Controller.Interpreter.memory_mux_selector } = 3'011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3631_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3631_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3930_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3930_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3635_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3635_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3636_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3636_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3683_CMP $flatten\cpu.$procmux$3841_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3683_CMP $flatten\cpu.$procmux$3841_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3684_CMP $flatten\cpu.$procmux$3841_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3684_CMP $flatten\cpu.$procmux$3841_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3682_CMP $flatten\cpu.$procmux$3841_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3682_CMP $flatten\cpu.$procmux$3841_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3895_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3895_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3485_CMP $flatten\cpu.$procmux$3841_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3485_CMP $flatten\cpu.$procmux$3841_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3630_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3630_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3639_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3639_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$435: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3634_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3634_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3684_CMP $flatten\cpu.$procmux$3689_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3684_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3638_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3638_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3689_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3689_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3689_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3631_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3631_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3683_CMP $flatten\cpu.$procmux$3689_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3683_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3930_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3930_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3635_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3635_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3636_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3636_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3685_CMP $flatten\cpu.$procmux$3689_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3685_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3686_CMP $flatten\cpu.$procmux$3689_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3686_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3683_CMP $flatten\cpu.$procmux$3841_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3683_CMP $flatten\cpu.$procmux$3841_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3684_CMP $flatten\cpu.$procmux$3841_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3684_CMP $flatten\cpu.$procmux$3841_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3682_CMP $flatten\cpu.$procmux$3841_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3682_CMP $flatten\cpu.$procmux$3841_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3895_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3895_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3485_CMP $flatten\cpu.$procmux$3841_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3485_CMP $flatten\cpu.$procmux$3841_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3630_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3630_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3682_CMP $flatten\cpu.$procmux$3689_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3682_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3639_CMP $flatten\cpu.$procmux$3641_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3639_CMP $flatten\cpu.$procmux$3641_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3744_CMP } = 2'01
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3744_CMP } = 4'0001
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3744_CMP } = 5'00001
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3744_CMP \Controller.Interpreter.memory_mux_selector } = 3'011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3485_CMP $flatten\cpu.$procmux$3689_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3485_CMP $flatten\cpu.$procmux$3689_CMP } = 4'1011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3485_CMP $flatten\cpu.$procmux$3995_CMP } = 6'000011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3485_CMP $flatten\cpu.$procmux$3995_CMP } = 5'00011
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3790_CMP } = 2'01
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3790_CMP } = 4'0001
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3790_CMP } = 5'00001
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.imem_data [14] $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$4538_CMP } = 3'001
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.imem_data [14] $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$4536_CMP } = 3'001
      Activation pattern for cell $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432: { \cpu.imem_data [14] $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$4537_CMP } = 3'001
      Size of SAT problem: 0 cells, 1265 variables, 3649 clauses
      According to the SAT solver this pair of cells can not be shared.
      Model from SAT solver: { \cpu.imem_data [14] \cpu.mem_rd_enable_q $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:453$434_Y $flatten\cpu.$procmux$3485_CMP $flatten\cpu.$procmux$3630_CMP $flatten\cpu.$procmux$3631_CMP $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3634_CMP $flatten\cpu.$procmux$3635_CMP $flatten\cpu.$procmux$3636_CMP $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3638_CMP $flatten\cpu.$procmux$3639_CMP $flatten\cpu.$procmux$3641_CMP $flatten\cpu.$procmux$3682_CMP $flatten\cpu.$procmux$3683_CMP $flatten\cpu.$procmux$3684_CMP $flatten\cpu.$procmux$3685_CMP $flatten\cpu.$procmux$3686_CMP $flatten\cpu.$procmux$3689_CMP $flatten\cpu.$procmux$3744_CMP $flatten\cpu.$procmux$3790_CMP $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3895_CMP $flatten\cpu.$procmux$3930_CMP $flatten\cpu.$procmux$3995_CMP $flatten\cpu.$procmux$4536_CMP $flatten\cpu.$procmux$4537_CMP $flatten\cpu.$procmux$4538_CMP \Controller.Interpreter.memory_mux_selector } = 34'1000000000000000000000000011000000
  Analyzing resource sharing options for $flatten\cpu.$memrd$\regfile$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$432 ($memrd):
    Found 83 activation_patterns using ctrl signal { \cpu.imem_data [14] \cpu.mem_wr_enable \cpu.mem_rd_enable \cpu.mem_rd_enable_q \cpu.next_wr \cpu.illinsn \cpu.cycle_insn $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1054$403_Y $flatten\cpu.$logic_not$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:452$431_Y $flatten\cpu.$procmux$3485_CMP $flatten\cpu.$procmux$3630_CMP $flatten\cpu.$procmux$3631_CMP $flatten\cpu.$procmux$3632_CMP $flatten\cpu.$procmux$3633_CMP $flatten\cpu.$procmux$3634_CMP $flatten\cpu.$procmux$3635_CMP $flatten\cpu.$procmux$3636_CMP $flatten\cpu.$procmux$3637_CMP $flatten\cpu.$procmux$3638_CMP $flatten\cpu.$procmux$3639_CMP $flatten\cpu.$procmux$3641_CMP $flatten\cpu.$procmux$3682_CMP $flatten\cpu.$procmux$3683_CMP $flatten\cpu.$procmux$3684_CMP $flatten\cpu.$procmux$3685_CMP $flatten\cpu.$procmux$3686_CMP $flatten\cpu.$procmux$3689_CMP $flatten\cpu.$procmux$3742_CTRL $flatten\cpu.$procmux$3744_CMP $flatten\cpu.$procmux$3788_CTRL $flatten\cpu.$procmux$3790_CMP $flatten\cpu.$procmux$3839_CMP $flatten\cpu.$procmux$3841_CMP $flatten\cpu.$procmux$3895_CMP $flatten\cpu.$procmux$3930_CMP $flatten\cpu.$procmux$3993_CMP $flatten\cpu.$procmux$3995_CMP $flatten\cpu.$procmux$4536_CMP $flatten\cpu.$procmux$4537_CMP $flatten\cpu.$procmux$4538_CMP \Controller.Data_Memory.memory_write \Controller.Interpreter.memory_mux_selector }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1249 ($memrd):
    Found 1 activation_patterns using ctrl signal { \Controller.Memory.memory_read $flatten\Controller.\Interpreter.$procmux$2046_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1249 ($memrd):
    Found 6 activation_patterns using ctrl signal { \cpu.mem_rd_enable_q \cpu.next_wr $flatten\cpu.$logic_or$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1019$402_Y $flatten\cpu.$procmux$2995_CMP $flatten\cpu.$procmux$2996_CMP $flatten\cpu.$procmux$2997_CMP $flatten\cpu.$procmux$2998_CMP \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$2046_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.
Removing 10 cells in module processorci_top:
  Removing cell $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:932$379 ($shl).
  Removing cell $auto$share.cc:667:make_supercell$6492 ($shl).
  Removing cell $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:949$387 ($shl).
  Removing cell $flatten\cpu.$shl$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:961$392 ($shl).
  Removing cell $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1102$418 ($shr).
  Removing cell $auto$share.cc:667:make_supercell$6464 ($shr).
  Removing cell $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:950$388 ($shr).
  Removing cell $flatten\cpu.$shr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:965$396 ($shr).
  Removing cell $flatten\cpu.$sshr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:951$389 ($sshr).
  Removing cell $flatten\cpu.$sshr$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:966$397 ($sshr).

13.18. Executing TECHMAP pass (map to technology primitives).

13.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/cmp2lut.v
Parsing Verilog input from `/usr/local/share/synlig/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

13.18.2. Continuing TECHMAP pass.
Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt.
No more expansions possible.
<suppressed ~275 debug messages>

13.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~3 debug messages>

13.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 19 unused wires.
<suppressed ~11 debug messages>

13.21. Executing TECHMAP pass (map to technology primitives).

13.21.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/mul2dsp.v
Parsing Verilog input from `/usr/local/share/synlig/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

13.21.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/dsp_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

13.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

13.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module processorci_top:
  creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1541 ($sub).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1496 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1500 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1501 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1504 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1511 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1515 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1503 ($sub).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1478 ($add).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1473 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1441 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1457 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1459 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1441 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1457 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1459 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1622 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1633 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1571 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1582 ($add).
  creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1195 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1059$409 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:654$33 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$254 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$260 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$263 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$266 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$269 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$272 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$275 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$278 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$281 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$284 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$287 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$290 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$293 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$296 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$299 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$302 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$305 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$308 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$311 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$314 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$317 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$320 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$323 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$326 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$329 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$332 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$335 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$338 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$341 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$344 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$347 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:857$351 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:863$352 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:875$356 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:887$362 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:919$377 ($add).
  creating $macc model for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:959$390 ($add).
  creating $macc model for $flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1222$430 ($sub).
  creating $macc model for $flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:960$391 ($sub).
  creating $alu model for $macc $flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:960$391.
  creating $alu model for $macc $flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1222$430.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:959$390.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:919$377.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:887$362.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:875$356.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:863$352.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:857$351.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$347.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$344.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$341.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$338.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$335.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$332.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$329.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$326.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$323.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$320.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$317.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$314.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$311.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$308.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$305.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$302.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$299.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$296.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$293.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$290.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$287.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$284.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$281.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$278.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$275.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$272.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$269.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$266.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$263.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$260.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$254.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:654$33.
  creating $alu model for $macc $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1059$409.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1195.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1582.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1571.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1633.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1622.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1459.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1457.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1441.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1459.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1457.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1441.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1473.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1478.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1503.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1515.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1511.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1504.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1501.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1500.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1496.
  creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1541.
  creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1540 ($gt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1520 ($ge): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1513 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1520.
  creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1194 ($lt): new $alu
  creating $alu model for $flatten\cpu.$ge$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:890$367 ($ge): new $alu
  creating $alu model for $flatten\cpu.$ge$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:892$371 ($ge): merged with $flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:960$391.
  creating $alu model for $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:889$365 ($lt): merged with $flatten\cpu.$ge$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:890$367.
  creating $alu model for $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:891$369 ($lt): merged with $flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:960$391.
  creating $alu model for $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:944$382 ($lt): new $alu
  creating $alu model for $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:945$383 ($lt): new $alu
  creating $alu model for $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:962$393 ($lt): merged with $flatten\cpu.$ge$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:890$367.
  creating $alu model for $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:963$394 ($lt): merged with $flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:960$391.
  creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1518 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1520.
  creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$1196 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1194.
  creating $alu model for $flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:887$361 ($eq): merged with $flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:960$391.
  creating $alu model for $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:888$363 ($ne): merged with $flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:960$391.
  creating $alu cell for $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:944$382: $auto$alumacc.cc:485:replace_alu$6515
  creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1194, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$1196: $auto$alumacc.cc:485:replace_alu$6528
  creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1520, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1513, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1518: $auto$alumacc.cc:485:replace_alu$6539
  creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1540: $auto$alumacc.cc:485:replace_alu$6552
  creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1541: $auto$alumacc.cc:485:replace_alu$6557
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1496: $auto$alumacc.cc:485:replace_alu$6560
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1500: $auto$alumacc.cc:485:replace_alu$6563
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1501: $auto$alumacc.cc:485:replace_alu$6566
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1504: $auto$alumacc.cc:485:replace_alu$6569
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1511: $auto$alumacc.cc:485:replace_alu$6572
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1515: $auto$alumacc.cc:485:replace_alu$6575
  creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1503: $auto$alumacc.cc:485:replace_alu$6578
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1478: $auto$alumacc.cc:485:replace_alu$6581
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1473: $auto$alumacc.cc:485:replace_alu$6584
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1441: $auto$alumacc.cc:485:replace_alu$6587
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1457: $auto$alumacc.cc:485:replace_alu$6590
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1459: $auto$alumacc.cc:485:replace_alu$6593
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1441: $auto$alumacc.cc:485:replace_alu$6596
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1457: $auto$alumacc.cc:485:replace_alu$6599
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1459: $auto$alumacc.cc:485:replace_alu$6602
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1622: $auto$alumacc.cc:485:replace_alu$6605
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1633: $auto$alumacc.cc:485:replace_alu$6608
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1571: $auto$alumacc.cc:485:replace_alu$6611
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1582: $auto$alumacc.cc:485:replace_alu$6614
  creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1195: $auto$alumacc.cc:485:replace_alu$6617
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1059$409: $auto$alumacc.cc:485:replace_alu$6620
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:654$33: $auto$alumacc.cc:485:replace_alu$6623
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$254: $auto$alumacc.cc:485:replace_alu$6626
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$260: $auto$alumacc.cc:485:replace_alu$6629
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$263: $auto$alumacc.cc:485:replace_alu$6632
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$266: $auto$alumacc.cc:485:replace_alu$6635
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$269: $auto$alumacc.cc:485:replace_alu$6638
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$272: $auto$alumacc.cc:485:replace_alu$6641
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$275: $auto$alumacc.cc:485:replace_alu$6644
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$278: $auto$alumacc.cc:485:replace_alu$6647
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$281: $auto$alumacc.cc:485:replace_alu$6650
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$284: $auto$alumacc.cc:485:replace_alu$6653
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$287: $auto$alumacc.cc:485:replace_alu$6656
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$290: $auto$alumacc.cc:485:replace_alu$6659
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$293: $auto$alumacc.cc:485:replace_alu$6662
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$296: $auto$alumacc.cc:485:replace_alu$6665
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$299: $auto$alumacc.cc:485:replace_alu$6668
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$302: $auto$alumacc.cc:485:replace_alu$6671
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$305: $auto$alumacc.cc:485:replace_alu$6674
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$308: $auto$alumacc.cc:485:replace_alu$6677
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$311: $auto$alumacc.cc:485:replace_alu$6680
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$314: $auto$alumacc.cc:485:replace_alu$6683
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$317: $auto$alumacc.cc:485:replace_alu$6686
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$320: $auto$alumacc.cc:485:replace_alu$6689
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$323: $auto$alumacc.cc:485:replace_alu$6692
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$326: $auto$alumacc.cc:485:replace_alu$6695
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$329: $auto$alumacc.cc:485:replace_alu$6698
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$332: $auto$alumacc.cc:485:replace_alu$6701
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$335: $auto$alumacc.cc:485:replace_alu$6704
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$338: $auto$alumacc.cc:485:replace_alu$6707
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$341: $auto$alumacc.cc:485:replace_alu$6710
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$344: $auto$alumacc.cc:485:replace_alu$6713
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:764$347: $auto$alumacc.cc:485:replace_alu$6716
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:857$351: $auto$alumacc.cc:485:replace_alu$6719
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:863$352: $auto$alumacc.cc:485:replace_alu$6722
  creating $alu cell for $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:945$383: $auto$alumacc.cc:485:replace_alu$6725
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:875$356: $auto$alumacc.cc:485:replace_alu$6730
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:887$362: $auto$alumacc.cc:485:replace_alu$6733
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:919$377: $auto$alumacc.cc:485:replace_alu$6736
  creating $alu cell for $flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1222$430: $auto$alumacc.cc:485:replace_alu$6739
  creating $alu cell for $flatten\cpu.$ge$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:890$367, $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:889$365, $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:962$393: $auto$alumacc.cc:485:replace_alu$6742
  creating $alu cell for $flatten\cpu.$add$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:959$390: $auto$alumacc.cc:485:replace_alu$6757
  creating $alu cell for $flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:960$391, $flatten\cpu.$ge$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:892$371, $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:891$369, $flatten\cpu.$lt$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:963$394, $flatten\cpu.$eq$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:887$361, $flatten\cpu.$ne$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:888$363: $auto$alumacc.cc:485:replace_alu$6760
  created 68 $alu and 0 $macc cells.

13.23. Executing OPT pass (performing simple optimizations).

13.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~5 debug messages>

13.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

13.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~246 debug messages>

13.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

13.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

13.23.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$5922 ($dff) from module processorci_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$5925 ($dff) from module processorci_top.

13.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 19 unused wires.
<suppressed ~2 debug messages>

13.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.23.9. Rerunning OPT passes. (Maybe there is more to do..)

13.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~246 debug messages>

13.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

13.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.23.13. Executing OPT_DFF pass (perform DFF optimizations).

13.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

13.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.23.16. Finished OPT passes. (There is nothing left to do.)

13.24. Executing MEMORY pass.

13.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

13.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

13.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing processorci_top.Controller.Data_Memory.memory write port 0.
  Analyzing processorci_top.Controller.Memory.memory write port 0.
  Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0.
  Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0.
  Analyzing processorci_top.cpu.regfile write port 0.

13.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

13.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\cpu.regfile'[0] in module `\processorci_top': no output FF found.
Checking read port `\cpu.regfile'[1] in module `\processorci_top': no output FF found.
Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\cpu.regfile'[0] in module `\processorci_top': no address FF found.
Checking read port address `\cpu.regfile'[1] in module `\processorci_top': no address FF found.

13.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 2 unused cells and 18 unused wires.
<suppressed ~3 debug messages>

13.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory processorci_top.cpu.regfile by address:

13.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

13.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

13.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

13.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

13.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0]
mapping memory processorci_top.cpu.regfile via $__TRELLIS_DPR16X4_
<suppressed ~1170 debug messages>

13.27. Executing TECHMAP pass (map to technology primitives).

13.27.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/lutrams_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

13.27.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/brams_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

13.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1078 debug messages>

13.28. Executing OPT pass (performing simple optimizations).

13.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1745 debug messages>

13.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~57 debug messages>
Removed a total of 19 cells.

13.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$5655 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding SRST signal on $auto$ff.cc:266:slice$6301 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1515_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$6240 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2274_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]).
Adding SRST signal on $auto$ff.cc:266:slice$6089 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2941_Y, Q = \ResetBootSystem.counter, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$5930 ($sdff) from module processorci_top (D = { \cpu.csr_mcause_next [31] \cpu.csr_mcause_next [4:0] }, Q = { \cpu.csr_mcause_value [31] \cpu.csr_mcause_value [4:0] }).
Adding EN signal on $auto$ff.cc:266:slice$5929 ($sdff) from module processorci_top (D = \cpu.csr_mepc_next [31:2], Q = \cpu.csr_mepc_value [31:2]).
Handling never-active EN on $auto$ff.cc:266:slice$5928 ($sdffe) from module processorci_top (connecting SRST instead).
Handling never-active EN on $auto$ff.cc:266:slice$5926 ($sdffe) from module processorci_top (connecting SRST instead).
Handling never-active EN on $auto$ff.cc:266:slice$5923 ($sdffe) from module processorci_top (connecting SRST instead).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$5923 ($dffe) from module processorci_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$5926 ($dffe) from module processorci_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$5928 ($dffe) from module processorci_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$5933 ($sdff) from module processorci_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$6088 ($sdff) from module processorci_top.
Setting constant 1-bit at position 0 on $flatten\cpu.$procdff$5658 ($dff) from module processorci_top.
Setting constant 1-bit at position 1 on $flatten\cpu.$procdff$5658 ($dff) from module processorci_top.
Setting constant 1-bit at position 2 on $flatten\cpu.$procdff$5658 ($dff) from module processorci_top.
Setting constant 1-bit at position 3 on $flatten\cpu.$procdff$5658 ($dff) from module processorci_top.
Setting constant 1-bit at position 4 on $flatten\cpu.$procdff$5658 ($dff) from module processorci_top.
Setting constant 0-bit at position 0 on $flatten\cpu.$procdff$5660 ($dff) from module processorci_top.

13.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 304 unused cells and 8388 unused wires.
<suppressed ~318 debug messages>

13.28.5. Rerunning OPT passes. (Removed registers in this run.)

13.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~499 debug messages>

13.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

13.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\cpu.$procdff$5661 ($dff) from module processorci_top (D = $flatten\cpu.$sub$/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1222$430_Y, Q = \cpu.pc, rval = 0).
Adding SRST signal on $auto$ff.cc:266:slice$9211 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$6429 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).
Setting constant 1-bit at position 0 on $flatten\cpu.$procdff$5659 ($dff) from module processorci_top.
Setting constant 1-bit at position 1 on $flatten\cpu.$procdff$5659 ($dff) from module processorci_top.
Setting constant 1-bit at position 2 on $flatten\cpu.$procdff$5659 ($dff) from module processorci_top.

13.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 50 unused cells and 93 unused wires.
<suppressed ~61 debug messages>

13.28.10. Rerunning OPT passes. (Removed registers in this run.)

13.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~2 debug messages>

13.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.28.13. Executing OPT_DFF pass (perform DFF optimizations).

13.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

13.28.15. Finished fast OPT passes.

13.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

13.30. Executing OPT pass (performing simple optimizations).

13.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~50 debug messages>

13.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$9209: { $auto$opt_dff.cc:194:make_patterns_logic$9206 $auto$opt_dff.cc:194:make_patterns_logic$6241 $auto$opt_dff.cc:194:make_patterns_logic$6243 $auto$fsm_map.cc:74:implement_pattern_cache$5907 }
    Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1209:
      Old ports: A=12'000000000000, B={ \Controller.Interpreter.memory_page_number [5:0] 6'000000 }, Y=$auto$wreduce.cc:461:run$6393 [11:0]
      New ports: A=6'000000, B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$6393 [11:6]
      New connections: $auto$wreduce.cc:461:run$6393 [5:0] = 6'000000
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$2014:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$6396 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$6396 [2] $auto$wreduce.cc:461:run$6396 [0] }
      New connections: $auto$wreduce.cc:461:run$6396 [1] = $auto$wreduce.cc:461:run$6396 [0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$2019:
      Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$6397 [6:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$6397 [1:0]
      New connections: $auto$wreduce.cc:461:run$6397 [6:2] = { $auto$wreduce.cc:461:run$6397 [1] 3'010 $auto$wreduce.cc:461:run$6397 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$2030:
      Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$6398 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6398 [2]
      New connections: { $auto$wreduce.cc:461:run$6398 [3] $auto$wreduce.cc:461:run$6398 [1:0] } = { $auto$wreduce.cc:461:run$6398 [2] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$2040:
      Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$6400 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6400 [0]
      New connections: $auto$wreduce.cc:461:run$6400 [3:1] = { $auto$wreduce.cc:461:run$6400 [0] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$2054:
      Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$6402 [6:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$6402 [0]
      New connections: $auto$wreduce.cc:461:run$6402 [6:1] = { $auto$wreduce.cc:461:run$6402 [0] 1'0 $auto$wreduce.cc:461:run$6402 [0] 3'011 }
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2449:
      Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$2449_Y
      New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$2449_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2449_Y [7:5] = 3'000
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2574:
      Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2574_Y
      New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2574_Y [23:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2574_Y [31:24] = 8'00000000
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2584: $auto$opt_reduce.cc:137:opt_pmux$5749
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2788:
      Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$6408 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2788_Y
      New ports: A=3'000, B={ $auto$wreduce.cc:461:run$6408 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2788_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2788_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2796:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$6408 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$6408 [2]
      New connections: $auto$wreduce.cc:461:run$6408 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2872:
      Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2872_Y
      New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2872_Y [2:1]
      New connections: { $flatten\Controller.\Uart.$procmux$2872_Y [3] $flatten\Controller.\Uart.$procmux$2872_Y [0] } = 2'00
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1830:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$6421 [0] 1'0 $auto$wreduce.cc:461:run$6422 [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$6424 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$6421 [0] $auto$wreduce.cc:461:run$6422 [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$6424 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1611:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$6424 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6424 [0]
      New connections: $auto$wreduce.cc:461:run$6424 [1] = $auto$wreduce.cc:461:run$6424 [0]
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1967:
      Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$6426 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$6428 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$6426 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$6428 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1554:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$6428 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6428 [0]
      New connections: $auto$wreduce.cc:461:run$6428 [1] = $auto$wreduce.cc:461:run$6428 [0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2952: { $flatten\ResetBootSystem.$procmux$2945_CMP $flatten\ResetBootSystem.$procmux$2944_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2955:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2955_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2955_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2955_Y [0] = 1'0
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2866:
      Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2872_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2866_Y
      New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2872_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2866_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2866_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2961:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2955_Y, Y=$flatten\ResetBootSystem.$procmux$2961_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2955_Y [1], Y=$flatten\ResetBootSystem.$procmux$2961_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2961_Y [0] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 23 changes.

13.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

13.30.6. Executing OPT_DFF pass (perform DFF optimizations).

13.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

13.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~3 debug messages>

13.30.9. Rerunning OPT passes. (Maybe there is more to do..)

13.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~50 debug messages>

13.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

13.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6120 ($sdff) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6164 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6192 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6294 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6294 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6294 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6321 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6321 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6321 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6321 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6321 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6321 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6321 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6321 ($dffe) from module processorci_top.

13.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 22 unused cells and 4 unused wires.
<suppressed ~23 debug messages>

13.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~24 debug messages>

13.30.16. Rerunning OPT passes. (Maybe there is more to do..)

13.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~50 debug messages>

13.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$2024:
      Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2024_Y
      New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$2024_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2024_Y [7:5] = 3'000
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2002:
      Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$6406 [0] 6'000000 $auto$wreduce.cc:461:run$6399 [1:0] 1'0 $auto$wreduce.cc:461:run$6404 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$6403 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$6402 [6] 1'0 $auto$wreduce.cc:461:run$6402 [6] 3'011 $auto$wreduce.cc:461:run$6402 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$6398 [3] 2'00 $auto$wreduce.cc:461:run$6398 [3] 6'000010 $auto$wreduce.cc:461:run$6399 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$6398 [3] $auto$wreduce.cc:461:run$6398 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$2024_Y 1'0 $auto$wreduce.cc:461:run$6397 [6] 3'010 $auto$wreduce.cc:461:run$6397 [2] $auto$wreduce.cc:461:run$6397 [6] $auto$wreduce.cc:461:run$6397 [2] 13'0001001100010 $auto$wreduce.cc:461:run$6396 [2:1] $auto$wreduce.cc:461:run$6396 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$6395 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$2002_Y
      New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$6406 [0] 5'00000 $auto$wreduce.cc:461:run$6399 [1:0] $auto$wreduce.cc:461:run$6404 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$6403 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$6402 [6] 1'0 $auto$wreduce.cc:461:run$6402 [6] 3'011 $auto$wreduce.cc:461:run$6402 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$6398 [3] 2'00 $auto$wreduce.cc:461:run$6398 [3] 5'00010 $auto$wreduce.cc:461:run$6399 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$6398 [3] $auto$wreduce.cc:461:run$6398 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$2024_Y [4:0] $auto$wreduce.cc:461:run$6397 [6] 3'010 $auto$wreduce.cc:461:run$6397 [2] $auto$wreduce.cc:461:run$6397 [6] $auto$wreduce.cc:461:run$6397 [2] 11'00100110010 $auto$wreduce.cc:461:run$6396 [2:1] $auto$wreduce.cc:461:run$6396 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$6395 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$2002_Y [6:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2002_Y [7] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 2 changes.

13.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.30.20. Executing OPT_DFF pass (perform DFF optimizations).

13.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

13.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.30.23. Rerunning OPT passes. (Maybe there is more to do..)

13.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~50 debug messages>

13.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

13.30.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.30.27. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6349 ($sdff) from module processorci_top.

13.30.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

13.30.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

13.30.30. Rerunning OPT passes. (Maybe there is more to do..)

13.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~50 debug messages>

13.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

13.30.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.30.34. Executing OPT_DFF pass (perform DFF optimizations).

13.30.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

13.30.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.30.37. Finished OPT passes. (There is nothing left to do.)

13.31. Executing TECHMAP pass (map to technology primitives).

13.31.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v
Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

13.31.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/arith_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

13.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $lut.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $sdffe.
Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu.
Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu.
Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux.
Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux.
Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux.
Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux.
Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux.
Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $sdff.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $ne.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~3479 debug messages>

13.32. Executing OPT pass (performing simple optimizations).

13.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~9337 debug messages>

13.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~2421 debug messages>
Removed a total of 807 cells.

13.32.3. Executing OPT_DFF pass (perform DFF optimizations).

13.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1021 unused cells and 3630 unused wires.
<suppressed ~1027 debug messages>

13.32.5. Finished fast OPT passes.

13.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

13.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

13.35. Executing TECHMAP pass (map to technology primitives).

13.35.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

13.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
No more expansions possible.
<suppressed ~782 debug messages>

13.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~97 debug messages>

13.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

13.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in processorci_top.

13.39. Executing ATTRMVCP pass (move or copy attributes).

13.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 3735 unused wires.
<suppressed ~1 debug messages>

13.41. Executing TECHMAP pass (map to technology primitives).

13.41.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/latches_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

13.41.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

13.42. Executing ABC9 pass.

13.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

13.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

13.42.3. Executing PROC pass (convert processes to netlists).

13.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$31857'.
Cleaned up 1 empty switch.

13.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$31858 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

13.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

13.42.3.4. Executing PROC_INIT pass (extract init attributes).

13.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

13.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

13.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$31858'.
     1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$31856_EN[3:0]$31864
     2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$31856_DATA[3:0]$31863
     3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$31856_ADDR[3:0]$31862
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$31857'.

13.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

13.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31851_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31846_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31841_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31842_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31843_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31847_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31848_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31852_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31844_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31853_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31840_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31849_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31845_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31854_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31855_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$31850_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$31856_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$31858'.
  created $dff cell `$procdff$31908' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$31856_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$31858'.
  created $dff cell `$procdff$31909' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$31856_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$31858'.
  created $dff cell `$procdff$31910' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$31857'.
  created direct connection (no actual register cell created).

13.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

13.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$31882'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$31858'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$31857'.
Cleaned up 1 empty switch.

13.42.3.12. Executing OPT_EXPR pass (perform const folding).

13.42.4. Executing SCC pass (detecting logic loops).
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$18526 $auto$simplemap.cc:126:simplemap_reduce$18979 $auto$simplemap.cc:38:simplemap_not$25210 $auto$ff.cc:266:slice$18966 $auto$ff.cc:479:convert_ce_over_srst$31029 $auto$simplemap.cc:126:simplemap_reduce$9344 $auto$simplemap.cc:38:simplemap_not$25209 $auto$alumacc.cc:485:replace_alu$6528.slice[0].ccu2c_i $auto$ff.cc:266:slice$18965 $auto$ff.cc:479:convert_ce_over_srst$31027 $auto$ff.cc:266:slice$18970 $auto$ff.cc:479:convert_ce_over_srst$31037 $auto$ff.cc:266:slice$18967 $auto$ff.cc:479:convert_ce_over_srst$31031 $auto$alumacc.cc:485:replace_alu$6528.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$9348 $auto$simplemap.cc:126:simplemap_reduce$9345 $auto$simplemap.cc:38:simplemap_not$25212 $auto$ff.cc:266:slice$18968 $auto$ff.cc:479:convert_ce_over_srst$31033 $auto$simplemap.cc:38:simplemap_not$14317 $auto$alumacc.cc:485:replace_alu$6528.slice[4].ccu2c_i $auto$ff.cc:266:slice$18969 $auto$ff.cc:479:convert_ce_over_srst$31035 $auto$simplemap.cc:126:simplemap_reduce$18484 $auto$simplemap.cc:126:simplemap_reduce$18482 $auto$simplemap.cc:126:simplemap_reduce$18529 $auto$simplemap.cc:126:simplemap_reduce$18527 $auto$simplemap.cc:38:simplemap_not$19059 $auto$simplemap.cc:75:simplemap_bitop$9400 $auto$simplemap.cc:126:simplemap_reduce$9350 $auto$simplemap.cc:126:simplemap_reduce$9346 $auto$simplemap.cc:38:simplemap_not$27688
Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$30745 $auto$ff.cc:266:slice$13440 $auto$ff.cc:266:slice$13442 $auto$simplemap.cc:126:simplemap_reduce$13556 $auto$simplemap.cc:126:simplemap_reduce$13541 $auto$ff.cc:266:slice$13441 $auto$opt_expr.cc:617:replace_const_cells$30829 $auto$simplemap.cc:267:simplemap_mux$25222 $auto$simplemap.cc:126:simplemap_reduce$25229 $auto$simplemap.cc:126:simplemap_reduce$25226 $auto$simplemap.cc:75:simplemap_bitop$25284 $auto$simplemap.cc:267:simplemap_mux$13528 $auto$simplemap.cc:225:simplemap_logbin$13531 $auto$simplemap.cc:196:simplemap_lognot$13546 $auto$simplemap.cc:126:simplemap_reduce$13544 $auto$simplemap.cc:126:simplemap_reduce$13542 $auto$simplemap.cc:126:simplemap_reduce$25179 $auto$simplemap.cc:126:simplemap_reduce$25176 $auto$simplemap.cc:75:simplemap_bitop$25173 $auto$simplemap.cc:196:simplemap_lognot$13561 $auto$simplemap.cc:126:simplemap_reduce$13559 $auto$simplemap.cc:126:simplemap_reduce$13557 $auto$opt_expr.cc:617:replace_const_cells$30831 $auto$ff.cc:266:slice$13443 $auto$simplemap.cc:126:simplemap_reduce$14412 $auto$simplemap.cc:126:simplemap_reduce$14410 $auto$simplemap.cc:225:simplemap_logbin$13487 $auto$simplemap.cc:196:simplemap_lognot$13497 $auto$simplemap.cc:126:simplemap_reduce$13495 $auto$opt_expr.cc:617:replace_const_cells$30833 $auto$simplemap.cc:267:simplemap_mux$25221
Found an SCC: $auto$ff.cc:266:slice$13296 $auto$opt_expr.cc:617:replace_const_cells$30275 $auto$ff.cc:266:slice$13299 $auto$ff.cc:266:slice$13303 $auto$simplemap.cc:126:simplemap_reduce$13424 $auto$simplemap.cc:126:simplemap_reduce$13393 $auto$opt_expr.cc:617:replace_const_cells$30283 $auto$ff.cc:266:slice$13300 $auto$opt_expr.cc:617:replace_const_cells$30287 $auto$ff.cc:266:slice$13297 $auto$opt_expr.cc:617:replace_const_cells$30277 $auto$ff.cc:266:slice$13301 $auto$simplemap.cc:126:simplemap_reduce$13422 $auto$opt_expr.cc:617:replace_const_cells$30271 $auto$simplemap.cc:126:simplemap_reduce$13391 $auto$ff.cc:266:slice$13295 $auto$simplemap.cc:126:simplemap_reduce$13427 $auto$simplemap.cc:126:simplemap_reduce$13423 $auto$simplemap.cc:126:simplemap_reduce$13396 $auto$simplemap.cc:126:simplemap_reduce$13392 $auto$opt_expr.cc:617:replace_const_cells$30273 $auto$ff.cc:266:slice$13298 $auto$simplemap.cc:196:simplemap_lognot$13434 $auto$simplemap.cc:126:simplemap_reduce$13432 $auto$simplemap.cc:126:simplemap_reduce$13430 $auto$simplemap.cc:126:simplemap_reduce$13428 $auto$simplemap.cc:126:simplemap_reduce$13425 $auto$opt_expr.cc:617:replace_const_cells$30279 $auto$simplemap.cc:196:simplemap_lognot$13403 $auto$simplemap.cc:126:simplemap_reduce$13401 $auto$simplemap.cc:126:simplemap_reduce$13399 $auto$simplemap.cc:126:simplemap_reduce$13397 $auto$simplemap.cc:126:simplemap_reduce$13394 $auto$ff.cc:266:slice$13302 $auto$simplemap.cc:167:logic_reduce$9366 $auto$simplemap.cc:225:simplemap_logbin$13375 $auto$simplemap.cc:225:simplemap_logbin$13376
Found an SCC: $auto$ff.cc:266:slice$13452 $auto$opt_expr.cc:617:replace_const_cells$30821 $auto$ff.cc:266:slice$13450 $auto$simplemap.cc:126:simplemap_reduce$13579 $auto$opt_expr.cc:617:replace_const_cells$30819 $auto$ff.cc:266:slice$13451 $auto$ff.cc:266:slice$13445 $auto$simplemap.cc:126:simplemap_reduce$13576 $auto$opt_expr.cc:617:replace_const_cells$30827 $auto$ff.cc:266:slice$13444 $auto$ff.cc:266:slice$13449 $auto$opt_expr.cc:617:replace_const_cells$30825 $auto$ff.cc:266:slice$13447 $auto$simplemap.cc:126:simplemap_reduce$13581 $auto$simplemap.cc:126:simplemap_reduce$13577 $auto$ff.cc:266:slice$13446 $auto$simplemap.cc:126:simplemap_reduce$13584 $auto$simplemap.cc:126:simplemap_reduce$13582 $auto$simplemap.cc:126:simplemap_reduce$13578 $auto$opt_expr.cc:617:replace_const_cells$30823 $auto$ff.cc:266:slice$13448 $auto$simplemap.cc:126:simplemap_reduce$14406 $auto$simplemap.cc:196:simplemap_lognot$13588 $auto$simplemap.cc:126:simplemap_reduce$13586
Found 4 SCCs in module processorci_top.
Found 4 SCCs.

13.42.5. Executing ABC9_OPS pass (helper functions for ABC9).

13.42.6. Executing PROC pass (convert processes to netlists).

13.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

13.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

13.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

13.42.6.4. Executing PROC_INIT pass (extract init attributes).

13.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

13.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

13.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

13.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

13.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).

13.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

13.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

13.42.6.12. Executing OPT_EXPR pass (perform const folding).

13.42.7. Executing TECHMAP pass (map to technology primitives).

13.42.7.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v
Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

13.42.7.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~162 debug messages>

13.42.8. Executing OPT pass (performing simple optimizations).

13.42.8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.

13.42.8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

13.42.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

13.42.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Performed a total of 0 changes.

13.42.8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

13.42.8.6. Executing OPT_DFF pass (perform DFF optimizations).

13.42.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..

13.42.8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.

13.42.8.9. Finished OPT passes. (There is nothing left to do.)

13.42.9. Executing TECHMAP pass (map to technology primitives).

13.42.9.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_map.v
Parsing Verilog input from `/usr/local/share/synlig/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

13.42.9.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1041 debug messages>

13.42.10. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_model.v
Parsing Verilog input from `/usr/local/share/synlig/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

13.42.11. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

13.42.12. Executing ABC9_OPS pass (helper functions for ABC9).

13.42.13. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

13.42.14. Executing TECHMAP pass (map to technology primitives).

13.42.14.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v
Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

13.42.14.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~201 debug messages>

13.42.15. Executing OPT pass (performing simple optimizations).

13.42.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~18 debug messages>

13.42.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

13.42.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

13.42.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

13.42.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.42.15.6. Executing OPT_DFF pass (perform DFF optimizations).

13.42.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

13.42.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.42.15.9. Rerunning OPT passes. (Maybe there is more to do..)

13.42.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

13.42.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

13.42.15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

13.42.15.13. Executing OPT_DFF pass (perform DFF optimizations).

13.42.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

13.42.15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

13.42.15.16. Finished OPT passes. (There is nothing left to do.)

13.42.16. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

13.42.17. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 5877 cells with 38658 new cells, skipped 3745 cells.
  replaced 3 cell types:
     827 $_OR_
     112 $_XOR_
    4938 $_MUX_
  not replaced 8 cell types:
      12 $scopeinfo
     243 $_NOT_
     572 $_AND_
     667 TRELLIS_FF
     174 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
    1038 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
    1038 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
       1 $__ABC9_SCC_BREAKER

13.42.17.1. Executing ABC9_OPS pass (helper functions for ABC9).

13.42.17.2. Executing ABC9_OPS pass (helper functions for ABC9).

13.42.17.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 16549 AND gates and 49718 wires from module `processorci_top' to a netlist network with 4830 inputs and 936 outputs.

13.42.17.4. Executing ABC9_EXE pass (technology mapping using ABC9).

13.42.17.5. Executing ABC9.
Running ABC command: "built in abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   4830/    936  and =   15587  lev =   21 (0.98)  mem = 0.49 MB  box = 1212  bb = 1038
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   4830/    936  and =   19187  lev =   17 (0.95)  mem = 0.53 MB  ch = 1728  box = 1212  bb = 1038
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   64. Obj =  148. Set =  672. CutMin = no
ABC: Node =   19187.  Ch =  1165.  Total mem =    6.18 MB. Peak cut mem =    0.11 MB.
ABC: P:  Del = 3965.00.  Ar =   19777.0.  Edge =    22675.  Cut =   169955.  T =     0.08 sec
ABC: P:  Del = 3965.00.  Ar =   19772.0.  Edge =    22598.  Cut =   169662.  T =     0.08 sec
ABC: P:  Del = 3965.00.  Ar =    7297.0.  Edge =    15861.  Cut =   580045.  T =     0.25 sec
ABC: F:  Del = 3962.00.  Ar =    5598.0.  Edge =    15563.  Cut =   248154.  T =     0.11 sec
ABC: A:  Del = 3962.00.  Ar =    5394.0.  Edge =    15156.  Cut =   234551.  T =     0.16 sec
ABC: A:  Del = 3962.00.  Ar =    5350.0.  Edge =    15112.  Cut =   242048.  T =     0.16 sec
ABC: Total time =     0.84 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   4830/    936  and =   11825  lev =   20 (0.97)  mem = 0.45 MB  box = 1212  bb = 1038
ABC: Mapping (K=7)  :  lut =   3855  edge =   15084  lev =    8 (0.62)  Boxes are not in a topological order. Switching to level computation without boxes.
ABC: levB =   20  mem = 0.21 MB
ABC: LUT = 3855 : 2=506 13.1 %  3=371 9.6 %  4=2173 56.4 %  5=649 16.8 %  6=70 1.8 %  7=86 2.2 %  Ave = 3.91
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 6.97 seconds, total: 6.97 seconds

13.42.17.6. Executing AIGER frontend.
<suppressed ~11544 debug messages>
Removed 15202 unused cells and 40157 unused wires.

13.42.17.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     3865
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      174
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1038
ABC RESULTS:           input signals:     1098
ABC RESULTS:          output signals:      185
Removing temp directory.

13.42.18. Executing TECHMAP pass (map to technology primitives).

13.42.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_unmap.v
Parsing Verilog input from `/usr/local/share/synlig/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

13.42.18.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000110 for cells of type $__ABC9_SCC_BREAKER.
No more expansions possible.
<suppressed ~2270 debug messages>
Removed 284 unused cells and 64862 unused wires.

13.43. Executing TECHMAP pass (map to technology primitives).

13.43.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

13.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$0aae27145afd1348566af63c85046495acb0e0d8\$lut for cells of type $lut.
Using template $paramod$e96357bcccc12feb7d7c9440a8ab8eb843c3a2d0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$8285f8849e040d5e63ae8e647a5a5d3dc47fa58c\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$ce15874c299a587dd16825ec2d2d2759b547554e\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$6e4a86e6f1a5dc8f826898a131e83cdba4a4fc9e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$7ca4db46d3cd57dbe2541a389808e6d33af02319\$lut for cells of type $lut.
Using template $paramod$d909494d67d7075f17a422f7cb5526f6d6564ea6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod$983adbc56c7400f95b406f02e82bd0da8b98fd00\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$0a4d85497e20c50068555dd5ad9ad3a7952cab73\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut.
Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut.
Using template $paramod$3c5eb16fa418cfbbe1710d24d17e7d0b5448c3c1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$8c14e6d85060218e346675600ae1194fdf5a803e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$b1eb37a8da55eebd94e79ec6bd1998d832a45f0a\$lut for cells of type $lut.
Using template $paramod$25ee0a22257eb7d0412f2c01bf38b7b3e778f214\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$1bff0b0820f100a92ddd1519c6f1bfefea71d360\$lut for cells of type $lut.
Using template $paramod$09e1da88b3c98bd7bb79c46c015150df2adcb20c\$lut for cells of type $lut.
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut.
Using template $paramod$1ea42a34184b78f4245e12c43d015f13aa00ec29\$lut for cells of type $lut.
Using template $paramod$bd00b9312f50e463dbb076ec1e8c49f1fd6f25bc\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$d4c377cd18232ff8b0f1b77e3edb2a4e4be3300b\$lut for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut.
Using template $paramod$2fd3c42461376c704c07117e7368b2ed8179d1e0\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$9de80d92e8cc66d364ef31ee1a69cde5cb2d00d8\$lut for cells of type $lut.
Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut.
Using template $paramod$c441dbd41fa7b52ce609b1fb3e8a706905598601\$lut for cells of type $lut.
Using template $paramod$d8a6058f97335646f000496287ca88987ac437c1\$lut for cells of type $lut.
Using template $paramod$505aa48b0a2b03f0940e895e3506bc51003d82d3\$lut for cells of type $lut.
Using template $paramod$51da077e4bf37b6b4b0961a4797af73831856ba1\$lut for cells of type $lut.
Using template $paramod$1e2eea4af445cbfb1544b5246bff77719d26cd69\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$86fabc282b33a875087c403b2dbc7c28de74ecb8\$lut for cells of type $lut.
Using template $paramod$bdddf4a24964e2e96968085b76d17d67519d6d9c\$lut for cells of type $lut.
Using template $paramod$ecb83b3ee175d0b56cdac6c6fa19a7c550767e64\$lut for cells of type $lut.
Using template $paramod$542e2fdf39f66ee0d9684372297ec1f9c72087d5\$lut for cells of type $lut.
Using template $paramod$98e1d11683c0a22e595b32649124489a2d73a644\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$e0e16f0e69ba9e6596b61d072bd230c598f46f32\$lut for cells of type $lut.
Using template $paramod$b51a34d9025f179ac3b0198c8334e4840dd632a0\$lut for cells of type $lut.
Using template $paramod$2f23ee9496edbb044d48f324aa9a472e448048c6\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$13b3436639770e0cb561c14fb7d7938f483d4456\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut.
Using template $paramod$903b13a78e0201d81ee2cb5e579e213337de2eac\$lut for cells of type $lut.
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$b089060a61c5d29ddce66d73edb5ee493ec9de27\$lut for cells of type $lut.
Using template $paramod$edb78bf6097bd1610bf429917d83de43c0242af1\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$12e9049d8709286a770fe60b59ec4d94c39ce3c9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$f55f4b90ec8e3e648d5c29eab1fa5ddd64b3f973\$lut for cells of type $lut.
Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$9cf044275e70b6dc34d2f815a6f8ffc23f9694a0\$lut for cells of type $lut.
Using template $paramod$c56d1c20dec1034d0c3d987223d8125f681c6f54\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$aeb27cd9efe624def2282ecf09671da132bf31e8\$lut for cells of type $lut.
Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut.
Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9\$lut for cells of type $lut.
Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut.
Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$343c340914da1bc1b087d2ab3971dc221716ccb1\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$6c51c1ba6c39f0c09b896d52432b366f116bd3c1\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut.
Using template $paramod$b5155ccbba5fc82cb953259e05148880324a134d\$lut for cells of type $lut.
Using template $paramod$f7cbd8f5974233f70d25c33ef6a692898e4f6377\$lut for cells of type $lut.
Using template $paramod$a648edd7290dbdc60b4277769ac1653dae6fd74c\$lut for cells of type $lut.
Using template $paramod$9851cb11f88bbbf4a516c0595f3b0113b1f100c4\$lut for cells of type $lut.
Using template $paramod$af6bfc66edfa832be553173935a94fd15de7c168\$lut for cells of type $lut.
Using template $paramod$130af793a2ec6ecceb3e0ef509cf6b180e856b6f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$17fa8a939b0f8314dda6bb78f4f778f4e2f790ea\$lut for cells of type $lut.
Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut.
Using template $paramod$e0286d7bdebdb6346cb367bb1962e01892ba2e32\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod$71ee25e9c5d051763351c9d480fc189154f82403\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut.
Using template $paramod$9beb8ded65337efae33440136749662bd930ae79\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$d80c9b99dacb354fa564a6fcc23ca30753bf6623\$lut for cells of type $lut.
Using template $paramod$4978360fe53bdcf6193c85aac631cf6592e5a5ce\$lut for cells of type $lut.
Using template $paramod$5afe21d6fdc7c33aeb338fdb508ea02813207bfd\$lut for cells of type $lut.
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut.
Using template $paramod$5c6d01824df27a97c3776b3694e8814e23c197cd\$lut for cells of type $lut.
Using template $paramod$454817d44aced61c7102ee154821f5e0ef7afb56\$lut for cells of type $lut.
Using template $paramod$74c0f3179b5cebe485563ea55e9b637e7ee5c0c3\$lut for cells of type $lut.
Using template $paramod$9efa450cf4ff54645fb0c2bdc008d4e3bfcced0e\$lut for cells of type $lut.
Using template $paramod$ce1c9e5dc69130ad725a1305c625edfc80c5b8a9\$lut for cells of type $lut.
Using template $paramod$7e2a54848bdfd3a79f4ef5ed39bdd60d6c085df9\$lut for cells of type $lut.
Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$5f69790c19b5e35c1c6c7354854d5628ca59cfcc\$lut for cells of type $lut.
Using template $paramod$46337428ce420685467716f9921402709a730c9d\$lut for cells of type $lut.
Using template $paramod$7c085cdbf0919cd3ad402d9495d97f0d71e4db93\$lut for cells of type $lut.
Using template $paramod$11c86b7a6cb6e98dcfb16c5f4d4cc1052b93d8a4\$lut for cells of type $lut.
Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut.
Using template $paramod$648d5b3c4c08a2b5e6752f60f9134dd7da5b02b9\$lut for cells of type $lut.
Using template $paramod$fce992df4978ad69e56d150579aa6ba47bc13a78\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut.
Using template $paramod$f8e1bdecd38a1f2a88371fc52b96bff86506a2c7\$lut for cells of type $lut.
Using template $paramod$e459aea4cf4dc2824e78edc2d14a92ea420144ff\$lut for cells of type $lut.
Using template $paramod$1d8da67e55226ee6f849b82c7c3ba5690a649089\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$d4352b9972e10fd529b42d1ec77ff0fe6dbbb640\$lut for cells of type $lut.
Using template $paramod$078a725d7245a429d31c2ec95904a26c239ee717\$lut for cells of type $lut.
Using template $paramod$839224a4a2957506d52e9b18f895e38fe46d3a48\$lut for cells of type $lut.
Using template $paramod$52a4ebcc5e3fff1e7a0d8c68626d4cc0adc4c53f\$lut for cells of type $lut.
Using template $paramod$4667cec65cfa6b20c0b9ee9dc457b7f9882c9380\$lut for cells of type $lut.
Using template $paramod$36e77cf68e95b3b8cccf1bb5b64409630f2c88d1\$lut for cells of type $lut.
Using template $paramod$5b17484c2590736ad70267419f134a32681b2631\$lut for cells of type $lut.
Using template $paramod$44c0fe996e6f3f4ba8bae2e194245aa82c30fa47\$lut for cells of type $lut.
Using template $paramod$e2372f20dfa8b54b21637ffb5cbd5a4f43a05e34\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$fb4ed309581bcd972f41afa8566ae8b9812c7f6c\$lut for cells of type $lut.
Using template $paramod$e91b01f9349714d55057bc22c604be26aa38a50d\$lut for cells of type $lut.
Using template $paramod$e524b19ac792ea41fadc9313560a5edc62c1b6c2\$lut for cells of type $lut.
Using template $paramod$1ad9ca75a5e52e69f39f16c0b8ffb14773a0b7f2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$b26fbfdb68e98cf016d61a8611b449e9f4a30f3c\$lut for cells of type $lut.
Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut.
Using template $paramod$46d981b5eabc08c1691f743d7a017e4435316de4\$lut for cells of type $lut.
Using template $paramod$3039c7f41767c4672f4e3f22ad78f16d42720fbf\$lut for cells of type $lut.
Using template $paramod$8cac5452d526045503c5864c3a1dac0121c7053e\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$77268019239d7d46332da9cb6aa01cbf3ba29ee3\$lut for cells of type $lut.
Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut.
Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut.
Using template $paramod$82ed25b11a6a11eb861f4dd3d46f5fc9aa1eebaf\$lut for cells of type $lut.
Using template $paramod$8c13ad014d500c3a349fa680995aa7f6f9eaaf87\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut.
Using template $paramod$c9dfa790606eacc6d63ef9d6a678491503ba2472\$lut for cells of type $lut.
Using template $paramod$1e9d7896e1dd3d2af9633eefc9c29afb478cef41\$lut for cells of type $lut.
Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut.
Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut.
Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut.
Using template $paramod$baf2a67c5497343d1e1817f7f8ec5c5ad7729886\$lut for cells of type $lut.
Using template $paramod$5979463fa46217f1a0e7d4ad32b6027073222314\$lut for cells of type $lut.
Using template $paramod$2bd75d8029426ce76ee7c14a23725daf1a2274fc\$lut for cells of type $lut.
Using template $paramod$c593ce43158c39bf45b040e3d3a4bf18087d62dd\$lut for cells of type $lut.
Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut.
Using template $paramod$96fd7fc3f7e393c78154d3a6e62b8a680078a178\$lut for cells of type $lut.
Using template $paramod$9f60b19e935c0a173907f1e58262a84ee5c51c6f\$lut for cells of type $lut.
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut.
Using template $paramod$2db09828103b88d8ba5b1dd7a95383b77780c50e\$lut for cells of type $lut.
Using template $paramod$39fea1c845fe0f56a461ac64484e7bbd858aff3b\$lut for cells of type $lut.
Using template $paramod$1e66e926164e6462a8179be1078ea3b9daa3e399\$lut for cells of type $lut.
Using template $paramod$50ec6039d9de561a6d0a8dc470847f22a306b04f\$lut for cells of type $lut.
Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut.
Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut.
Using template $paramod$ab4188c7524eec831e9177bc675d62b21a3ccd8b\$lut for cells of type $lut.
Using template $paramod$4e09fb85ad5980549134c5674f63e37de31e60bc\$lut for cells of type $lut.
Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26\$lut for cells of type $lut.
Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut.
Using template $paramod$0d1bcdf20f80f8baee4bf503a0f8a7acf7ff86b6\$lut for cells of type $lut.
Using template $paramod$c78b28b0674e1f0605658e28384d11f25f372de7\$lut for cells of type $lut.
Using template $paramod$6312bf9d0ee12f510d2140f7420a2fcb82e2b92f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut.
Using template $paramod$b637cf4714c2e93484bb499728e176a6ab69c910\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$f9b715fbf1040e81e900b2461c2390d17ed5e988\$lut for cells of type $lut.
Using template $paramod$34536926332939882b8ff52380fffc08ed1f405f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut.
Using template $paramod$01d6171b877f7655dc0d32e32900a6a207a75b44\$lut for cells of type $lut.
Using template $paramod$191860d093976742c784e7b27f9ce3c93c9867c5\$lut for cells of type $lut.
Using template $paramod$3ea1653073c31f2ca4b26ae811cefd3adaf51c2c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$9664b2f5fd61944d7798b30cde43b99ccda87303\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~7385 debug messages>

13.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in processorci_top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110823.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$21213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$21098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$20911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$20796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$20574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$20459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$19656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$18898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$18697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$18241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$17689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$17574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$17322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$17240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$16992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$16222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$15646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$15646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$15631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$15631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$15065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$15044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$12905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$12688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$12353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$12238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10505.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10505.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10505.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10251.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$auto$opt_dff.cc:219:make_patterns_logic$6096.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10505.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$10857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$10857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$10867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$11403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$11481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$11653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$11686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$11923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$12175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$12276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$12287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$12337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$12358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$12368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$12510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$12611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$12622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$12672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$12693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$12703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$12943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$12954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$12961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$12988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$13004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13009.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$13025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$13207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$13288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$13332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$13393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$13414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$13652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$13713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$13734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$13851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$13952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$13963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$13970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$13997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$14013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$14034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14207.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$14281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$14342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$14363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$14652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$14713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$14734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14893.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$14967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$14978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$14985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$14992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$15028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15033.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$15049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$15059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$15248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15335.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15635.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$15911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$15940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$15988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16124.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$16176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$16530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$16757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$16848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$16915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$16976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16981.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$16992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$17007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$17256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$17337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$17623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$17704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$17860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$17971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$18037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18341.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18512.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$18553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$18620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$18631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$18681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$18702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$18712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18887.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$18970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$18977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$19060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$19169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$19421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19505.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$19512.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$19579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$19590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$19640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$19661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$19671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19745.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$19905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$20123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$20497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$20508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$20558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$20579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$20589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$20733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$20834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$20845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$20895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$20916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$20926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$20991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$20995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$21060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$21136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$21147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$21197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$110728$lut$aiger110727$21218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$110728$lut$aiger110727$21218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$21228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$21234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$9525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$9651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$9669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$10924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$9810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$9912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$9975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$9725.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$auto$opt_dff.cc:219:make_patterns_logic$6175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$110728$lut$aiger110727$11953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$19969.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$aiger110727$11216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$110728$lut$auto$fsm_map.cc:170:map_fsm$5853[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110905.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110745.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110743.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110763.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110921.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110786.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110805.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110831.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110842.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110872.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110865.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110879.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110893.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110895.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110897.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110971.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110939.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$110906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$111004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$111004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 12062 unused wires.

13.45. Executing AUTONAME pass.
Renamed 268213 objects in module processorci_top (160 iterations).
<suppressed ~14158 debug messages>

13.46. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `processorci_top'. Setting top module to processorci_top.

13.46.1. Analyzing design hierarchy..
Top module:  \processorci_top

13.46.2. Analyzing design hierarchy..
Top module:  \processorci_top
Removed 0 unused modules.

13.47. Printing statistics.

=== processorci_top ===

   Number of wires:               7171
   Number of wire bits:          38495
   Number of public wires:        7171
   Number of public wire bits:   38495
   Number of ports:                 10
   Number of port bits:             10
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               8681
     $scopeinfo                     12
     CCU2C                         174
     L6MUX21                       328
     LUT4                         5329
     PFUMX                        1133
     TRELLIS_DPR16X4              1038
     TRELLIS_FF                    667

13.48. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Found and reported 0 problems.

13.49. Executing JSON backend.

Warnings: 82 unique messages, 235 total
End of script. Logfile hash: 5200f775b1, CPU: user 46.71s system 0.23s, MEM: 231.96 MB peak
Time spent: 15% 33x opt_clean (7 sec), 14% 1x abc9_exe (7 sec), ...
/eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \
	--lpf /eda/processor_ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \
	--speed 6 --lpf-allow-unconstrained  --ignore-loops
/eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config  --bit colorlight_i9.bit

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] dir
Running in /var/jenkins_home/workspace/nerv/nerv
[Pipeline] {
[Pipeline] echo
Flashing FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p nerv -b colorlight_i9 -l
Final configuration file generated at /var/jenkins_home/workspace/nerv/nerv/build_digilent_arty_a7_100t.tcl
Makefile executed successfully.
Makefile output:
Building the Design...
/eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/nerv/nerv/build_digilent_arty_a7_100t.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096"

****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source /var/jenkins_home/workspace/nerv/nerv/build_digilent_arty_a7_100t.tcl
# read_verilog -sv /var/jenkins_home/workspace/nerv/nerv/nerv.sv
read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1305.145 ; gain = 0.023 ; free physical = 1291 ; free virtual = 24573
# read_verilog /eda/processor_ci/rtl/nerv.v
# read_verilog /eda/processor-ci-controller/modules/uart.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
# read_verilog /eda/processor-ci-controller/src/fifo.v
# read_verilog /eda/processor-ci-controller/src/reset.v
# read_verilog /eda/processor-ci-controller/src/clk_divider.v
# read_verilog /eda/processor-ci-controller/src/memory.v
# read_verilog /eda/processor-ci-controller/src/interpreter.v
# read_verilog /eda/processor-ci-controller/src/controller.v
# set ID [lindex $argv 0]
# set CLOCK_FREQ [lindex $argv 1]
# set MEMORY_SIZE [lindex $argv 2]
# set HIGH_CLK 1
# read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
# set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
# synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE \
#     -verilog_define $HIGH_CLK
Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096 -verilog_define 1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 3779070
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2031.812 ; gain = 404.629 ; free physical = 184 ; free virtual = 23477
---------------------------------------------------------------------------------
WARNING: [Synth 8-6901] identifier 'irq_num' is used before its declaration [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:565]
WARNING: [Synth 8-6901] identifier 'csr_hpm_event_sel' is used before its declaration [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:612]
WARNING: [Synth 8-6901] identifier 'csr_hpm_counter_sel' is used before its declaration [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:613]
WARNING: [Synth 8-6901] identifier 'csr_hpm_counterh_sel' is used before its declaration [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:614]
WARNING: [Synth 8-6901] identifier 'mem_rdata' is used before its declaration [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1052]
CRITICAL WARNING: [Synth 8-9339] data object 'reset_o' is already declared [/eda/processor_ci/rtl/nerv.v:150]
INFO: [Synth 8-6826] previous declaration of 'reset_o' is from here [/eda/processor_ci/rtl/nerv.v:29]
CRITICAL WARNING: [Synth 8-11152] second declaration of 'reset_o' is ignored [/eda/processor_ci/rtl/nerv.v:150]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16]
WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15]
WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16]
WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17]
WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84]
WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85]
INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/nerv.v:1]
INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
	Parameter BUFFER_SIZE bound to: 8 - type: integer 
	Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer 
	Parameter BUS_WIDTH bound to: 32 - type: integer 
	Parameter WORD_SIZE_BY bound to: 4 - type: integer 
	Parameter ID bound to: 0 - type: integer 
	Parameter RESET_CLK_CYCLES bound to: 20 - type: integer 
	Parameter MEMORY_FILE bound to: (null) - type: string 
	Parameter MEMORY_SIZE bound to: 4096 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1]
	Parameter COUNTER_BITS bound to: 32 - type: integer 
	Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1]
INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer 
	Parameter BUS_WIDTH bound to: 32 - type: integer 
	Parameter ID bound to: 0 - type: integer 
	Parameter RESET_CLK_CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
	Parameter BUFFER_SIZE bound to: 8 - type: integer 
	Parameter WORD_SIZE_BY bound to: 4 - type: integer 
INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213]
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1]
	Parameter DEPTH bound to: 8 - type: integer 
	Parameter WIDTH bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 50000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 50000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1]
	Parameter MEMORY_FILE bound to: (null) - type: string 
	Parameter MEMORY_SIZE bound to: 4096 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1]
WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1]
INFO: [Synth 8-6157] synthesizing module 'nerv' [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:298]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:684]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:717]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:927]
INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:1103]
INFO: [Synth 8-6155] done synthesizing module 'nerv' (0#1) [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:298]
WARNING: [Synth 8-7071] port 'irq' of module 'nerv' is unconnected for instance 'cpu' [/eda/processor_ci/rtl/nerv.v:96]
WARNING: [Synth 8-7023] instance 'cpu' of module 'nerv' has 12 connections declared, but only 11 given [/eda/processor_ci/rtl/nerv.v:96]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1]
	Parameter CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/nerv.v:154]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/nerv.v:154]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/nerv.v:154]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/nerv.v:1]
WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25]
WARNING: [Synth 8-6014] Unused sequential element imem_addr_q_reg was removed.  [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:436]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/nerv.v:21]
WARNING: [Synth 8-3848] Net core_read_data in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/nerv.v:32]
WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2144.781 ; gain = 517.598 ; free physical = 169 ; free virtual = 23257
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2159.625 ; gain = 532.441 ; free physical = 166 ; free virtual = 23254
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2159.625 ; gain = 532.441 ; free physical = 166 ; free virtual = 23254
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2159.625 ; gain = 0.000 ; free physical = 145 ; free virtual = 23234
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2286.375 ; gain = 0.000 ; free physical = 160 ; free virtual = 23236
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2286.410 ; gain = 0.000 ; free physical = 153 ; free virtual = 23229
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 163 ; free virtual = 23114
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 163 ; free virtual = 23114
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 163 ; free virtual = 23113
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_RECV |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_SEND |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              000 |                             0000
                    READ |                              001 |                             0001
        COPY_READ_BUFFER |                              010 |                             0100
                      WB |                              011 |                             0010
                  FINISH |                              100 |                             0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              000 |                             0000
       COPY_WRITE_BUFFER |                              001 |                             0100
                   WRITE |                              010 |                             0001
                      WB |                              011 |                             0010
                  FINISH |                              100 |                             0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  iSTATE |                             0001 |                               00
                 iSTATE0 |                             0010 |                               01
                 iSTATE1 |                             0100 |                               10
                 iSTATE2 |                             1000 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
           RESET_COUNTER |                               00 |                               01
                    IDLE |                               01 |                               10
                    INIT |                               10 |                               00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 170 ; free virtual = 23106
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input   64 Bit       Adders := 34    
	   3 Input   32 Bit       Adders := 1     
	   2 Input   32 Bit       Adders := 15    
	   2 Input   24 Bit       Adders := 2     
	   2 Input   10 Bit       Adders := 2     
	   2 Input    8 Bit       Adders := 1     
	   2 Input    6 Bit       Adders := 4     
	   2 Input    5 Bit       Adders := 1     
	   2 Input    4 Bit       Adders := 2     
	   2 Input    3 Bit       Adders := 2     
+---XORs : 
	   2 Input     32 Bit         XORs := 2     
+---Registers : 
	             1024 Bit    Registers := 3     
	               64 Bit    Registers := 2     
	               32 Bit    Registers := 24    
	               24 Bit    Registers := 5     
	               10 Bit    Registers := 2     
	                8 Bit    Registers := 11    
	                6 Bit    Registers := 1     
	                5 Bit    Registers := 2     
	                4 Bit    Registers := 2     
	                3 Bit    Registers := 2     
	                1 Bit    Registers := 31    
+---RAMs : 
	              32K Bit	(1024 X 32 bit)          RAMs := 2     
	               64 Bit	(8 X 8 bit)          RAMs := 2     
+---Muxes : 
	   4 Input   64 Bit        Muxes := 1     
	   2 Input   64 Bit        Muxes := 1     
	  48 Input   64 Bit        Muxes := 2     
	   2 Input   32 Bit        Muxes := 205   
	   5 Input   32 Bit        Muxes := 10    
	   6 Input   32 Bit        Muxes := 1     
	   4 Input   32 Bit        Muxes := 61    
	  11 Input   32 Bit        Muxes := 6     
	   3 Input   32 Bit        Muxes := 2     
	  10 Input   32 Bit        Muxes := 1     
	   2 Input   30 Bit        Muxes := 2     
	  48 Input   24 Bit        Muxes := 1     
	   4 Input    8 Bit        Muxes := 1     
	  48 Input    8 Bit        Muxes := 2     
	   2 Input    8 Bit        Muxes := 4     
	   2 Input    7 Bit        Muxes := 3     
	  24 Input    7 Bit        Muxes := 1     
	   2 Input    6 Bit        Muxes := 4     
	   3 Input    6 Bit        Muxes := 1     
	   2 Input    5 Bit        Muxes := 5     
	   2 Input    4 Bit        Muxes := 6     
	   4 Input    4 Bit        Muxes := 1     
	   2 Input    3 Bit        Muxes := 4     
	   4 Input    3 Bit        Muxes := 1     
	  11 Input    3 Bit        Muxes := 1     
	   5 Input    3 Bit        Muxes := 4     
	   5 Input    2 Bit        Muxes := 4     
	   2 Input    2 Bit        Muxes := 16    
	  48 Input    2 Bit        Muxes := 1     
	   4 Input    2 Bit        Muxes := 4     
	   3 Input    2 Bit        Muxes := 1     
	 109 Input    1 Bit        Muxes := 1     
	   2 Input    1 Bit        Muxes := 61    
	  11 Input    1 Bit        Muxes := 5     
	  10 Input    1 Bit        Muxes := 2     
	   3 Input    1 Bit        Muxes := 6     
	   8 Input    1 Bit        Muxes := 1     
	   6 Input    1 Bit        Muxes := 1     
	  48 Input    1 Bit        Muxes := 22    
	   4 Input    1 Bit        Muxes := 3     
	   5 Input    1 Bit        Muxes := 11    
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-3936] Found unconnected internal register 'mem_rd_func_q_reg' and it is trimmed from '5' to '3' bits. [/var/jenkins_home/workspace/nerv/nerv/nerv.sv:413]
WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:38 ; elapsed = 00:01:40 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 186 ; free virtual = 23085
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object          | Depth x Width | Implemented As | 
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1         | LUT            | 
|Interpreter | memory_mux_selector | 256x1         | LUT            | 
+------------+---------------------+---------------+----------------+


Distributed RAM: Preliminary Mapping Report (see note below)
+----------------+------------------------------------+-----------+----------------------+------------------+
|Module Name     | RTL Object                         | Inference | Size (Depth x Width) | Primitives       | 
+----------------+------------------------------------+-----------+----------------------+------------------+
|processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|processorci_top | Controller/Memory/memory_reg       | Implied   | 1 K x 32             | RAM256X1S x 128  | 
|processorci_top | Controller/Data_Memory/memory_reg  | Implied   | 1 K x 32             | RAM256X1S x 128  | 
+----------------+------------------------------------+-----------+----------------------+------------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:50 ; elapsed = 00:01:52 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 174 ; free virtual = 23073
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:02:00 ; elapsed = 00:02:02 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 175 ; free virtual = 23074
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping Report
+----------------+------------------------------------+-----------+----------------------+------------------+
|Module Name     | RTL Object                         | Inference | Size (Depth x Width) | Primitives       | 
+----------------+------------------------------------+-----------+----------------------+------------------+
|processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|processorci_top | Controller/Memory/memory_reg       | Implied   | 1 K x 32             | RAM256X1S x 128  | 
|processorci_top | Controller/Data_Memory/memory_reg  | Implied   | 1 K x 32             | RAM256X1S x 128  | 
+----------------+------------------------------------+-----------+----------------------+------------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:02:02 ; elapsed = 00:02:04 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 177 ; free virtual = 23076
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:02:12 ; elapsed = 00:02:14 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 183 ; free virtual = 23082
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:02:12 ; elapsed = 00:02:14 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 183 ; free virtual = 23082
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:13 ; elapsed = 00:02:15 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 183 ; free virtual = 23082
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:02:13 ; elapsed = 00:02:15 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 183 ; free virtual = 23082
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:02:13 ; elapsed = 00:02:15 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 183 ; free virtual = 23082
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:02:13 ; elapsed = 00:02:15 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 183 ; free virtual = 23082
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+----------+------+
|      |Cell      |Count |
+------+----------+------+
|1     |BUFG      |     1|
|2     |CARRY4    |    65|
|3     |LUT1      |    34|
|4     |LUT2      |   194|
|5     |LUT3      |   230|
|6     |LUT4      |   100|
|7     |LUT5      |    96|
|8     |LUT6      |   277|
|9     |MUXF7     |     4|
|10    |RAM256X1S |   256|
|11    |RAM32M    |     2|
|12    |RAM32X1D  |     4|
|13    |FDRE      |   606|
|14    |FDSE      |     5|
|15    |IBUF      |     2|
|16    |OBUF      |     2|
|17    |OBUFT     |     1|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:02:13 ; elapsed = 00:02:15 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 183 ; free virtual = 23082
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 3 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:02:06 ; elapsed = 00:02:08 . Memory (MB): peak = 2286.410 ; gain = 532.441 ; free physical = 183 ; free virtual = 23082
Synthesis Optimization Complete : Time (s): cpu = 00:02:13 ; elapsed = 00:02:15 . Memory (MB): peak = 2286.410 ; gain = 659.227 ; free physical = 183 ; free virtual = 23082
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2286.410 ; gain = 0.000 ; free physical = 473 ; free virtual = 23373
INFO: [Netlist 29-17] Analyzing 331 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2350.406 ; gain = 0.000 ; free physical = 478 ; free virtual = 23377
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 262 instances were transformed.
  RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances

Synth Design complete | Checksum: d8165ac0
INFO: [Common 17-83] Releasing license: Synthesis
55 Infos, 62 Warnings, 4 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:02:31 ; elapsed = 00:02:28 . Memory (MB): peak = 2350.441 ; gain = 1045.297 ; free physical = 477 ; free virtual = 23376
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2084.003; main = 1788.003; forked = 438.001
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3239.699; main = 2350.410; forked = 985.336
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2414.438 ; gain = 63.996 ; free physical = 472 ; free virtual = 23371

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 21a0f254f

Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2530.250 ; gain = 115.812 ; free physical = 451 ; free virtual = 23350

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 21a0f254f

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2774.188 ; gain = 0.000 ; free physical = 179 ; free virtual = 23078

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 21a0f254f

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2774.188 ; gain = 0.000 ; free physical = 179 ; free virtual = 23078
Phase 1 Initialization | Checksum: 21a0f254f

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2774.188 ; gain = 0.000 ; free physical = 179 ; free virtual = 23078

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 21a0f254f

Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2774.188 ; gain = 0.000 ; free physical = 177 ; free virtual = 23076

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 21a0f254f

Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2774.188 ; gain = 0.000 ; free physical = 178 ; free virtual = 23077
Phase 2 Timer Update And Timing Data Collection | Checksum: 21a0f254f

Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2774.188 ; gain = 0.000 ; free physical = 178 ; free virtual = 23077

Phase 3 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 21a0f254f

Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.5 . Memory (MB): peak = 2774.188 ; gain = 0.000 ; free physical = 174 ; free virtual = 23074
Retarget | Checksum: 21a0f254f
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 2237e48ce

Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2774.188 ; gain = 0.000 ; free physical = 174 ; free virtual = 23074
Constant propagation | Checksum: 2237e48ce
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
Phase 5 Sweep | Checksum: 2125addad

Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.64 . Memory (MB): peak = 2774.188 ; gain = 0.000 ; free physical = 179 ; free virtual = 23078
Sweep | Checksum: 2125addad
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 2125addad

Time (s): cpu = 00:00:00.98 ; elapsed = 00:00:00.75 . Memory (MB): peak = 2806.203 ; gain = 32.016 ; free physical = 177 ; free virtual = 23076
BUFG optimization | Checksum: 2125addad
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 2125addad

Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2806.203 ; gain = 32.016 ; free physical = 177 ; free virtual = 23076
Shift Register Optimization | Checksum: 2125addad
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 2125addad

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2806.203 ; gain = 32.016 ; free physical = 177 ; free virtual = 23076
Post Processing Netlist | Checksum: 2125addad
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1d68971d8

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.88 . Memory (MB): peak = 2806.203 ; gain = 32.016 ; free physical = 176 ; free virtual = 23076

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2806.203 ; gain = 0.000 ; free physical = 176 ; free virtual = 23075
Phase 9.2 Verifying Netlist Connectivity | Checksum: 1d68971d8

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.89 . Memory (MB): peak = 2806.203 ; gain = 32.016 ; free physical = 175 ; free virtual = 23075
Phase 9 Finalization | Checksum: 1d68971d8

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.89 . Memory (MB): peak = 2806.203 ; gain = 32.016 ; free physical = 175 ; free virtual = 23075
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               0  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 1d68971d8

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.9 . Memory (MB): peak = 2806.203 ; gain = 32.016 ; free physical = 175 ; free virtual = 23074
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2806.203 ; gain = 0.000 ; free physical = 174 ; free virtual = 23074

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1d68971d8

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2806.203 ; gain = 0.000 ; free physical = 178 ; free virtual = 23078

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1d68971d8

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2806.203 ; gain = 0.000 ; free physical = 178 ; free virtual = 23078

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2806.203 ; gain = 0.000 ; free physical = 178 ; free virtual = 23078
Ending Netlist Obfuscation Task | Checksum: 1d68971d8

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2806.203 ; gain = 0.000 ; free physical = 178 ; free virtual = 23078
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 2806.203 ; gain = 455.762 ; free physical = 178 ; free virtual = 23078
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2838.219 ; gain = 0.000 ; free physical = 174 ; free virtual = 23073
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1c7551108

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2838.219 ; gain = 0.000 ; free physical = 173 ; free virtual = 23073
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2838.219 ; gain = 0.000 ; free physical = 173 ; free virtual = 23072

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 16a8ae138

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2838.219 ; gain = 0.000 ; free physical = 171 ; free virtual = 23070

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 260f93dad

Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2845.246 ; gain = 7.027 ; free physical = 169 ; free virtual = 23068

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 260f93dad

Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2845.246 ; gain = 7.027 ; free physical = 169 ; free virtual = 23068
Phase 1 Placer Initialization | Checksum: 260f93dad

Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2845.246 ; gain = 7.027 ; free physical = 169 ; free virtual = 23068

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 230cece72

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2845.246 ; gain = 7.027 ; free physical = 181 ; free virtual = 23081

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1c7d2f3e5

Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2845.246 ; gain = 7.027 ; free physical = 181 ; free virtual = 23081

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1c7d2f3e5

Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2845.246 ; gain = 7.027 ; free physical = 181 ; free virtual = 23081

Phase 2.4 Global Placement Core

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1c2cf9d65

Time (s): cpu = 00:00:29 ; elapsed = 00:00:20 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 239 ; free virtual = 23033

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 112 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 53 nets or LUTs. Breaked 0 LUT, combined 53 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 239 ; free virtual = 23033

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |             53  |                    53  |           0  |           1  |  00:00:01  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            0  |             53  |                    53  |           0  |           4  |  00:00:01  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2665f1c40

Time (s): cpu = 00:00:33 ; elapsed = 00:00:23 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 254 ; free virtual = 23048
Phase 2.4 Global Placement Core | Checksum: 248581ef9

Time (s): cpu = 00:00:57 ; elapsed = 00:00:35 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 240 ; free virtual = 23034
Phase 2 Global Placement | Checksum: 248581ef9

Time (s): cpu = 00:00:57 ; elapsed = 00:00:35 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 240 ; free virtual = 23034

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 23046d0b5

Time (s): cpu = 00:00:58 ; elapsed = 00:00:36 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 231 ; free virtual = 23025

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 239be4eab

Time (s): cpu = 00:01:02 ; elapsed = 00:00:39 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 231 ; free virtual = 23025

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 2561f84b1

Time (s): cpu = 00:01:02 ; elapsed = 00:00:39 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 240 ; free virtual = 23034

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1882c371a

Time (s): cpu = 00:01:03 ; elapsed = 00:00:39 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 237 ; free virtual = 23031

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 176b53c3c

Time (s): cpu = 00:01:04 ; elapsed = 00:00:41 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 240 ; free virtual = 23034

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1dfde8771

Time (s): cpu = 00:01:04 ; elapsed = 00:00:41 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 240 ; free virtual = 23034

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 2041f257c

Time (s): cpu = 00:01:04 ; elapsed = 00:00:41 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 240 ; free virtual = 23034
Phase 3 Detail Placement | Checksum: 2041f257c

Time (s): cpu = 00:01:04 ; elapsed = 00:00:41 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 240 ; free virtual = 23034

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 22bb5cb09

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.054 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 14a79a85e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.88 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 238 ; free virtual = 23032
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 14a79a85e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.99 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 238 ; free virtual = 23032
Phase 4.1.1.1 BUFG Insertion | Checksum: 22bb5cb09

Time (s): cpu = 00:01:11 ; elapsed = 00:00:46 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 238 ; free virtual = 23032

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=1.054. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 19209d0e5

Time (s): cpu = 00:01:11 ; elapsed = 00:00:46 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 238 ; free virtual = 23032

Time (s): cpu = 00:01:11 ; elapsed = 00:00:46 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 238 ; free virtual = 23032
Phase 4.1 Post Commit Optimization | Checksum: 19209d0e5

Time (s): cpu = 00:01:11 ; elapsed = 00:00:46 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 238 ; free virtual = 23032

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 19209d0e5

Time (s): cpu = 00:01:11 ; elapsed = 00:00:46 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 238 ; free virtual = 23032

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                2x2|
|___________|___________________|___________________|
|      South|                1x1|                1x1|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 19209d0e5

Time (s): cpu = 00:01:11 ; elapsed = 00:00:46 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 238 ; free virtual = 23032
Phase 4.3 Placer Reporting | Checksum: 19209d0e5

Time (s): cpu = 00:01:11 ; elapsed = 00:00:46 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 238 ; free virtual = 23032

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 238 ; free virtual = 23032

Time (s): cpu = 00:01:11 ; elapsed = 00:00:46 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 238 ; free virtual = 23032
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f1ba7efc

Time (s): cpu = 00:01:11 ; elapsed = 00:00:46 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 238 ; free virtual = 23032
Ending Placer Task | Checksum: 19af5f5a5

Time (s): cpu = 00:01:11 ; elapsed = 00:00:46 . Memory (MB): peak = 2877.262 ; gain = 39.043 ; free physical = 238 ; free virtual = 23032
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:14 ; elapsed = 00:00:47 . Memory (MB): peak = 2877.262 ; gain = 71.059 ; free physical = 238 ; free virtual = 23032
# report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
# report_utilization -file digilent_arty_a7_utilization_place.rpt
# report_io -file digilent_arty_a7_io.rpt
report_io: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 229 ; free virtual = 23023
# report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 227 ; free virtual = 23021
# report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: d41e8f4a ConstDB: 0 ShapeSum: c6d7665b RouteDB: 0
Post Restoration Checksum: NetGraph: 4707b737 | NumContArr: 9852b2aa | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 264ac5f1b

Time (s): cpu = 00:01:26 ; elapsed = 00:01:16 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 233 ; free virtual = 23030

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 264ac5f1b

Time (s): cpu = 00:01:26 ; elapsed = 00:01:16 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 233 ; free virtual = 23030

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 264ac5f1b

Time (s): cpu = 00:01:26 ; elapsed = 00:01:16 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 233 ; free virtual = 23030
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 34b177c39

Time (s): cpu = 00:01:34 ; elapsed = 00:01:21 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 210 ; free virtual = 23007
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.130  | TNS=0.000  | WHS=-0.153 | THS=-16.209|


Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 1448
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 1448
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 2 Router Initialization | Checksum: 28bbd67ea

Time (s): cpu = 00:01:37 ; elapsed = 00:01:22 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 200 ; free virtual = 22997

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 28bbd67ea

Time (s): cpu = 00:01:37 ; elapsed = 00:01:22 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 208 ; free virtual = 23005

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 1f608f1fd

Time (s): cpu = 00:01:40 ; elapsed = 00:01:24 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 209 ; free virtual = 23006
Phase 3 Initial Routing | Checksum: 1f608f1fd

Time (s): cpu = 00:01:40 ; elapsed = 00:01:24 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 209 ; free virtual = 23006

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 190
 Number of Nodes with overlaps = 34
 Number of Nodes with overlaps = 12
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.481  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 1f6d0962d

Time (s): cpu = 00:01:47 ; elapsed = 00:01:29 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 208 ; free virtual = 23005
Phase 4 Rip-up And Reroute | Checksum: 1f6d0962d

Time (s): cpu = 00:01:47 ; elapsed = 00:01:29 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 208 ; free virtual = 23005

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 1c60acb51

Time (s): cpu = 00:01:48 ; elapsed = 00:01:30 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 200 ; free virtual = 22997
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.569  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 5.1 Delay CleanUp | Checksum: 1c60acb51

Time (s): cpu = 00:01:48 ; elapsed = 00:01:30 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 207 ; free virtual = 23004

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1c60acb51

Time (s): cpu = 00:01:48 ; elapsed = 00:01:30 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 207 ; free virtual = 23004
Phase 5 Delay and Skew Optimization | Checksum: 1c60acb51

Time (s): cpu = 00:01:48 ; elapsed = 00:01:30 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 207 ; free virtual = 23004

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1d33517b8

Time (s): cpu = 00:01:50 ; elapsed = 00:01:31 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 207 ; free virtual = 23004
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.569  | TNS=0.000  | WHS=0.066  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 219841b00

Time (s): cpu = 00:01:50 ; elapsed = 00:01:31 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 207 ; free virtual = 23004
Phase 6 Post Hold Fix | Checksum: 219841b00

Time (s): cpu = 00:01:50 ; elapsed = 00:01:31 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 207 ; free virtual = 23004

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.703094 %
  Global Horizontal Routing Utilization  = 0.617718 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 219841b00

Time (s): cpu = 00:01:50 ; elapsed = 00:01:31 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 207 ; free virtual = 23004

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 219841b00

Time (s): cpu = 00:01:50 ; elapsed = 00:01:31 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 207 ; free virtual = 23004

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 2479f3c8f

Time (s): cpu = 00:01:51 ; elapsed = 00:01:32 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 207 ; free virtual = 23004

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.569  | TNS=0.000  | WHS=0.066  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 2479f3c8f

Time (s): cpu = 00:01:53 ; elapsed = 00:01:33 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 207 ; free virtual = 23004
INFO: [Route 35-16] Router Completed Successfully

Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 171a436b0

Time (s): cpu = 00:01:53 ; elapsed = 00:01:33 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 198 ; free virtual = 22995
Ending Routing Task | Checksum: 171a436b0

Time (s): cpu = 00:01:53 ; elapsed = 00:01:33 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 190 ; free virtual = 22987

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
13 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:56 ; elapsed = 00:01:36 . Memory (MB): peak = 2877.262 ; gain = 0.000 ; free physical = 193 ; free virtual = 22990
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (1)
------------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (1)
-------------------------------
 There is 1 port with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      1.570        0.000                      0                11929        0.065        0.000                      0                11929        3.750        0.000                       0                  1660  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock        Waveform(ns)         Period(ns)      Frequency(MHz)
-----        ------------         ----------      --------------
sck          {0.000 50.000}       100.000         10.000          
sys_clk_pin  {0.000 5.000}        10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
sys_clk_pin         1.570        0.000                      0                11929        0.065        0.000                      0                11929        3.750        0.000                       0                  1660  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


# report_route_status -file digilent_arty_a7_route_status.rpt
# report_drc -file digilent_arty_a7_drc.rpt
Command: report_drc -file digilent_arty_a7_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/nerv/nerv/digilent_arty_a7_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_arty_a7_power.rpt
Command: report_power -file digilent_arty_a7_power.rpt
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "digilent_arty_a7_100t.bit"
Command: write_bitstream -force digilent_arty_a7_100t.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_arty_a7_100t.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 3149.301 ; gain = 249.180 ; free physical = 337 ; free virtual = 23093
# exit
INFO: [Common 17-206] Exiting Vivado at Sun Apr  6 03:27:26 2025...

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
[Pipeline] dir
Running in /var/jenkins_home/workspace/nerv/nerv
[Pipeline] {
Final configuration file generated at /var/jenkins_home/workspace/nerv/nerv/build_colorlight_i9.tcl
Makefile executed successfully.
Makefile output:
/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 (null)
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE

Loading: [=====                                             ] 8.39%
Loading: [=========                                         ] 16.48%
Loading: [============                                      ] 23.94%
Loading: [=================                                 ] 32.02%
Loading: [=====================                             ] 40.42%
Loading: [=========================                         ] 48.81%
Loading: [=============================                     ] 56.89%
Loading: [=================================                 ] 65.29%
Loading: [=====================================             ] 73.68%
Loading: [==========================================        ] 82.08%
Loading: [==============================================    ] 90.47%
Loading: [==================================================] 98.87%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE

[Pipeline] echo
Flashing FPGA digilent_arty_a7_100t.
[Pipeline] sh
[Pipeline] }
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p nerv -b digilent_arty_a7_100t -l
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
[Pipeline] echo
Testing FPGA colorlight_i9.
[Pipeline] dir
Running in /var/jenkins_home/workspace/nerv/nerv
[Pipeline] {
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyACM0
Test for FPGA in /dev/ttyACM0
[Pipeline] sh
+ python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0
Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'}
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
Final configuration file generated at /var/jenkins_home/workspace/nerv/nerv/build_digilent_arty_a7_100t.tcl
Makefile executed successfully.
Makefile output:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit
empty
Jtag frequency : requested 10.00MHz   -> real 10.00MHz  
Open file DONE
Parse file DONE
load program

Load SRAM: [================                                  ] 31.00%
Load SRAM: [================================                  ] 63.00%
Load SRAM: [===============================================   ] 94.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1

[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // dir
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
[Pipeline] echo
Testing FPGA digilent_arty_a7_100t.
[Pipeline] dir
Running in /var/jenkins_home/workspace/nerv/nerv
[Pipeline] {
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyUSB1
Test for FPGA in /dev/ttyUSB1
[Pipeline] sh
+ python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1
Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'}
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 2a0e698b-ba8d-4f3a-98f1-565b99b40bd3
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: No test report files were found. Configuration error?
Finished: FAILURE