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Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/mriscv [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf mriscv [Pipeline] sh + git clone --recursive --depth=1 https://github.com/onchipuis/mriscv mriscv Cloning into 'mriscv'... Submodule 'mriscvcore' (https://github.com/onchipuis/mriscvcore.git) registered for path 'mriscvcore' Cloning into '/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore'... Submodule path 'mriscvcore': checked out '1e94fa95bcdddb889be205ed661b9addff1221a4' [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/mriscv/mriscv [Pipeline] { [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s mriscvcore mriscvcore/mriscvcore.v mriscvcore/ALU/ALU.v mriscvcore/DECO_INSTR/DECO_INSTR.v mriscvcore/FSM/FSM.v mriscvcore/IRQ/IRQ.v mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v mriscvcore/MULT/MULT.v mriscvcore/REG_FILE/REG_FILE.v mriscvcore/UTILITIES/UTILITY.v mriscvcore/DECO_INSTR/DECO_INSTR.v:112: warning: Extra digits given for sized binary constant. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/mriscv/mriscv [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/mriscv/mriscv -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels WARNING: Error reading file /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR_tb.v with encoding utf-8: 'utf-8' codec can't decode byte 0xd3 in position 602: invalid continuation byte WARNING: Error reading file /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v with encoding utf-8: 'utf-8' codec can't decode byte 0xf3 in position 3316: invalid continuation byte Trying to read file: /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v Cache-related signals in axi4_interconnect.v Cache-related signals in priencr.v Cache-related signals in axi4_interconnect.v Results saved to /jenkins/processor_ci_utils/labels/mriscv.json [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] Resource [colorlight_i9] did not exist. Created. Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] Resource [digilent_arty_a7_100t] did not exist. Created. Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/mriscv/mriscv [Pipeline] { [Pipeline] dir Running in /var/jenkins_home/workspace/mriscv/mriscv [Pipeline] { [Pipeline] echo Starting synthesis for FPGA colorlight_i9. [Pipeline] sh [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mriscv -b colorlight_i9 [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mriscv -b digilent_arty_a7_100t Final configuration file generated at /var/jenkins_home/workspace/mriscv/mriscv/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/synlig -c /var/jenkins_home/workspace/mriscv/mriscv/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096 -- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' -- 1. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v Parsing Verilog input from `/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v' to AST representation. Generating RTLIL representation for module `\mriscvcore'. /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:130: Warning: Identifier `\rdw_rsrn' is implicitly declared. /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:204: Warning: Identifier `\enable_pc' is implicitly declared. /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:223: Warning: Identifier `\done_exec' is implicitly declared. /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:231: Warning: Identifier `\enable_exec' is implicitly declared. /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:232: Warning: Identifier `\enable_exec_mem' is implicitly declared. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v Parsing Verilog input from `/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:382) Generating RTLIL representation for module `\ALU'. Generating RTLIL representation for module `\ALU_add'. Generating RTLIL representation for module `\ALU_sub'. Generating RTLIL representation for module `\ALU_and'. Generating RTLIL representation for module `\ALU_xor'. Generating RTLIL representation for module `\ALU_or'. Generating RTLIL representation for module `\ALU_beq'. Generating RTLIL representation for module `\ALU_blt'. Generating RTLIL representation for module `\ALU_bltu'. Generating RTLIL representation for module `\ALU_sXXx'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v Parsing Verilog input from `/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v' to AST representation. Generating RTLIL representation for module `\DECO_INSTR'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v Parsing Verilog input from `/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v' to AST representation. Generating RTLIL representation for module `\FSM'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v Parsing Verilog input from `/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:228) Generating RTLIL representation for module `\divM'. Generating RTLIL representation for module `\Count'. Generating RTLIL representation for module `\IRQ'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v Parsing Verilog input from `/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:336) Generating RTLIL representation for module `\MEMORY_INTERFACE'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v Parsing Verilog input from `/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:197) Generating RTLIL representation for module `\FSM_Booth'. Note: Assuming pure combinatorial block at /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17.2-31.9 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Note: Assuming pure combinatorial block at /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:39.2-43.24 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Generating RTLIL representation for module `\Alg_Booth'. Generating RTLIL representation for module `\MULT'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v Parsing Verilog input from `/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v' to AST representation. Generating RTLIL representation for module `\true_dpram_sclk'. Generating RTLIL representation for module `\REG_FILE'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v Parsing Verilog input from `/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:78) Generating RTLIL representation for module `\UTILITY'. Note: Assuming pure combinatorial block at /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52.5-61.16 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Note: Assuming pure combinatorial block at /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64.5-76.8 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /eda/processor_ci/rtl/mriscv.v Parsing Verilog input from `/eda/processor_ci/rtl/mriscv.v' to AST representation. Generating RTLIL representation for module `\processorci_top'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation. Generating RTLIL representation for module `\ClkDivider'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation. Generating RTLIL representation for module `\Interpreter'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation. Generating RTLIL representation for module `\Controller'. Successfully finished Verilog frontend. 20. Executing SYNTH_ECP5 pass. 20.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_sim.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 20.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_bb.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 20.3. Executing HIERARCHY pass (managing design hierarchy). 20.3.1. Analyzing design hierarchy.. Top module: \processorci_top Used module: \ResetBootSystem Used module: \mriscvcore Used module: \FSM Used module: \UTILITY Used module: \MULT Used module: \Alg_Booth Used module: \FSM_Booth Used module: \IRQ Used module: \Count Used module: \divM Used module: \ALU Used module: \ALU_sXXx Used module: \ALU_bltu Used module: \ALU_blt Used module: \ALU_beq Used module: \ALU_or Used module: \ALU_xor Used module: \ALU_and Used module: \ALU_sub Used module: \ALU_add Used module: \REG_FILE Used module: \true_dpram_sclk Used module: \DECO_INSTR Used module: \MEMORY_INTERFACE Used module: \Controller Used module: \Memory Used module: \UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 20.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ALU_sXXx'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 Generating RTLIL representation for module `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 20.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\ALU_bltu'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 Generating RTLIL representation for module `$paramod\ALU_bltu\REG_ALU=1'1\REG_OUT=1'1'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 20.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ALU_blt'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 Generating RTLIL representation for module `$paramod\ALU_blt\REG_ALU=1'1\REG_OUT=1'1'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 20.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\ALU_beq'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 Generating RTLIL representation for module `$paramod\ALU_beq\REG_ALU=1'1\REG_OUT=1'1'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 20.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\ALU_or'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 Generating RTLIL representation for module `$paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 20.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\ALU_xor'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 Generating RTLIL representation for module `$paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 20.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\ALU_and'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 Generating RTLIL representation for module `$paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 20.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\ALU_sub'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 Generating RTLIL representation for module `$paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 20.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\ALU_add'. Parameter \REG_ALU = 1'1 Parameter \REG_OUT = 1'1 Generating RTLIL representation for module `$paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1'. Parameter \SWORD = 18 20.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\Alg_Booth'. Parameter \SWORD = 18 Generating RTLIL representation for module `$paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010'. Parameter \BITS_BOOTH = 17 20.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\FSM_Booth'. Parameter \BITS_BOOTH = 17 Generating RTLIL representation for module `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001'. Note: Assuming pure combinatorial block at /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17.2-31.9 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Note: Assuming pure combinatorial block at /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:39.2-43.24 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Parameter \CYCLES = 20 20.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 20.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 20.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 20.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 20.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 20.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 20.3.19. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 20.3.20. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 20.3.21. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 20.3.22. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \mriscvcore Used module: \FSM Used module: \UTILITY Used module: \MULT Used module: \Alg_Booth Used module: \FSM_Booth Used module: $paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010 Used module: $paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001 Used module: \IRQ Used module: \Count Used module: \divM Used module: \ALU Used module: $paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_bltu\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_blt\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_beq\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1 Used module: \REG_FILE Used module: \true_dpram_sclk Used module: \DECO_INSTR Used module: \MEMORY_INTERFACE Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: \Memory Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 20.3.23. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 20.3.24. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 20.3.25. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'. 20.3.26. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \mriscvcore Used module: \FSM Used module: \UTILITY Used module: \MULT Used module: \Alg_Booth Used module: \FSM_Booth Used module: $paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010 Used module: $paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001 Used module: \IRQ Used module: \Count Used module: \divM Used module: \ALU Used module: $paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_bltu\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_blt\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_beq\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1 Used module: \REG_FILE Used module: \true_dpram_sclk Used module: \DECO_INSTR Used module: \MEMORY_INTERFACE Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 20.3.27. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 20.3.28. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 20.3.29. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \mriscvcore Used module: \FSM Used module: \UTILITY Used module: \MULT Used module: \Alg_Booth Used module: \FSM_Booth Used module: $paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010 Used module: $paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001 Used module: \IRQ Used module: \Count Used module: \divM Used module: \ALU Used module: $paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_bltu\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_blt\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_beq\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1 Used module: \REG_FILE Used module: \true_dpram_sclk Used module: \DECO_INSTR Used module: \MEMORY_INTERFACE Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider 20.3.30. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \mriscvcore Used module: \FSM Used module: \UTILITY Used module: \MULT Used module: \Alg_Booth Used module: \FSM_Booth Used module: $paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010 Used module: $paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001 Used module: \IRQ Used module: \Count Used module: \divM Used module: \ALU Used module: $paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_bltu\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_blt\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_beq\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1 Used module: $paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1 Used module: \REG_FILE Used module: \true_dpram_sclk Used module: \DECO_INSTR Used module: \MEMORY_INTERFACE Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'. Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'. Removing unused module `\Controller'. Removing unused module `\Interpreter'. Removing unused module `\Memory'. Removing unused module `\ClkDivider'. Removing unused module `\ResetBootSystem'. Removing unused module `\FIFO'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\UART'. Removing unused module `\ALU_sXXx'. Removing unused module `\ALU_bltu'. Removing unused module `\ALU_blt'. Removing unused module `\ALU_beq'. Removing unused module `\ALU_or'. Removing unused module `\ALU_xor'. Removing unused module `\ALU_and'. Removing unused module `\ALU_sub'. Removing unused module `\ALU_add'. Removed 23 unused modules. 20.4. Executing PROC pass (convert processes to netlists). 20.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$741'. Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$977'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$977'. Cleaned up 2 empty switches. 20.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:615$850 in module $paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1. Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$848 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$800 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$742 in module TRELLIS_DPR16X4. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$1157 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$1149 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1350 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1348 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1340 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1337 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1331 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1326 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1321 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1312 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1299 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1297 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1289 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1275 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1269 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1264 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1251 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1242 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1206 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1198 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1198 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1193 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1188 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$1183 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$966 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$955 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$905 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:100$331 in module UTILITY. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328 in module UTILITY. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322 in module UTILITY. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321 in module UTILITY. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:44$318 in module UTILITY. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:31$313 in module UTILITY. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:24$310 in module UTILITY. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:28$296 in module true_dpram_sclk. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:234$289 in module MULT. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:230$283 in module MULT. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:226$277 in module MULT. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:211$274 in module MULT. Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249 in module MULT. Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$243 in module Alg_Booth. Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$243 in module Alg_Booth. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:39$236 in module FSM_Booth. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:33$234 in module FSM_Booth. Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17$230 in module FSM_Booth. Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17$230 in module FSM_Booth. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:321$226 in module MEMORY_INTERFACE. Removed 9 dead cases from process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211 in module MEMORY_INTERFACE. Marked 16 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211 in module MEMORY_INTERFACE. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:197$209 in module MEMORY_INTERFACE. Marked 22 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167 in module MEMORY_INTERFACE. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:262$165 in module IRQ. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:255$163 in module IRQ. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:250$161 in module IRQ. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:244$158 in module IRQ. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:217$157 in module IRQ. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:208$155 in module IRQ. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:199$149 in module IRQ. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:191$146 in module IRQ. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:177$139 in module IRQ. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:147$137 in module IRQ. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:142$135 in module IRQ. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:98$127 in module Count. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:81$125 in module Count. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:64$122 in module Count. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:26$114 in module divM. Marked 10 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:62$104 in module FSM. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:41$97 in module FSM. Marked 10 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:22$66 in module DECO_INSTR. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:39$900 in module $paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:33$898 in module $paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001. Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17$894 in module $paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001. Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17$894 in module $paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001. Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$888 in module $paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010. Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$888 in module $paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:403$882 in module $paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:435$879 in module $paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:466$876 in module $paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:497$873 in module $paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:528$870 in module $paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:368$28 in module ALU. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:212$26 in module ALU. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:230$20 in module ALU. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:77$16 in module ALU. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:51$12 in module ALU. Removed a total of 14 dead cases. 20.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 23 redundant assignments. Promoted 194 assignments to connections. 20.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$849'. Set init value: \Q = 1'0 Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1182'. Set init value: \read_ptr = 6'000000 Set init value: \write_ptr = 6'000000 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1352'. Set init value: \i = 0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1305'. Set init value: \i = 0 Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1257'. Set init value: \clk_o_auto = 1'0 Set init value: \clk_counter = 0 Set init value: \pulse_counter = 0 Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1235'. Set init value: \state = 8'00000000 Set init value: \counter = 8'00000000 Set init value: \read_buffer = 0 Set init value: \timeout = 0 Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000 Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1205'. Set init value: \read_response = 1'0 Set init value: \write_response = 1'0 Set init value: \read_data = 0 Set init value: \uart_tx_en = 1'0 Set init value: \tx_fifo_read = 1'0 Set init value: \tx_fifo_write = 1'0 Set init value: \rx_fifo_read = 1'0 Set init value: \rx_fifo_write = 1'0 Set init value: \uart_tx_data = 8'00000000 Set init value: \tx_fifo_write_data = 8'00000000 Set init value: \rx_fifo_write_data = 8'00000000 Set init value: \counter_write = 3'000 Set init value: \counter_read = 3'000 Set init value: \state_read = 4'0000 Set init value: \state_write = 4'0000 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$912'. Set init value: \state = 2'01 Set init value: \reset_o = 1'0 Set init value: \counter = 6'000000 Found init rule in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$340'. Set init value: \RD_DATA = 0 Found init rule in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$339'. Set init value: \PC_N2 = 0 Found init rule in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$338'. Set init value: \PC_N = 0 Found init rule in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$337'. Set init value: \rd_n = 0 Found init rule in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$336'. Set init value: \TIME = 0 Found init rule in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:19$335'. Set init value: \REAL_TIME = 64'0000000000000000000000000000000000000000000000000000000000000000 Found init rule in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:19$334'. Set init value: \N_INSTRUC = 64'0000000000000000000000000000000000000000000000000000000000000000 Found init rule in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:19$333'. Set init value: \N_CYCLE = 64'0000000000000000000000000000000000000000000000000000000000000000 Found init rule in `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:95$132'. Set init value: \divcounter = 0 Found init rule in `\divM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:23$121'. Set init value: \divcounter = 0 20.4.5. Executing PROC_ARST pass (detect async resets in processes). 20.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~257 debug messages> 20.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod\ALU_bltu\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:592$864'. Creating decoders for process `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:615$850'. 1/5: $0\count[4:0] 2/5: $0\SRA_Alu[31:0] 3/5: $0\SLL_Alu[31:0] 4/5: $0\SRL_Alu[31:0] 5/5: $0\sl_ok[0:0] Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$849'. Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$848'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$800'. 1/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$799_EN[3:0]$806 2/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$799_DATA[3:0]$805 3/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$799_ADDR[3:0]$804 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$742'. 1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$740_EN[3:0]$748 2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$740_DATA[3:0]$747 3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$740_ADDR[3:0]$746 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$741'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1182'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1157'. 1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1169 2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_DATA[7:0]$1168 3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_ADDR[5:0]$1167 4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1163 5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_DATA[7:0]$1162 6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_ADDR[5:0]$1161 7/7: $0\write_ptr[5:0] Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1149'. 1/2: $0\read_ptr[5:0] 2/2: $0\read_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1352'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1350'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1348'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1340'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1337'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1331'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1326'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1321'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1312'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1305'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1299'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1297'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1289'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1275'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1269'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1264'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1257'. Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1251'. 1/1: $0\pulse_counter[31:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1242'. 1/2: $0\clk_counter[31:0] 2/2: $0\clk_o_auto[0:0] Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1235'. Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. 1/28: $0\state[7:0] 2/28: $0\reset_bus[0:0] 3/28: $0\memory_write[0:0] 4/28: $0\memory_read[0:0] 5/28: $0\write_pulse[0:0] 6/28: $0\core_reset[0:0] 7/28: $0\communication_write[0:0] 8/28: $0\communication_read[0:0] 9/28: $0\temp_buffer[63:0] 10/28: $0\accumulator[63:0] 11/28: $0\timeout_counter[31:0] 12/28: $0\timeout[31:0] 13/28: $0\read_buffer[31:0] 14/28: $0\communication_buffer[31:0] 15/28: $0\num_of_positions[23:0] 16/28: $0\num_of_pages[23:0] 17/28: $0\return_state[7:0] 18/28: $0\memory_page_number[23:0] 19/28: $0\memory_mux_selector[0:0] 20/28: $0\end_position[31:0] 21/28: $0\memory_page_size[23:0] 22/28: $0\bus_mode[0:0] 23/28: $0\num_of_cycles_to_pulse[31:0] 24/28: $0\core_clk_enable[0:0] 25/28: $0\communication_write_data[31:0] 26/28: $0\counter[7:0] 27/28: $0\write_data[31:0] 28/28: $0\address[31:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1205'. Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1198'. 1/4: $0\tx_fifo_read[0:0] 2/4: $0\uart_tx_en[0:0] 3/4: $0\tx_fifo_read_state[1:0] 4/4: $0\uart_tx_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1193'. 1/2: $0\rx_fifo_write[0:0] 2/2: $0\rx_fifo_write_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1188'. 1/6: $0\tx_fifo_write[0:0] 2/6: $0\write_response[0:0] 3/6: $0\state_write[3:0] 4/6: $0\counter_write[2:0] 5/6: $0\write_data_buffer[31:0] 6/6: $0\tx_fifo_write_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1183'. 1/5: $0\read_response[0:0] 2/5: $0\rx_fifo_read[0:0] 3/5: $0\state_read[3:0] 4/5: $0\counter_read[2:0] 5/5: $0\read_data[31:0] Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$976'. Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$966'. 1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$975 2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_DATA[31:0]$974 3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_ADDR[31:0]$973 4/4: $0\read_sync[31:0] Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$955'. 1/1: $0\finish_execution[0:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$912'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$905'. 1/3: $0\counter[5:0] 2/3: $0\reset_o[0:0] 3/3: $0\state[1:0] Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$340'. Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$339'. Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$338'. Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$337'. Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$336'. Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:19$335'. Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:19$334'. Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:19$333'. Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:100$331'. 1/1: $0\PC_N2[31:0] Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328'. 1/3: $3\PC_N[31:0] 2/3: $2\PC_N[31:0] 3/3: $1\PC_N[31:0] Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322'. 1/3: $1\rd_n[31:0] 2/3: $1\is_inst[0:0] 3/3: $1\is_rd[0:0] Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321'. 1/1: $1\RD_DATA[31:0] Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:44$318'. 1/1: $0\N_INSTRUC[63:0] Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:31$313'. 1/2: $0\TIME[31:0] 2/2: $0\REAL_TIME[63:0] Creating decoders for process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:24$310'. 1/1: $0\N_CYCLE[63:0] Creating decoders for process `\true_dpram_sclk.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:28$296'. 1/3: $1$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$302 2/3: $1$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_DATA[31:0]$301 3/3: $1$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_ADDR[4:0]$300 Creating decoders for process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:234$289'. 1/2: $2\cont3[4:0] 2/2: $1\cont3[4:0] Creating decoders for process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:230$283'. 1/2: $2\cont2[4:0] 2/2: $1\cont2[4:0] Creating decoders for process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:226$277'. 1/2: $2\cont1[4:0] 2/2: $1\cont1[4:0] Creating decoders for process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:211$274'. 1/5: $3\rdu[63:0] 2/5: $2\Done[0:0] 3/5: $2\rdu[63:0] 4/5: $1\Done[0:0] 5/5: $1\rdu[63:0] Creating decoders for process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. 1/8: $3\ss1[31:0] 2/8: $2\ss2[31:0] 3/8: $2\ss1[31:0] 4/8: $1\srd[31:0] 5/8: $1\is_oper[0:0] 6/8: $1\sig[0:0] 7/8: $1\ss2[31:0] 8/8: $1\ss1[31:0] Creating decoders for process `\Alg_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$243'. 1/11: $4\S[34:0] 2/11: $4\aux[16:0] 3/11: $3\aux[16:0] 4/11: $3\S[34:0] 5/11: $3\Q1[16:0] 6/11: $2\S[34:0] 7/11: $2\Q1[16:0] 8/11: $2\aux[16:0] 9/11: $1\S[34:0] 10/11: $1\Q1[16:0] 11/11: $1\aux[16:0] Creating decoders for process `\FSM_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:39$236'. 1/3: $3\OutFSM[2:0] 2/3: $2\OutFSM[2:0] 3/3: $1\OutFSM[2:0] Creating decoders for process `\FSM_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:33$234'. 1/1: $1\state[1:0] Creating decoders for process `\FSM_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17$230'. 1/4: $4\nextState[1:0] 2/4: $3\nextState[1:0] 3/4: $2\nextState[1:0] 4/4: $1\nextState[1:0] Creating decoders for process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:321$226'. 1/4: $0\Wstrb[3:0] 2/4: $0\Wdata[31:0] 3/4: $0\rdu[31:0] 4/4: $0\inst[31:0] Creating decoders for process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. 1/34: $7\relleno24[23:0] 2/34: $6\relleno24[23:0] 3/34: $5\relleno24[23:0] 4/34: $4\relleno24[23:0] 5/34: $4\Rdataq[31:0] 6/34: $3\relleno24[23:0] 7/34: $5\relleno16[15:0] 8/34: $4\relleno16[15:0] 9/34: $3\Rdataq[31:0] 10/34: $3\relleno16[15:0] 11/34: $7\align[0:0] 12/34: $6\align[0:0] 13/34: $2\Rdataq[31:0] 14/34: $5\align[0:0] 15/34: $2\relleno24[23:0] 16/34: $2\relleno16[15:0] 17/34: $2\rd_en[0:0] 18/34: $4\align[0:0] 19/34: $3\align[0:0] 20/34: $2\Wstrbq[3:0] 21/34: $2\Wdataq[31:0] 22/34: $2\align[0:0] 23/34: $1\Wstrbq[3:0] 24/34: $1\Wdataq[31:0] 25/34: $1\align[0:0] 26/34: $1\AWdata[31:0] 27/34: $1\awprot[2:0] 28/34: $1\en_instr[0:0] 29/34: $1\Rdataq[31:0] 30/34: $1\relleno24[23:0] 31/34: $1\relleno16[15:0] 32/34: $1\arprot[2:0] 33/34: $1\rd_en[0:0] 34/34: $1\ARdata[31:0] Creating decoders for process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:197$209'. 1/1: $0\state[3:0] Creating decoders for process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167'. 1/68: $22\nexstate[3:0] 2/68: $22\busy[0:0] 3/68: $21\nexstate[3:0] 4/68: $21\busy[0:0] 5/68: $20\busy[0:0] 6/68: $20\nexstate[3:0] 7/68: $19\nexstate[3:0] 8/68: $19\busy[0:0] 9/68: $18\busy[0:0] 10/68: $18\nexstate[3:0] 11/68: $17\nexstate[3:0] 12/68: $17\busy[0:0] 13/68: $16\busy[0:0] 14/68: $16\nexstate[3:0] 15/68: $15\busy[0:0] 16/68: $15\nexstate[3:0] 17/68: $14\busy[0:0] 18/68: $14\nexstate[3:0] 19/68: $13\nexstate[3:0] 20/68: $6\en_read[0:0] 21/68: $13\busy[0:0] 22/68: $12\busy[0:0] 23/68: $12\nexstate[3:0] 24/68: $11\nexstate[3:0] 25/68: $5\en_read[0:0] 26/68: $11\busy[0:0] 27/68: $10\busy[0:0] 28/68: $10\nexstate[3:0] 29/68: $9\busy[0:0] 30/68: $9\nexstate[3:0] 31/68: $8\busy[0:0] 32/68: $8\nexstate[3:0] 33/68: $7\busy[0:0] 34/68: $7\nexstate[3:0] 35/68: $6\nexstate[3:0] 36/68: $6\busy[0:0] 37/68: $4\Bready[0:0] 38/68: $4\Wvalid[0:0] 39/68: $4\AWvalid[0:0] 40/68: $5\busy[0:0] 41/68: $5\nexstate[3:0] 42/68: $4\busy[0:0] 43/68: $4\en_read[0:0] 44/68: $4\nexstate[3:0] 45/68: $3\nexstate[3:0] 46/68: $3\en_read[0:0] 47/68: $3\busy[0:0] 48/68: $3\RReady[0:0] 49/68: $3\ARvalid[0:0] 50/68: $3\Bready[0:0] 51/68: $3\Wvalid[0:0] 52/68: $3\AWvalid[0:0] 53/68: $2\nexstate[3:0] 54/68: $2\en_read[0:0] 55/68: $2\busy[0:0] 56/68: $2\Bready[0:0] 57/68: $2\Wvalid[0:0] 58/68: $2\AWvalid[0:0] 59/68: $2\RReady[0:0] 60/68: $2\ARvalid[0:0] 61/68: $1\nexstate[3:0] 62/68: $1\en_read[0:0] 63/68: $1\busy[0:0] 64/68: $1\Bready[0:0] 65/68: $1\Wvalid[0:0] 66/68: $1\AWvalid[0:0] 67/68: $1\RReady[0:0] 68/68: $1\ARvalid[0:0] Creating decoders for process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:262$165'. 1/2: $2\pc_c_q[31:0] 2/2: $1\pc_c_q[31:0] Creating decoders for process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:255$163'. 1/3: $3\addrm_q[31:0] 2/3: $2\addrm_q[31:0] 3/3: $1\addrm_q[31:0] Creating decoders for process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:250$161'. 1/2: $2\irrstate_rd[31:0] 2/2: $1\irrstate_rd[31:0] Creating decoders for process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:244$158'. 1/2: $2\pc_irq_reg[31:0] 2/2: $1\pc_irq_reg[31:0] Creating decoders for process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:217$157'. 1/2: $1\rd1[31:0] 2/2: $1\instr_sel[8:0] Creating decoders for process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:208$155'. 1/3: $3\flag_q[0:0] 2/3: $2\flag_q[0:0] 3/3: $1\flag_q[0:0] Creating decoders for process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:199$149'. 1/1: $0\q[31:0] Creating decoders for process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:191$146'. 1/1: $0\true_irrstate[31:0] Creating decoders for process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:177$139'. 1/1: $1\regirr[31:0] Creating decoders for process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:147$137'. 1/10: $2\timer_max_count[31:0] 2/10: $2\div_freq[31:0] 3/10: $2\timer_count[31:0] 4/10: $2\irr_tisirr[0:0] 5/10: $2\enable[0:0] 6/10: $1\timer_max_count[31:0] 7/10: $1\div_freq[31:0] 8/10: $1\timer_count[31:0] 9/10: $1\irr_tisirr[0:0] 10/10: $1\enable[0:0] Creating decoders for process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:142$135'. 1/2: $2\irr_ebreak[0:0] 2/2: $1\irr_ebreak[0:0] Creating decoders for process `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:95$132'. Creating decoders for process `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:98$127'. 1/6: $3\Ready_count_int[0:0] 2/6: $3\divcounter[31:0] 3/6: $2\Ready_count_int[0:0] 4/6: $2\divcounter[31:0] 5/6: $1\Ready_count_int[0:0] 6/6: $1\divcounter[31:0] Creating decoders for process `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:81$125'. 1/4: $2\freq_int[31:0] 2/4: $2\Max_count_int[31:0] 3/4: $1\freq_int[31:0] 4/4: $1\Max_count_int[31:0] Creating decoders for process `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:64$122'. 1/9: $3\Ready_count[0:0] 2/9: $3\b[0:0] 3/9: $3\enable_int[0:0] 4/9: $2\b[0:0] 5/9: $2\Ready_count[0:0] 6/9: $2\enable_int[0:0] 7/9: $1\Ready_count[0:0] 8/9: $1\enable_int[0:0] 9/9: $1\b[0:0] Creating decoders for process `\divM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:23$121'. Creating decoders for process `\divM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:26$114'. 1/4: $2\clk_out[0:0] 2/4: $2\divcounter[31:0] 3/4: $1\clk_out[0:0] 4/4: $1\divcounter[31:0] Creating decoders for process `\FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:62$104'. 1/7: $0\state[3:0] 2/7: $0\enable_pc_fsm[0:0] 3/7: $0\enable_exec_mem[0:0] 4/7: $0\enable_exec[0:0] 5/7: $0\en_mem[0:0] 6/7: $0\W_R_mem[1:0] 7/7: $0\trap[0:0] Creating decoders for process `\FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:41$97'. 1/1: $0\enable_pc_aux[0:0] Creating decoders for process `\DECO_INSTR.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:22$66'. 1/50: $10\codif[11:0] 2/50: $10\rs2i[4:0] 3/50: $10\rs1i[4:0] 4/50: $10\rdi[4:0] 5/50: $10\immr[31:0] 6/50: $9\codif[11:0] 7/50: $9\immr[31:0] 8/50: $9\rs2i[4:0] 9/50: $9\rs1i[4:0] 10/50: $9\rdi[4:0] 11/50: $8\codif[11:0] 12/50: $8\immr[31:0] 13/50: $8\rs2i[4:0] 14/50: $8\rs1i[4:0] 15/50: $8\rdi[4:0] 16/50: $7\codif[11:0] 17/50: $7\immr[31:0] 18/50: $7\rdi[4:0] 19/50: $7\rs1i[4:0] 20/50: $7\rs2i[4:0] 21/50: $6\codif[11:0] 22/50: $6\immr[31:0] 23/50: $6\rs2i[4:0] 24/50: $6\rs1i[4:0] 25/50: $6\rdi[4:0] 26/50: $5\codif[11:0] 27/50: $5\rdi[4:0] 28/50: $5\rs2i[4:0] 29/50: $5\rs1i[4:0] 30/50: $5\immr[31:0] 31/50: $4\codif[11:0] 32/50: $4\rs2i[4:0] 33/50: $4\rdi[4:0] 34/50: $4\rs1i[4:0] 35/50: $4\immr[31:0] 36/50: $3\codif[11:0] 37/50: $3\rs2i[4:0] 38/50: $3\rs1i[4:0] 39/50: $3\rdi[4:0] 40/50: $3\immr[31:0] 41/50: $2\codif[11:0] 42/50: $2\rs2i[4:0] 43/50: $2\rdi[4:0] 44/50: $2\rs1i[4:0] 45/50: $2\immr[31:0] 46/50: $1\codif[11:0] 47/50: $1\rs2i[4:0] 48/50: $1\rs1i[4:0] 49/50: $1\rdi[4:0] 50/50: $1\immr[31:0] Creating decoders for process `\DECO_INSTR.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:17$65'. Creating decoders for process `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:39$900'. 1/3: $3\OutFSM[2:0] 2/3: $2\OutFSM[2:0] 3/3: $1\OutFSM[2:0] Creating decoders for process `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:33$898'. 1/1: $1\state[1:0] Creating decoders for process `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17$894'. 1/4: $4\nextState[1:0] 2/4: $3\nextState[1:0] 3/4: $2\nextState[1:0] 4/4: $1\nextState[1:0] Creating decoders for process `$paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$888'. 1/11: $4\S[36:0] 2/11: $4\aux[17:0] 3/11: $3\aux[17:0] 4/11: $3\S[36:0] 5/11: $3\Q1[17:0] 6/11: $2\S[36:0] 7/11: $2\Q1[17:0] 8/11: $2\aux[17:0] 9/11: $1\S[36:0] 10/11: $1\Q1[17:0] 11/11: $1\aux[17:0] Creating decoders for process `$paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:403$882'. 1/1: $0\ADD_Alu[32:0] Creating decoders for process `$paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:435$879'. 1/1: $0\SUB_Alu[31:0] Creating decoders for process `$paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:466$876'. 1/1: $0\AND_Alu[31:0] Creating decoders for process `$paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:497$873'. 1/1: $0\XOR_Alu[31:0] Creating decoders for process `$paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:528$870'. 1/1: $0\OR_Alu[31:0] Creating decoders for process `$paramod\ALU_beq\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:556$868'. Creating decoders for process `$paramod\ALU_blt\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:574$866'. Creating decoders for process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:368$28'. 1/1: $0\OUT_Alu_rd[31:0] Creating decoders for process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:212$26'. 1/2: $0\SLTU_Alu[31:0] 2/2: $0\SLT_Alu[31:0] Creating decoders for process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:230$20'. 1/3: $1\cmp[0:0] 2/3: $1\carry[0:0] 3/3: $1\OUT_Alu[31:0] Creating decoders for process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:77$16'. 1/3: $1\oper2[31:0] 2/3: $1\is_inst_nr[0:0] 3/3: $1\is_rd_nr[0:0] Creating decoders for process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:51$12'. 1/3: $0\en_reg[0:0] 2/3: $0\is_inst_reg[1:0] 3/3: $0\is_rd_reg[1:0] 20.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\ALU_bltu\REG_ALU=1'1\REG_OUT=1'1.\BLTU_Alu' from process `$paramod\ALU_bltu\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:592$864'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1321'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1264'. No latch inferred for signal `\UTILITY.\PC_N' from process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328'. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [0]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [1]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [2]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [3]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [4]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [5]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [6]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [7]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [8]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [9]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [10]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [11]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [12]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [13]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [14]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [15]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [16]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [17]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [18]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [19]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [20]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [21]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [22]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [23]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [24]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [25]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [26]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [27]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [28]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [29]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [30]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\PC_N [31]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328`. No latch inferred for signal `\UTILITY.\is_rd' from process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322'. No latch inferred for signal `\UTILITY.\is_inst' from process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322'. No latch inferred for signal `\UTILITY.\rd_n' from process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322'. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [0]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [1]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [2]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [3]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [4]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [5]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [6]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [7]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [8]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [9]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [10]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [11]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [12]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [13]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [14]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [15]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [16]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [17]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [18]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [19]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [20]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [21]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [22]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [23]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [24]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [25]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [26]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [27]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [28]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [29]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [30]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\rd_n [31]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322`. No latch inferred for signal `\UTILITY.\RD_DATA' from process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321'. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [0]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [1]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [2]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [3]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [4]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [5]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [6]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [7]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [8]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [9]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [10]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [11]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [12]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [13]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [14]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [15]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [16]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [17]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [18]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [19]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [20]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [21]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [22]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [23]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [24]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [25]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [26]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [27]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [28]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [29]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [30]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. Removing init bit 1'0 for non-memory siginal `\UTILITY.\RD_DATA [31]` in process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321`. No latch inferred for signal `\MULT.\is_oper' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\MULT.\ss2' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\MULT.\X1' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\MULT.\X0' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\MULT.\Y1' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\MULT.\Y0' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\MULT.\M1' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\MULT.\M2' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\MULT.\ss1' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\MULT.\srd' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\MULT.\ss1_ss1' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\MULT.\ss2_ss2' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\MULT.\sig' from process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. No latch inferred for signal `\FSM_Booth.\OutFSM' from process `\FSM_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:39$236'. No latch inferred for signal `\FSM_Booth.\nextState' from process `\FSM_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17$230'. No latch inferred for signal `\MEMORY_INTERFACE.\AWdata' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. No latch inferred for signal `\MEMORY_INTERFACE.\ARdata' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. No latch inferred for signal `\MEMORY_INTERFACE.\rd_en' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. No latch inferred for signal `\MEMORY_INTERFACE.\arprot' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. No latch inferred for signal `\MEMORY_INTERFACE.\awprot' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. No latch inferred for signal `\MEMORY_INTERFACE.\align' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. No latch inferred for signal `\MEMORY_INTERFACE.\relleno16' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. No latch inferred for signal `\MEMORY_INTERFACE.\relleno24' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. No latch inferred for signal `\MEMORY_INTERFACE.\Rdataq' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. No latch inferred for signal `\MEMORY_INTERFACE.\Wdataq' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. No latch inferred for signal `\MEMORY_INTERFACE.\Wstrbq' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. No latch inferred for signal `\MEMORY_INTERFACE.\en_instr' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. No latch inferred for signal `\MEMORY_INTERFACE.\ARvalid' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167'. No latch inferred for signal `\MEMORY_INTERFACE.\RReady' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167'. No latch inferred for signal `\MEMORY_INTERFACE.\AWvalid' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167'. No latch inferred for signal `\MEMORY_INTERFACE.\Wvalid' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167'. No latch inferred for signal `\MEMORY_INTERFACE.\Bready' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167'. No latch inferred for signal `\MEMORY_INTERFACE.\busy' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167'. No latch inferred for signal `\MEMORY_INTERFACE.\done' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167'. No latch inferred for signal `\MEMORY_INTERFACE.\en_read' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167'. No latch inferred for signal `\MEMORY_INTERFACE.\nexstate' from process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167'. No latch inferred for signal `\IRQ.\rd1' from process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:217$157'. No latch inferred for signal `\IRQ.\instr_sel' from process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:217$157'. No latch inferred for signal `\DECO_INSTR.\codif' from process `\DECO_INSTR.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:22$66'. No latch inferred for signal `\DECO_INSTR.\rs1i' from process `\DECO_INSTR.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:22$66'. No latch inferred for signal `\DECO_INSTR.\rs2i' from process `\DECO_INSTR.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:22$66'. No latch inferred for signal `\DECO_INSTR.\rdi' from process `\DECO_INSTR.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:22$66'. No latch inferred for signal `\DECO_INSTR.\immr' from process `\DECO_INSTR.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:22$66'. No latch inferred for signal `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.\OutFSM' from process `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:39$900'. No latch inferred for signal `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.\nextState' from process `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17$894'. No latch inferred for signal `$paramod\ALU_beq\REG_ALU=1'1\REG_OUT=1'1.\BEQ_Alu' from process `$paramod\ALU_beq\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:556$868'. No latch inferred for signal `$paramod\ALU_blt\REG_ALU=1'1\REG_OUT=1'1.\BLT_Alu' from process `$paramod\ALU_blt\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:574$866'. No latch inferred for signal `\ALU.\cmp' from process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:230$20'. No latch inferred for signal `\ALU.\carry' from process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:230$20'. No latch inferred for signal `\ALU.\OUT_Alu' from process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:230$20'. No latch inferred for signal `\ALU.\oper2' from process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:77$16'. No latch inferred for signal `\ALU.\is_rd_nr' from process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:77$16'. No latch inferred for signal `\ALU.\is_inst_nr' from process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:77$16'. 20.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.\sl_ok' using process `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:615$850'. created $dff cell `$procdff$5568' with positive edge clock. Creating register for signal `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.\SRL_Alu' using process `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:615$850'. created $dff cell `$procdff$5569' with positive edge clock. Creating register for signal `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.\SLL_Alu' using process `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:615$850'. created $dff cell `$procdff$5570' with positive edge clock. Creating register for signal `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.\SRA_Alu' using process `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:615$850'. created $dff cell `$procdff$5571' with positive edge clock. Creating register for signal `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.\count' using process `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:615$850'. created $dff cell `$procdff$5572' with positive edge clock. Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$848'. created $dff cell `$procdff$5573' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$784_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$785_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$786_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$787_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$788_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$789_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$790_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$791_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$792_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$793_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$794_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$795_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$796_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$797_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$798_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$799_ADDR' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$800'. created $dff cell `$procdff$5574' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$799_DATA' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$800'. created $dff cell `$procdff$5575' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$799_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$800'. created $dff cell `$procdff$5576' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$724_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$725_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$726_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$727_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$728_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$729_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$730_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$731_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$732_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$733_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$734_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$735_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$736_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$737_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$738_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$739_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$740_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$742'. created $dff cell `$procdff$5577' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$740_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$742'. created $dff cell `$procdff$5578' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$740_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$742'. created $dff cell `$procdff$5579' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$741'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1157'. created $dff cell `$procdff$5580' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1157'. created $dff cell `$procdff$5581' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1157'. created $dff cell `$procdff$5582' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1157'. created $dff cell `$procdff$5583' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1149'. created $dff cell `$procdff$5584' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1149'. created $dff cell `$procdff$5585' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1350'. created $dff cell `$procdff$5586' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1350'. created $dff cell `$procdff$5587' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1348'. created $dff cell `$procdff$5588' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1340'. created $dff cell `$procdff$5589' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1337'. created $dff cell `$procdff$5590' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1331'. created $dff cell `$procdff$5591' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1326'. created $dff cell `$procdff$5592' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1326'. created $dff cell `$procdff$5593' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1312'. created $dff cell `$procdff$5594' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1299'. created $dff cell `$procdff$5595' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1297'. created $dff cell `$procdff$5596' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1289'. created $dff cell `$procdff$5597' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1275'. created $dff cell `$procdff$5598' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1269'. created $dff cell `$procdff$5599' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1269'. created $dff cell `$procdff$5600' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1251'. created $dff cell `$procdff$5601' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1242'. created $dff cell `$procdff$5602' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1242'. created $dff cell `$procdff$5603' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5604' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5605' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5606' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5607' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5608' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5609' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5610' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5611' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5612' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5613' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5614' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5615' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5616' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5617' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5618' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5619' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5620' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5621' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5622' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5623' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5624' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5625' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5626' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5627' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5628' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5629' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5630' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. created $dff cell `$procdff$5631' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1198'. created $dff cell `$procdff$5632' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1198'. created $dff cell `$procdff$5633' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1198'. created $dff cell `$procdff$5634' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1198'. created $dff cell `$procdff$5635' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1193'. created $dff cell `$procdff$5636' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1193'. created $dff cell `$procdff$5637' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1188'. created $dff cell `$procdff$5638' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1188'. created $dff cell `$procdff$5639' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1188'. created $dff cell `$procdff$5640' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1188'. created $dff cell `$procdff$5641' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1188'. created $dff cell `$procdff$5642' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1188'. created $dff cell `$procdff$5643' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1183'. created $dff cell `$procdff$5644' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1183'. created $dff cell `$procdff$5645' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1183'. created $dff cell `$procdff$5646' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1183'. created $dff cell `$procdff$5647' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1183'. created $dff cell `$procdff$5648' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$976'. created $dff cell `$procdff$5649' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$976'. created $dff cell `$procdff$5650' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$966'. created $dff cell `$procdff$5651' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$966'. created $dff cell `$procdff$5652' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$966'. created $dff cell `$procdff$5653' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$966'. created $dff cell `$procdff$5654' with positive edge clock. Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$955'. created $dff cell `$procdff$5655' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$905'. created $dff cell `$procdff$5656' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$905'. created $dff cell `$procdff$5657' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$905'. created $dff cell `$procdff$5658' with positive edge clock. Creating register for signal `\UTILITY.\PC_N2' using process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:100$331'. created $dff cell `$procdff$5659' with positive edge clock. Creating register for signal `\UTILITY.\N_INSTRUC' using process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:44$318'. created $dff cell `$procdff$5660' with positive edge clock. Creating register for signal `\UTILITY.\REAL_TIME' using process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:31$313'. created $dff cell `$procdff$5661' with positive edge clock. Creating register for signal `\UTILITY.\TIME' using process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:31$313'. created $dff cell `$procdff$5662' with positive edge clock. Creating register for signal `\UTILITY.\N_CYCLE' using process `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:24$310'. created $dff cell `$procdff$5663' with positive edge clock. Creating register for signal `\true_dpram_sclk.\q_a' using process `\true_dpram_sclk.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:28$296'. created $dff cell `$procdff$5664' with positive edge clock. Creating register for signal `\true_dpram_sclk.\q_b' using process `\true_dpram_sclk.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:28$296'. created $dff cell `$procdff$5665' with positive edge clock. Creating register for signal `\true_dpram_sclk.$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_ADDR' using process `\true_dpram_sclk.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:28$296'. created $dff cell `$procdff$5666' with positive edge clock. Creating register for signal `\true_dpram_sclk.$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_DATA' using process `\true_dpram_sclk.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:28$296'. created $dff cell `$procdff$5667' with positive edge clock. Creating register for signal `\true_dpram_sclk.$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN' using process `\true_dpram_sclk.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:28$296'. created $dff cell `$procdff$5668' with positive edge clock. Creating register for signal `\MULT.\cont3' using process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:234$289'. created $dff cell `$procdff$5669' with positive edge clock. Creating register for signal `\MULT.\cont2' using process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:230$283'. created $dff cell `$procdff$5670' with positive edge clock. Creating register for signal `\MULT.\cont1' using process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:226$277'. created $dff cell `$procdff$5671' with positive edge clock. Creating register for signal `\MULT.\Done' using process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:211$274'. created $dff cell `$procdff$5672' with positive edge clock. Creating register for signal `\MULT.\rdu' using process `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:211$274'. created $dff cell `$procdff$5673' with positive edge clock. Creating register for signal `\Alg_Booth.\S' using process `\Alg_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$243'. created $dff cell `$procdff$5674' with positive edge clock. Creating register for signal `\Alg_Booth.\Q1' using process `\Alg_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$243'. created $dff cell `$procdff$5675' with positive edge clock. Creating register for signal `\Alg_Booth.\aux' using process `\Alg_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$243'. created $dff cell `$procdff$5676' with positive edge clock. Creating register for signal `\FSM_Booth.\state' using process `\FSM_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:33$234'. created $dff cell `$procdff$5677' with positive edge clock. Creating register for signal `\MEMORY_INTERFACE.\Wdata' using process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:321$226'. created $dff cell `$procdff$5678' with positive edge clock. Creating register for signal `\MEMORY_INTERFACE.\Wstrb' using process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:321$226'. created $dff cell `$procdff$5679' with positive edge clock. Creating register for signal `\MEMORY_INTERFACE.\inst' using process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:321$226'. created $dff cell `$procdff$5680' with positive edge clock. Creating register for signal `\MEMORY_INTERFACE.\rdu' using process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:321$226'. created $dff cell `$procdff$5681' with positive edge clock. Creating register for signal `\MEMORY_INTERFACE.\state' using process `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:197$209'. created $dff cell `$procdff$5682' with positive edge clock. Creating register for signal `\IRQ.\pc_c_q' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:262$165'. created $dff cell `$procdff$5683' with positive edge clock. Creating register for signal `\IRQ.\addrm_q' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:255$163'. created $dff cell `$procdff$5684' with positive edge clock. Creating register for signal `\IRQ.\irrstate_rd' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:250$161'. created $dff cell `$procdff$5685' with positive edge clock. Creating register for signal `\IRQ.\pc_irq_reg' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:244$158'. created $dff cell `$procdff$5686' with positive edge clock. Creating register for signal `\IRQ.\flag_q' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:208$155'. created $dff cell `$procdff$5687' with positive edge clock. Creating register for signal `\IRQ.\q' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:199$149'. created $dff cell `$procdff$5688' with positive edge clock. Creating register for signal `\IRQ.\true_irrstate' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:191$146'. created $dff cell `$procdff$5689' with positive edge clock. Creating register for signal `\IRQ.\regirr' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:177$139'. created $dff cell `$procdff$5690' with positive edge clock. Creating register for signal `\IRQ.\enable' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:147$137'. created $dff cell `$procdff$5691' with positive edge clock. Creating register for signal `\IRQ.\irr_tisirr' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:147$137'. created $dff cell `$procdff$5692' with positive edge clock. Creating register for signal `\IRQ.\timer_count' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:147$137'. created $dff cell `$procdff$5693' with positive edge clock. Creating register for signal `\IRQ.\timer_max_count' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:147$137'. created $dff cell `$procdff$5694' with positive edge clock. Creating register for signal `\IRQ.\div_freq' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:147$137'. created $dff cell `$procdff$5695' with positive edge clock. Creating register for signal `\IRQ.\irr_ebreak' using process `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:142$135'. created $dff cell `$procdff$5696' with positive edge clock. Creating register for signal `\Count.\divcounter' using process `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:98$127'. created $dff cell `$procdff$5697' with positive edge clock. Creating register for signal `\Count.\Ready_count_int' using process `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:98$127'. created $dff cell `$procdff$5698' with positive edge clock. Creating register for signal `\Count.\Max_count_int' using process `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:81$125'. created $dff cell `$procdff$5699' with positive edge clock. Creating register for signal `\Count.\freq_int' using process `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:81$125'. created $dff cell `$procdff$5700' with positive edge clock. Creating register for signal `\Count.\Ready_count' using process `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:64$122'. created $dff cell `$procdff$5701' with positive edge clock. Creating register for signal `\Count.\enable_int' using process `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:64$122'. created $dff cell `$procdff$5702' with positive edge clock. Creating register for signal `\Count.\b' using process `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:64$122'. created $dff cell `$procdff$5703' with positive edge clock. Creating register for signal `\divM.\clk_out' using process `\divM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:26$114'. created $dff cell `$procdff$5704' with positive edge clock. Creating register for signal `\divM.\divcounter' using process `\divM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:26$114'. created $dff cell `$procdff$5705' with positive edge clock. Creating register for signal `\FSM.\trap' using process `\FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:62$104'. created $dff cell `$procdff$5706' with positive edge clock. Creating register for signal `\FSM.\W_R_mem' using process `\FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:62$104'. created $dff cell `$procdff$5707' with positive edge clock. Creating register for signal `\FSM.\en_mem' using process `\FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:62$104'. created $dff cell `$procdff$5708' with positive edge clock. Creating register for signal `\FSM.\enable_exec' using process `\FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:62$104'. created $dff cell `$procdff$5709' with positive edge clock. Creating register for signal `\FSM.\enable_exec_mem' using process `\FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:62$104'. created $dff cell `$procdff$5710' with positive edge clock. Creating register for signal `\FSM.\enable_pc_fsm' using process `\FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:62$104'. created $dff cell `$procdff$5711' with positive edge clock. Creating register for signal `\FSM.\state' using process `\FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:62$104'. created $dff cell `$procdff$5712' with positive edge clock. Creating register for signal `\FSM.\enable_pc_aux' using process `\FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:41$97'. created $dff cell `$procdff$5713' with positive edge clock. Creating register for signal `\DECO_INSTR.\imm' using process `\DECO_INSTR.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:17$65'. created $dff cell `$procdff$5714' with positive edge clock. Creating register for signal `\DECO_INSTR.\code' using process `\DECO_INSTR.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:17$65'. created $dff cell `$procdff$5715' with positive edge clock. Creating register for signal `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.\state' using process `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:33$898'. created $dff cell `$procdff$5716' with positive edge clock. Creating register for signal `$paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010.\S' using process `$paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$888'. created $dff cell `$procdff$5717' with positive edge clock. Creating register for signal `$paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010.\Q1' using process `$paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$888'. created $dff cell `$procdff$5718' with positive edge clock. Creating register for signal `$paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010.\aux' using process `$paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$888'. created $dff cell `$procdff$5719' with positive edge clock. Creating register for signal `$paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1.\ADD_Alu' using process `$paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:403$882'. created $dff cell `$procdff$5720' with positive edge clock. Creating register for signal `$paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1.\SUB_Alu' using process `$paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:435$879'. created $dff cell `$procdff$5721' with positive edge clock. Creating register for signal `$paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1.\AND_Alu' using process `$paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:466$876'. created $dff cell `$procdff$5722' with positive edge clock. Creating register for signal `$paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1.\XOR_Alu' using process `$paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:497$873'. created $dff cell `$procdff$5723' with positive edge clock. Creating register for signal `$paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1.\OR_Alu' using process `$paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:528$870'. created $dff cell `$procdff$5724' with positive edge clock. Creating register for signal `\ALU.\OUT_Alu_rd' using process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:368$28'. created $dff cell `$procdff$5725' with positive edge clock. Creating register for signal `\ALU.\SLT_Alu' using process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:212$26'. created $dff cell `$procdff$5726' with positive edge clock. Creating register for signal `\ALU.\SLTU_Alu' using process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:212$26'. created $dff cell `$procdff$5727' with positive edge clock. Creating register for signal `\ALU.\is_rd_reg' using process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:51$12'. created $dff cell `$procdff$5728' with positive edge clock. Creating register for signal `\ALU.\is_inst_reg' using process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:51$12'. created $dff cell `$procdff$5729' with positive edge clock. Creating register for signal `\ALU.\en_reg' using process `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:51$12'. created $dff cell `$procdff$5730' with positive edge clock. 20.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 20.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod\ALU_bltu\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:592$864'. Found and cleaned up 5 empty switches in `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:615$850'. Removing empty process `$paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:615$850'. Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$849'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$848'. Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$848'. Removing empty process `DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$823'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$800'. Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$766'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$742'. Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$741'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1182'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1157'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1157'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1149'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1149'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1352'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1350'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1350'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1348'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1348'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1340'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1340'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1337'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1337'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1331'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1331'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1326'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1326'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1321'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1321'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1312'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1312'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1305'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1299'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1299'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1297'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1297'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1289'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1289'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1275'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1275'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1269'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1269'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1264'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1264'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1257'. Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1251'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1251'. Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1242'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1242'. Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1235'. Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1206'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1205'. Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1198'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1198'. Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1193'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1193'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1188'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1188'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1183'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1183'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$976'. Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$966'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$966'. Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$955'. Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$955'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$912'. Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$905'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$905'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$340'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$339'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$338'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$337'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:20$336'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:19$335'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:19$334'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:19$333'. Found and cleaned up 2 empty switches in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:100$331'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:100$331'. Found and cleaned up 3 empty switches in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:84$328'. Found and cleaned up 1 empty switch in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:64$322'. Found and cleaned up 1 empty switch in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:52$321'. Found and cleaned up 2 empty switches in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:44$318'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:44$318'. Found and cleaned up 2 empty switches in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:31$313'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:31$313'. Found and cleaned up 1 empty switch in `\UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:24$310'. Removing empty process `UTILITY.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:24$310'. Found and cleaned up 1 empty switch in `\true_dpram_sclk.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:28$296'. Removing empty process `true_dpram_sclk.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:28$296'. Found and cleaned up 2 empty switches in `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:234$289'. Removing empty process `MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:234$289'. Found and cleaned up 2 empty switches in `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:230$283'. Removing empty process `MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:230$283'. Found and cleaned up 2 empty switches in `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:226$277'. Removing empty process `MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:226$277'. Found and cleaned up 3 empty switches in `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:211$274'. Removing empty process `MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:211$274'. Found and cleaned up 4 empty switches in `\MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. Removing empty process `MULT.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:143$249'. Found and cleaned up 4 empty switches in `\Alg_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$243'. Removing empty process `Alg_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$243'. Found and cleaned up 3 empty switches in `\FSM_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:39$236'. Removing empty process `FSM_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:39$236'. Found and cleaned up 1 empty switch in `\FSM_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:33$234'. Removing empty process `FSM_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:33$234'. Found and cleaned up 4 empty switches in `\FSM_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17$230'. Removing empty process `FSM_Booth.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17$230'. Found and cleaned up 3 empty switches in `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:321$226'. Removing empty process `MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:321$226'. Found and cleaned up 16 empty switches in `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. Removing empty process `MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:205$211'. Found and cleaned up 1 empty switch in `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:197$209'. Removing empty process `MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:197$209'. Found and cleaned up 22 empty switches in `\MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167'. Removing empty process `MEMORY_INTERFACE.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:66$167'. Found and cleaned up 2 empty switches in `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:262$165'. Removing empty process `IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:262$165'. Found and cleaned up 3 empty switches in `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:255$163'. Removing empty process `IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:255$163'. Found and cleaned up 2 empty switches in `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:250$161'. Removing empty process `IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:250$161'. Found and cleaned up 2 empty switches in `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:244$158'. Removing empty process `IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:244$158'. Found and cleaned up 1 empty switch in `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:217$157'. Removing empty process `IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:217$157'. Found and cleaned up 3 empty switches in `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:208$155'. Removing empty process `IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:208$155'. Found and cleaned up 2 empty switches in `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:199$149'. Removing empty process `IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:199$149'. Found and cleaned up 2 empty switches in `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:191$146'. Removing empty process `IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:191$146'. Found and cleaned up 1 empty switch in `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:177$139'. Removing empty process `IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:177$139'. Found and cleaned up 2 empty switches in `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:147$137'. Removing empty process `IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:147$137'. Found and cleaned up 2 empty switches in `\IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:142$135'. Removing empty process `IRQ.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:142$135'. Removing empty process `Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:95$132'. Found and cleaned up 3 empty switches in `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:98$127'. Removing empty process `Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:98$127'. Found and cleaned up 2 empty switches in `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:81$125'. Removing empty process `Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:81$125'. Found and cleaned up 3 empty switches in `\Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:64$122'. Removing empty process `Count.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:64$122'. Removing empty process `divM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:23$121'. Found and cleaned up 2 empty switches in `\divM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:26$114'. Removing empty process `divM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:26$114'. Found and cleaned up 14 empty switches in `\FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:62$104'. Removing empty process `FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:62$104'. Found and cleaned up 1 empty switch in `\FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:41$97'. Removing empty process `FSM.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:41$97'. Found and cleaned up 10 empty switches in `\DECO_INSTR.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:22$66'. Removing empty process `DECO_INSTR.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:22$66'. Removing empty process `DECO_INSTR.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:17$65'. Found and cleaned up 3 empty switches in `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:39$900'. Removing empty process `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:39$900'. Found and cleaned up 1 empty switch in `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:33$898'. Removing empty process `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:33$898'. Found and cleaned up 4 empty switches in `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17$894'. Removing empty process `$paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:17$894'. Found and cleaned up 4 empty switches in `$paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$888'. Removing empty process `$paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:64$888'. Found and cleaned up 1 empty switch in `$paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:403$882'. Removing empty process `$paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:403$882'. Found and cleaned up 1 empty switch in `$paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:435$879'. Removing empty process `$paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:435$879'. Found and cleaned up 1 empty switch in `$paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:466$876'. Removing empty process `$paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:466$876'. Found and cleaned up 1 empty switch in `$paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:497$873'. Removing empty process `$paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:497$873'. Found and cleaned up 1 empty switch in `$paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:528$870'. Removing empty process `$paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:528$870'. Removing empty process `$paramod\ALU_beq\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:556$868'. Removing empty process `$paramod\ALU_blt\REG_ALU=1'1\REG_OUT=1'1.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:574$866'. Found and cleaned up 1 empty switch in `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:368$28'. Removing empty process `ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:368$28'. Found and cleaned up 1 empty switch in `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:212$26'. Removing empty process `ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:212$26'. Found and cleaned up 1 empty switch in `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:230$20'. Removing empty process `ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:230$20'. Found and cleaned up 1 empty switch in `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:77$16'. Removing empty process `ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:77$16'. Found and cleaned up 1 empty switch in `\ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:51$12'. Removing empty process `ALU.$proc$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:51$12'. Cleaned up 257 empty switches. 20.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\ALU_bltu\REG_ALU=1'1\REG_OUT=1'1. Optimizing module $paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1. <suppressed ~14 debug messages> Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. <suppressed ~5 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. <suppressed ~21 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. <suppressed ~19 debug messages> Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. <suppressed ~9 debug messages> Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. <suppressed ~15 debug messages> Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. <suppressed ~24 debug messages> Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. <suppressed ~3 debug messages> Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. <suppressed ~26 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~8 debug messages> Optimizing module processorci_top. <suppressed ~1 debug messages> Optimizing module UTILITY. <suppressed ~9 debug messages> Optimizing module REG_FILE. Optimizing module true_dpram_sclk. Optimizing module MULT. <suppressed ~11 debug messages> Optimizing module Alg_Booth. <suppressed ~14 debug messages> Optimizing module FSM_Booth. <suppressed ~8 debug messages> Optimizing module MEMORY_INTERFACE. <suppressed ~91 debug messages> Optimizing module IRQ. <suppressed ~27 debug messages> Optimizing module Count. <suppressed ~19 debug messages> Optimizing module divM. Optimizing module FSM. <suppressed ~29 debug messages> Optimizing module DECO_INSTR. <suppressed ~9 debug messages> Optimizing module $paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001. <suppressed ~8 debug messages> Optimizing module $paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010. <suppressed ~14 debug messages> Optimizing module $paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1. <suppressed ~1 debug messages> Optimizing module $paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1. <suppressed ~1 debug messages> Optimizing module $paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1. <suppressed ~1 debug messages> Optimizing module $paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1. <suppressed ~1 debug messages> Optimizing module $paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1. <suppressed ~1 debug messages> Optimizing module $paramod\ALU_beq\REG_ALU=1'1\REG_OUT=1'1. Optimizing module $paramod\ALU_blt\REG_ALU=1'1\REG_OUT=1'1. Optimizing module ALU. <suppressed ~5 debug messages> Optimizing module mriscvcore. 20.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod\ALU_bltu\REG_ALU=1'1\REG_OUT=1'1. Deleting now unused module $paramod\ALU_sXXx\REG_ALU=1'1\REG_OUT=1'1. Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module UTILITY. Deleting now unused module REG_FILE. Deleting now unused module true_dpram_sclk. Deleting now unused module MULT. Deleting now unused module Alg_Booth. Deleting now unused module FSM_Booth. Deleting now unused module MEMORY_INTERFACE. Deleting now unused module IRQ. Deleting now unused module Count. Deleting now unused module divM. Deleting now unused module FSM. Deleting now unused module DECO_INSTR. Deleting now unused module $paramod\FSM_Booth\BITS_BOOTH=s32'00000000000000000000000000010001. Deleting now unused module $paramod\Alg_Booth\SWORD=s32'00000000000000000000000000010010. Deleting now unused module $paramod\ALU_add\REG_ALU=1'1\REG_OUT=1'1. Deleting now unused module $paramod\ALU_sub\REG_ALU=1'1\REG_OUT=1'1. Deleting now unused module $paramod\ALU_and\REG_ALU=1'1\REG_OUT=1'1. Deleting now unused module $paramod\ALU_xor\REG_ALU=1'1\REG_OUT=1'1. Deleting now unused module $paramod\ALU_or\REG_ALU=1'1\REG_OUT=1'1. Deleting now unused module $paramod\ALU_beq\REG_ALU=1'1\REG_OUT=1'1. Deleting now unused module $paramod\ALU_blt\REG_ALU=1'1\REG_OUT=1'1. Deleting now unused module ALU. Deleting now unused module mriscvcore. <suppressed ~38 debug messages> 20.6. Executing TRIBUF pass. 20.7. Executing DEMINOUT pass (demote inout ports to input or output). 20.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~404 debug messages> 20.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 282 unused cells and 2084 unused wires. <suppressed ~357 debug messages> 20.10. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [31]: port Y[31] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[31] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [30]: port Y[30] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[30] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [29]: port Y[29] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[29] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [28]: port Y[28] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[28] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [27]: port Y[27] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[27] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [26]: port Y[26] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[26] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [25]: port Y[25] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[25] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [24]: port Y[24] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[24] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [23]: port Y[23] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[23] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [22]: port Y[22] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[22] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [21]: port Y[21] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[21] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [20]: port Y[20] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[20] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [19]: port Y[19] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[19] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [18]: port Y[18] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[18] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [17]: port Y[17] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[17] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [16]: port Y[16] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[16] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [15]: port Y[15] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[15] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [14]: port Y[14] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[14] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [13]: port Y[13] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[13] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [12]: port Y[12] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[12] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [11]: port Y[11] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[11] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [10]: port Y[10] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[10] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [9]: port Y[9] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[9] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [8]: port Y[8] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[8] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [7]: port Y[7] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[7] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [6]: port Y[6] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[6] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [5]: port Y[5] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[5] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [4]: port Y[4] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[4] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [3]: port Y[3] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[3] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [2]: port Y[2] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[2] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [1]: port Y[1] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[1] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: multiple conflicting drivers for processorci_top.\mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [0]: port Y[0] of cell $auto$tribuf.cc:165:run$5772 ($pmux) port Y[0] of cell $flatten\mriscvcore_inst.\IRQ_inst.$procmux$4363 ($pmux) Warning: Wire processorci_top.\miso is used but has no driver. Warning: Wire processorci_top.\intr is used but has no driver. Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [31] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [30] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [29] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [28] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [27] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [26] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [25] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [24] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [23] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [22] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [21] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [20] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [19] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [18] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [17] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [16] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [15] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [14] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [13] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [12] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [11] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [10] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [9] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [8] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [7] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [6] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [5] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [4] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [3] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [2] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [1] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [0] is used but has no driver. Found and reported 67 problems. 20.11. Executing OPT pass (performing simple optimizations). 20.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~29 debug messages> 20.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~1560 debug messages> Removed a total of 520 cells. 20.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $flatten\mriscvcore_inst.\FSM_inst.$procmux$4709: \mriscvcore_inst.FSM_inst.en_mem -> 1'1 Replacing known input bits on port A of cell $flatten\mriscvcore_inst.\FSM_inst.$procmux$4721: \mriscvcore_inst.FSM_inst.en_mem -> 1'1 Replacing known input bits on port A of cell $flatten\mriscvcore_inst.\MULT_inst.$procmux$2893: \mriscvcore_inst.REG_FILE_inst.MEM_FILE.q_b -> { 1'0 \mriscvcore_inst.REG_FILE_inst.MEM_FILE.q_b [30:0] } Replacing known input bits on port A of cell $flatten\mriscvcore_inst.\MULT_inst.$procmux$2884: \mriscvcore_inst.REG_FILE_inst.MEM_FILE.q_a -> { 1'0 \mriscvcore_inst.REG_FILE_inst.MEM_FILE.q_a [30:0] } Replacing known input bits on port A of cell $flatten\mriscvcore_inst.\MULT_inst.$procmux$2902: \mriscvcore_inst.REG_FILE_inst.MEM_FILE.q_a -> { 1'0 \mriscvcore_inst.REG_FILE_inst.MEM_FILE.q_a [30:0] } Analyzing evaluation results. dead port 2/2 on $mux $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4784. dead port 2/2 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dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3895. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3897. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3911. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3913. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3915. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3929. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3931. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3933. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3965. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3967. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3969. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4042. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4044. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4046. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4060. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4062. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4064. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4078. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4080. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1442. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4082. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4095. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4097. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4110. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1448. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4112. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4125. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4127. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4155. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1454. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4157. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4185. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4187. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4214. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4226. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4238. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4258. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4291. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4294. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.$procmux$2835. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.$procmux$2844. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.$procmux$2853. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.$procmux$2861. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.$procmux$2866. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.$procmux$2872. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.$procmux$2886. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.$procmux$2895. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.$procmux$2904. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1442. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1448. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u1.$procmux$3021. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u1.$procmux$3024. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u1.$procmux$3030. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u1.$procmux$3041. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u1.$procmux$3047. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u1.$procmux$3055. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1454. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u2.$procmux$2942. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u2.$procmux$2945. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u2.$procmux$2948. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u2.$procmux$2977. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u2.$procmux$2980. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u2.$procmux$2985. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u2.$procmux$2988. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u2.$procmux$2994. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u2.$procmux$3000. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u3.$procmux$5270. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u3.$procmux$5273. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u3.$procmux$5279. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u3.$procmux$5290. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u3.$procmux$5296. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u3.$procmux$5304. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u4.$procmux$5317. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u4.$procmux$5320. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u4.$procmux$5323. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u4.$procmux$5352. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u4.$procmux$5355. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u4.$procmux$5360. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u4.$procmux$5363. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u4.$procmux$5369. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u4.$procmux$5375. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u5.$procmux$3021. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u5.$procmux$3024. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u5.$procmux$3030. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u5.$procmux$3041. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u5.$procmux$3047. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u5.$procmux$3055. dead port 2/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u6.$procmux$2942. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u6.$procmux$2945. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u6.$procmux$2948. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u6.$procmux$2977. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u6.$procmux$2980. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u6.$procmux$2985. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u6.$procmux$2988. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u6.$procmux$2994. dead port 1/2 on $mux $flatten\mriscvcore_inst.\MULT_inst.\u6.$procmux$3000. dead port 1/2 on $mux $flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2759. Removed 297 multiplexer ports. <suppressed ~208 debug messages> 20.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2257: { $auto$opt_reduce.cc:137:opt_pmux$5777 $auto$opt_reduce.cc:137:opt_pmux$5775 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1778: { $flatten\Controller.\Interpreter.$procmux$1872_CMP $flatten\Controller.\Interpreter.$procmux$1868_CMP $flatten\Controller.\Interpreter.$procmux$1864_CMP $flatten\Controller.\Interpreter.$procmux$1838_CMP $flatten\Controller.\Interpreter.$procmux$1837_CMP $flatten\Controller.\Interpreter.$procmux$1833_CMP $flatten\Controller.\Interpreter.$procmux$1832_CMP $flatten\Controller.\Interpreter.$procmux$1828_CMP $flatten\Controller.\Interpreter.$procmux$1818_CMP $flatten\Controller.\Interpreter.$procmux$1814_CMP $auto$opt_reduce.cc:137:opt_pmux$5785 $flatten\Controller.\Interpreter.$procmux$1809_CMP $flatten\Controller.\Interpreter.$procmux$1808_CMP $auto$opt_reduce.cc:137:opt_pmux$5783 $flatten\Controller.\Interpreter.$procmux$1803_CMP $flatten\Controller.\Interpreter.$procmux$1802_CMP $flatten\Controller.\Interpreter.$procmux$1797_CMP $flatten\Controller.\Interpreter.$procmux$1793_CMP $flatten\Controller.\Interpreter.$procmux$1792_CMP $auto$opt_reduce.cc:137:opt_pmux$5781 $flatten\Controller.\Interpreter.$procmux$1786_CMP $flatten\Controller.\Interpreter.$procmux$1785_CMP $flatten\Controller.\Interpreter.$procmux$1784_CMP $auto$opt_reduce.cc:137:opt_pmux$5779 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2339: { $flatten\Controller.\Interpreter.$procmux$1798_CMP $auto$opt_reduce.cc:137:opt_pmux$5787 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2350: { $flatten\Controller.\Interpreter.$procmux$1939_CMP $flatten\Controller.\Interpreter.$procmux$1838_CMP $auto$opt_reduce.cc:137:opt_pmux$5789 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1878: $auto$opt_reduce.cc:137:opt_pmux$5791 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2360: { $flatten\Controller.\Interpreter.$procmux$1837_CMP $auto$opt_reduce.cc:137:opt_pmux$5795 $auto$opt_reduce.cc:137:opt_pmux$5793 } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5207: { $auto$opt_reduce.cc:137:opt_pmux$5797 $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5153_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5092_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5036_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4985_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4943_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4902_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4819_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4785_CMP } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5219: { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5153_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5092_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5036_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4985_CMP $auto$opt_reduce.cc:137:opt_pmux$5799 $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4902_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4819_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4785_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2436: { $auto$opt_reduce.cc:137:opt_pmux$5801 $flatten\Controller.\Interpreter.$procmux$1837_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2460: { $flatten\Controller.\Interpreter.$procmux$1905_CMP $flatten\Controller.\Interpreter.$procmux$1904_CMP $auto$opt_reduce.cc:137:opt_pmux$5803 } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5231: { $auto$opt_reduce.cc:137:opt_pmux$5805 $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5153_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5092_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5036_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4985_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4943_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4902_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4819_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4785_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2486: { $auto$opt_reduce.cc:137:opt_pmux$5807 $flatten\Controller.\Interpreter.$procmux$1904_CMP $flatten\Controller.\Interpreter.$procmux$1823_CMP $flatten\Controller.\Interpreter.$procmux$1818_CMP $flatten\Controller.\Interpreter.$procmux$1808_CMP } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5243: { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5153_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5092_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5036_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4985_CMP $auto$opt_reduce.cc:137:opt_pmux$5809 $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4902_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4819_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4785_CMP } Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2688: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1902: $auto$opt_reduce.cc:137:opt_pmux$5811 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1924: $auto$opt_reduce.cc:137:opt_pmux$5813 New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2556: $auto$opt_reduce.cc:137:opt_pmux$5815 New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3288: { $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:86$177_Y $auto$opt_reduce.cc:137:opt_pmux$5817 } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3296: { $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3290_CTRL $auto$opt_reduce.cc:137:opt_pmux$5819 } New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2620: $auto$opt_reduce.cc:137:opt_pmux$5821 New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3304: { $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3290_CTRL $auto$opt_reduce.cc:137:opt_pmux$5823 } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3308: { $auto$opt_reduce.cc:137:opt_pmux$5825 $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:79$170_Y } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3324: { $auto$opt_reduce.cc:137:opt_pmux$5827 $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:79$170_Y } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3328: { $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3290_CTRL $auto$opt_reduce.cc:137:opt_pmux$5829 } Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2688: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_EN[31:0]$969 [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1935: $auto$opt_reduce.cc:137:opt_pmux$5831 New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\ALU_inst.$procmux$5458: { $auto$opt_reduce.cc:137:opt_pmux$5851 $flatten\mriscvcore_inst.\ALU_inst.$procmux$5481_CMP $auto$opt_reduce.cc:137:opt_pmux$5849 $auto$opt_reduce.cc:137:opt_pmux$5847 $auto$opt_reduce.cc:137:opt_pmux$5845 $auto$opt_reduce.cc:137:opt_pmux$5843 $auto$opt_reduce.cc:137:opt_pmux$5841 $auto$opt_reduce.cc:137:opt_pmux$5839 $auto$opt_reduce.cc:137:opt_pmux$5837 $auto$opt_reduce.cc:137:opt_pmux$5835 $auto$opt_reduce.cc:137:opt_pmux$5833 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1983: $auto$opt_reduce.cc:137:opt_pmux$5853 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1439: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1439_Y New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1439_Y [0] New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1439_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1439_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1439_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1439_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1439_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1439_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1439_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1439_Y [0] } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\ALU_inst.$procmux$5485: { $auto$opt_reduce.cc:137:opt_pmux$5857 $auto$opt_reduce.cc:137:opt_pmux$5855 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2025: $auto$opt_reduce.cc:137:opt_pmux$5859 New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4206: $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3722_CMP New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2050: { $flatten\Controller.\Interpreter.$procmux$1818_CMP $auto$opt_reduce.cc:137:opt_pmux$5861 $flatten\Controller.\Interpreter.$procmux$1808_CMP } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4222: { $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3722_CMP $auto$opt_reduce.cc:137:opt_pmux$5863 } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4254: { $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3722_CMP $auto$opt_reduce.cc:137:opt_pmux$5865 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2103: { $auto$opt_reduce.cc:137:opt_pmux$5869 $auto$opt_reduce.cc:137:opt_pmux$5867 } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MULT_inst.$procmux$2907: { $auto$opt_reduce.cc:137:opt_pmux$5871 $flatten\mriscvcore_inst.\MULT_inst.$procmux$2908_CMP } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MULT_inst.$procmux$2913: $auto$opt_reduce.cc:137:opt_pmux$5873 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1439: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1439_Y New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1439_Y [0] New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1439_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1439_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1439_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1439_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1439_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1439_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1439_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1439_Y [0] } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\ALU_inst.$procmux$5512: { $auto$opt_reduce.cc:137:opt_pmux$5877 $auto$opt_reduce.cc:137:opt_pmux$5875 } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MULT_inst.\u2.$procmux$2937: { $flatten\mriscvcore_inst.\MULT_inst.\u2.$procmux$2940_CMP $flatten\mriscvcore_inst.\MULT_inst.\u2.$procmux$2939_CMP $auto$opt_reduce.cc:137:opt_pmux$5879 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2172: $auto$opt_reduce.cc:137:opt_pmux$5881 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2197: { $flatten\Controller.\Interpreter.$procmux$1818_CMP $auto$opt_reduce.cc:137:opt_pmux$5883 $flatten\Controller.\Interpreter.$procmux$1808_CMP } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MULT_inst.\u4.$procmux$5312: { $flatten\mriscvcore_inst.\MULT_inst.\u4.$procmux$5315_CMP $flatten\mriscvcore_inst.\MULT_inst.\u4.$procmux$5314_CMP $auto$opt_reduce.cc:137:opt_pmux$5885 } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\ALU_inst.$procmux$5539: { $auto$opt_reduce.cc:137:opt_pmux$5889 $auto$opt_reduce.cc:137:opt_pmux$5887 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2225: { $flatten\Controller.\Interpreter.$procmux$1804_CMP $flatten\Controller.\Interpreter.$procmux$1797_CMP $flatten\Controller.\Interpreter.$procmux$1786_CMP $flatten\Controller.\Interpreter.$procmux$1780_CMP $auto$opt_reduce.cc:137:opt_pmux$5891 } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MULT_inst.\u6.$procmux$2937: { $flatten\mriscvcore_inst.\MULT_inst.\u6.$procmux$2940_CMP $flatten\mriscvcore_inst.\MULT_inst.\u6.$procmux$2939_CMP $auto$opt_reduce.cc:137:opt_pmux$5893 } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$procmux$2823: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 New ports: A=1'0, B=1'1, Y=$flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] New connections: $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [31:1] = { $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$0$memwr$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:32$295_EN[31:0]$299 [0] } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2774: { $flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2779_CMP $auto$opt_reduce.cc:137:opt_pmux$5895 $flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2776_CMP $flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2775_CMP } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2781: $auto$opt_reduce.cc:137:opt_pmux$5897 New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2788: $auto$opt_reduce.cc:137:opt_pmux$5899 New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$5804: { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5217_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5216_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$5808: { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5217_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5216_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4943_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$5796: { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5217_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5216_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$5798: { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5217_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5216_CMP $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4943_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$5816: { $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3290_CMP $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:79$170_Y } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$5824: { $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3290_CMP $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:86$177_Y } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$5826: { $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3290_CMP $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:86$177_Y } Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1457: Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1169, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1439_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1457: Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1169, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1439_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_EN[7:0]$1160 [0] } Optimizing cells in module \processorci_top. Performed a total of 68 changes. 20.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~114 debug messages> Removed a total of 38 cells. 20.11.6. Executing OPT_DFF pass (perform DFF optimizations). 20.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [31] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [30] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [29] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [28] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [27] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [26] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [25] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [24] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [23] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [22] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [21] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [20] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [19] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [18] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [17] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [16] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [15] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [14] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [13] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [12] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [11] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [10] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [9] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [8] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [7] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [6] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [5] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [4] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [3] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [2] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [1] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Warning: Driver-driver conflict for \mriscvcore_inst.REG_FILE_inst.MEM_FILE.data_a [0] between cell $auto$tribuf.cc:165:run$5772.Y and constant 1'z in processorci_top: Resolved using constant. Removed 222 unused cells and 1150 unused wires. <suppressed ~344 debug messages> 20.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~15 debug messages> 20.11.9. Rerunning OPT passes. (Maybe there is more to do..) 20.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\mriscvcore_inst.\FSM_inst.$procmux$4602. dead port 2/2 on $mux $flatten\mriscvcore_inst.\FSM_inst.$procmux$4625. dead port 2/2 on $mux $flatten\mriscvcore_inst.\FSM_inst.$procmux$4667. dead port 2/2 on $mux $flatten\mriscvcore_inst.\FSM_inst.$procmux$4709. dead port 2/2 on $mux $flatten\mriscvcore_inst.\FSM_inst.$procmux$4742. Removed 5 multiplexer ports. <suppressed ~162 debug messages> 20.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2050: { $auto$opt_reduce.cc:137:opt_pmux$5861 $auto$opt_reduce.cc:137:opt_pmux$5901 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2197: { $auto$opt_reduce.cc:137:opt_pmux$5861 $auto$opt_reduce.cc:137:opt_pmux$5903 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2486: { $auto$opt_reduce.cc:137:opt_pmux$5807 $flatten\Controller.\Interpreter.$procmux$1904_CMP $flatten\Controller.\Interpreter.$procmux$1823_CMP $auto$opt_reduce.cc:137:opt_pmux$5905 } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\FSM_inst.$procmux$4707: { $auto$opt_reduce.cc:137:opt_pmux$5909 $auto$opt_reduce.cc:137:opt_pmux$5907 } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\FSM_inst.$procmux$4740: { $flatten\mriscvcore_inst.\FSM_inst.$procmux$4633_CMP $flatten\mriscvcore_inst.\FSM_inst.$procmux$4610_CMP $auto$opt_reduce.cc:137:opt_pmux$5911 } New ctrl vector for $pmux cell $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3292: { $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3290_CTRL $auto$opt_reduce.cc:137:opt_pmux$5913 } Optimizing cells in module \processorci_top. Performed a total of 6 changes. 20.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~12 debug messages> Removed a total of 4 cells. 20.11.13. Executing OPT_DFF pass (perform DFF optimizations). 20.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 22 unused wires. <suppressed ~1 debug messages> 20.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.11.16. Rerunning OPT passes. (Maybe there is more to do..) 20.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~161 debug messages> 20.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 20.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.11.20. Executing OPT_DFF pass (perform DFF optimizations). 20.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 20.11.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.11.23. Finished OPT passes. (There is nothing left to do.) 20.12. Executing FSM pass (extract and optimize FSM). 20.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking processorci_top.Controller.Interpreter.return_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state. Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking processorci_top.Controller.Uart.state_read as FSM state register: Register has an initialization value. Not marking processorci_top.Controller.Uart.state_write as FSM state register: Register has an initialization value. Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state. Not marking processorci_top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. Found FSM state register processorci_top.mriscvcore_inst.FSM_inst.state. Not marking processorci_top.mriscvcore_inst.IRQ_inst.pc_c_q as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.mriscvcore_inst.MEMORY_INTERFACE_inst.state. Found FSM state register processorci_top.mriscvcore_inst.MULT_inst.u1.state. Found FSM state register processorci_top.mriscvcore_inst.MULT_inst.u3.state. Found FSM state register processorci_top.mriscvcore_inst.MULT_inst.u5.state. 20.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$5588 root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1316_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1329_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1342_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1328_Y found state code: 3'000 found ctrl input: \Controller.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \Controller.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1342_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1333_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1329_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1328_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1316_Y ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done } ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1316_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1328_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1329_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1333_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1342_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'00-- -> 3'001 8'01010001 transition: 3'000 4'01-- -> 3'000 8'01010000 transition: 3'000 4'1--- -> 3'000 8'01010000 transition: 3'010 4'0--0 -> 3'010 8'00100010 transition: 3'010 4'0--1 -> 3'011 8'00100011 transition: 3'010 4'1--- -> 3'000 8'00100000 transition: 3'001 4'0-0- -> 3'001 8'00011001 transition: 3'001 4'0-1- -> 3'010 8'00011010 transition: 3'001 4'1--- -> 3'000 8'00011000 transition: 3'011 4'0-0- -> 3'011 8'10010011 transition: 3'011 4'0-1- -> 3'000 8'10010000 transition: 3'011 4'1--- -> 3'000 8'10010000 Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Controller.\Uart.$procdff$5635 root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\Controller.\Uart.$procmux$2517_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2512_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2519_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2506_CMP found state code: 2'00 found state code: 2'11 found state code: 2'10 found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1202_Y found state code: 2'01 found ctrl output: $flatten\Controller.\Uart.$procmux$2506_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2512_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2517_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2519_CMP ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1202_Y } ctrl outputs: { $flatten\Controller.\Uart.$procmux$2519_CMP $flatten\Controller.\Uart.$procmux$2517_CMP $flatten\Controller.\Uart.$procmux$2512_CMP $flatten\Controller.\Uart.$procmux$2506_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] } transition: 2'00 2'00 -> 2'00 6'000100 transition: 2'00 2'01 -> 2'01 6'000101 transition: 2'00 2'1- -> 2'00 6'000100 transition: 2'10 2'0- -> 2'11 6'001011 transition: 2'10 2'1- -> 2'00 6'001000 transition: 2'01 2'0- -> 2'10 6'100010 transition: 2'01 2'1- -> 2'00 6'100000 transition: 2'11 2'0- -> 2'00 6'010000 transition: 2'11 2'1- -> 2'00 6'010000 Extracting FSM `\mriscvcore_inst.FSM_inst.state' from module `\processorci_top'. found $dff cell for state register: $flatten\mriscvcore_inst.\FSM_inst.$procdff$5712 root of input selection tree: $flatten\mriscvcore_inst.\FSM_inst.$0\state[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: \mriscvcore_inst.FSM_inst.aligned_mem found state code: 4'0100 found ctrl input: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4597_CMP found ctrl input: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4601_CMP found ctrl input: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4610_CMP found ctrl input: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4617_CMP found ctrl input: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4621_CMP found ctrl input: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4624_CMP found ctrl input: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4633_CMP found state code: 4'0000 found ctrl input: \mriscvcore_inst.FSM_inst.en_mem found ctrl input: \mriscvcore_inst.FSM_inst.is_mem found ctrl input: \mriscvcore_inst.FSM_inst.done_exec found state code: 4'0010 found state code: 4'0011 found ctrl input: \mriscvcore_inst.FSM_inst.is_illisn found state code: 4'0001 found ctrl output: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4597_CMP found ctrl output: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4601_CMP found ctrl output: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4610_CMP found ctrl output: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4617_CMP found ctrl output: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4621_CMP found ctrl output: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4624_CMP found ctrl output: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4633_CMP ctrl inputs: { \mriscvcore_inst.FSM_inst.is_illisn \mriscvcore_inst.FSM_inst.is_mem \mriscvcore_inst.FSM_inst.en_mem \mriscvcore_inst.FSM_inst.done_exec \mriscvcore_inst.FSM_inst.aligned_mem \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\mriscvcore_inst.\FSM_inst.$procmux$4633_CMP $flatten\mriscvcore_inst.\FSM_inst.$procmux$4624_CMP $flatten\mriscvcore_inst.\FSM_inst.$procmux$4621_CMP $flatten\mriscvcore_inst.\FSM_inst.$procmux$4617_CMP $flatten\mriscvcore_inst.\FSM_inst.$procmux$4610_CMP $flatten\mriscvcore_inst.\FSM_inst.$procmux$4601_CMP $flatten\mriscvcore_inst.\FSM_inst.$procmux$4597_CMP $flatten\mriscvcore_inst.\FSM_inst.$0\state[3:0] } transition: 4'0000 6'----00 -> 4'0100 11'10000000100 transition: 4'0000 6'--0-10 -> 4'0000 11'10000000000 transition: 4'0000 6'--1-10 -> 4'0001 11'10000000001 transition: 4'0000 6'-----1 -> 4'0000 11'10000000000 transition: 4'0100 6'----00 -> 4'0100 11'00000010100 transition: 4'0100 6'----10 -> 4'0100 11'00000010100 transition: 4'0100 6'-----1 -> 4'0000 11'00000010000 transition: 4'0010 6'----00 -> 4'0100 11'00010000100 transition: 4'0010 6'-0-010 -> 4'0010 11'00010000010 transition: 4'0010 6'-0-110 -> 4'0000 11'00010000000 transition: 4'0010 6'-1--10 -> 4'0011 11'00010000011 transition: 4'0010 6'-----1 -> 4'0000 11'00010000000 transition: 4'0001 6'----00 -> 4'0100 11'00100000100 transition: 4'0001 6'0---10 -> 4'0010 11'00100000010 transition: 4'0001 6'1---10 -> 4'0100 11'00100000100 transition: 4'0001 6'-----1 -> 4'0000 11'00100000000 transition: 4'0011 6'----00 -> 4'0100 11'00001000100 transition: 4'0011 6'--0-10 -> 4'0011 11'00001000011 transition: 4'0011 6'--1-10 -> 4'0000 11'00001000000 transition: 4'0011 6'-----1 -> 4'0000 11'00001000000 Extracting FSM `\mriscvcore_inst.MEMORY_INTERFACE_inst.state' from module `\processorci_top'. found $dff cell for state register: $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procdff$5682 root of input selection tree: $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$0\state[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3722_CMP found state code: 4'0000 found ctrl input: $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$logic_and$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:79$173_Y found ctrl input: $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$logic_and$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:86$179_Y fsm extraction failed: at least two states are required. Extracting FSM `\mriscvcore_inst.MULT_inst.u1.state' from module `\processorci_top'. found $dff cell for state register: $flatten\mriscvcore_inst.\MULT_inst.\u1.$procdff$5677 root of input selection tree: $flatten\mriscvcore_inst.\MULT_inst.\u1.$0\state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.\u1.$procmux$3042_CMP found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.\u1.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:42$239_Y found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.\u1.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:41$238_Y found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.\u1.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:40$237_Y found ctrl input: \mriscvcore_inst.MULT_inst.u1.Enable found state code: 2'00 found state code: 2'11 found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:227$279_Y found state code: 2'10 found state code: 2'01 found ctrl output: $flatten\mriscvcore_inst.\MULT_inst.\u1.$procmux$3042_CMP found ctrl output: $flatten\mriscvcore_inst.\MULT_inst.\u1.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:42$239_Y found ctrl output: $flatten\mriscvcore_inst.\MULT_inst.\u1.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:41$238_Y found ctrl output: $flatten\mriscvcore_inst.\MULT_inst.\u1.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:40$237_Y ctrl inputs: { \mriscvcore_inst.MULT_inst.u1.Enable $flatten\mriscvcore_inst.\MULT_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:227$279_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\mriscvcore_inst.\MULT_inst.\u1.$0\state[1:0] $flatten\mriscvcore_inst.\MULT_inst.\u1.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:40$237_Y $flatten\mriscvcore_inst.\MULT_inst.\u1.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:41$238_Y $flatten\mriscvcore_inst.\MULT_inst.\u1.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:42$239_Y $flatten\mriscvcore_inst.\MULT_inst.\u1.$procmux$3042_CMP } transition: 2'00 3'0-0 -> 2'00 6'001000 transition: 2'00 3'1-0 -> 2'01 6'011000 transition: 2'00 3'--1 -> 2'00 6'001000 transition: 2'10 3'-00 -> 2'10 6'100010 transition: 2'10 3'-10 -> 2'11 6'110010 transition: 2'10 3'--1 -> 2'00 6'000010 transition: 2'01 3'--0 -> 2'10 6'100100 transition: 2'01 3'--1 -> 2'00 6'000100 transition: 2'11 3'0-0 -> 2'00 6'000001 transition: 2'11 3'1-0 -> 2'11 6'110001 transition: 2'11 3'--1 -> 2'00 6'000001 Extracting FSM `\mriscvcore_inst.MULT_inst.u3.state' from module `\processorci_top'. found $dff cell for state register: $flatten\mriscvcore_inst.\MULT_inst.\u3.$procdff$5716 root of input selection tree: $flatten\mriscvcore_inst.\MULT_inst.\u3.$0\state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.\u3.$procmux$5291_CMP found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.\u3.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:42$903_Y found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.\u3.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:41$902_Y found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.\u3.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:40$901_Y found ctrl input: \mriscvcore_inst.MULT_inst.u1.Enable found state code: 2'00 found state code: 2'11 found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:231$285_Y found state code: 2'10 found state code: 2'01 found ctrl output: $flatten\mriscvcore_inst.\MULT_inst.\u3.$procmux$5291_CMP found ctrl output: $flatten\mriscvcore_inst.\MULT_inst.\u3.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:42$903_Y found ctrl output: $flatten\mriscvcore_inst.\MULT_inst.\u3.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:41$902_Y found ctrl output: $flatten\mriscvcore_inst.\MULT_inst.\u3.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:40$901_Y ctrl inputs: { \mriscvcore_inst.MULT_inst.u1.Enable $flatten\mriscvcore_inst.\MULT_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:231$285_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\mriscvcore_inst.\MULT_inst.\u3.$0\state[1:0] $flatten\mriscvcore_inst.\MULT_inst.\u3.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:40$901_Y $flatten\mriscvcore_inst.\MULT_inst.\u3.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:41$902_Y $flatten\mriscvcore_inst.\MULT_inst.\u3.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:42$903_Y $flatten\mriscvcore_inst.\MULT_inst.\u3.$procmux$5291_CMP } transition: 2'00 3'0-0 -> 2'00 6'001000 transition: 2'00 3'1-0 -> 2'01 6'011000 transition: 2'00 3'--1 -> 2'00 6'001000 transition: 2'10 3'-00 -> 2'10 6'100010 transition: 2'10 3'-10 -> 2'11 6'110010 transition: 2'10 3'--1 -> 2'00 6'000010 transition: 2'01 3'--0 -> 2'10 6'100100 transition: 2'01 3'--1 -> 2'00 6'000100 transition: 2'11 3'0-0 -> 2'00 6'000001 transition: 2'11 3'1-0 -> 2'11 6'110001 transition: 2'11 3'--1 -> 2'00 6'000001 Extracting FSM `\mriscvcore_inst.MULT_inst.u5.state' from module `\processorci_top'. found $dff cell for state register: $flatten\mriscvcore_inst.\MULT_inst.\u5.$procdff$5677 root of input selection tree: $flatten\mriscvcore_inst.\MULT_inst.\u5.$0\state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.\u5.$procmux$3042_CMP found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.\u5.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:42$239_Y found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.\u5.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:41$238_Y found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.\u5.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:40$237_Y found ctrl input: \mriscvcore_inst.MULT_inst.u1.Enable found state code: 2'00 found state code: 2'11 found ctrl input: $flatten\mriscvcore_inst.\MULT_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:235$291_Y found state code: 2'10 found state code: 2'01 found ctrl output: $flatten\mriscvcore_inst.\MULT_inst.\u5.$procmux$3042_CMP found ctrl output: $flatten\mriscvcore_inst.\MULT_inst.\u5.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:42$239_Y found ctrl output: $flatten\mriscvcore_inst.\MULT_inst.\u5.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:41$238_Y found ctrl output: $flatten\mriscvcore_inst.\MULT_inst.\u5.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:40$237_Y ctrl inputs: { \mriscvcore_inst.MULT_inst.u1.Enable $flatten\mriscvcore_inst.\MULT_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:235$291_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\mriscvcore_inst.\MULT_inst.\u5.$0\state[1:0] $flatten\mriscvcore_inst.\MULT_inst.\u5.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:40$237_Y $flatten\mriscvcore_inst.\MULT_inst.\u5.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:41$238_Y $flatten\mriscvcore_inst.\MULT_inst.\u5.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:42$239_Y $flatten\mriscvcore_inst.\MULT_inst.\u5.$procmux$3042_CMP } transition: 2'00 3'0-0 -> 2'00 6'001000 transition: 2'00 3'1-0 -> 2'01 6'011000 transition: 2'00 3'--1 -> 2'00 6'001000 transition: 2'10 3'-00 -> 2'10 6'100010 transition: 2'10 3'-10 -> 2'11 6'110010 transition: 2'10 3'--1 -> 2'00 6'000010 transition: 2'01 3'--0 -> 2'10 6'100100 transition: 2'01 3'--1 -> 2'00 6'000100 transition: 2'11 3'0-0 -> 2'00 6'000001 transition: 2'11 3'1-0 -> 2'11 6'110001 transition: 2'11 3'--1 -> 2'00 6'000001 20.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\mriscvcore_inst.MULT_inst.u5.state$5948' from module `\processorci_top'. Optimizing FSM `$fsm$\mriscvcore_inst.MULT_inst.u3.state$5942' from module `\processorci_top'. Optimizing FSM `$fsm$\mriscvcore_inst.MULT_inst.u1.state$5936' from module `\processorci_top'. Optimizing FSM `$fsm$\mriscvcore_inst.FSM_inst.state$5927' from module `\processorci_top'. Merging pattern 6'----00 and 6'----10 from group (1 1 11'00000010100). Merging pattern 6'----10 and 6'----00 from group (1 1 11'00000010100). Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5921' from module `\processorci_top'. Merging pattern 2'0- and 2'1- from group (3 0 6'010000). Merging pattern 2'1- and 2'0- from group (3 0 6'010000). Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5914' from module `\processorci_top'. 20.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 57 unused cells and 57 unused wires. <suppressed ~61 debug messages> 20.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5914' from module `\processorci_top'. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5921' from module `\processorci_top'. Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0]. Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1]. Removing unused output signal $flatten\Controller.\Uart.$procmux$2517_CMP. Removing unused output signal $flatten\Controller.\Uart.$procmux$2519_CMP. Optimizing FSM `$fsm$\mriscvcore_inst.FSM_inst.state$5927' from module `\processorci_top'. Removing unused output signal $flatten\mriscvcore_inst.\FSM_inst.$0\state[3:0] [0]. Removing unused output signal $flatten\mriscvcore_inst.\FSM_inst.$0\state[3:0] [1]. Removing unused output signal $flatten\mriscvcore_inst.\FSM_inst.$0\state[3:0] [2]. Removing unused output signal $flatten\mriscvcore_inst.\FSM_inst.$0\state[3:0] [3]. Removing unused output signal $flatten\mriscvcore_inst.\FSM_inst.$procmux$4597_CMP. Optimizing FSM `$fsm$\mriscvcore_inst.MULT_inst.u1.state$5936' from module `\processorci_top'. Removing unused output signal $flatten\mriscvcore_inst.\MULT_inst.\u1.$procmux$3042_CMP. Removing unused output signal $flatten\mriscvcore_inst.\MULT_inst.\u1.$0\state[1:0] [0]. Removing unused output signal $flatten\mriscvcore_inst.\MULT_inst.\u1.$0\state[1:0] [1]. Optimizing FSM `$fsm$\mriscvcore_inst.MULT_inst.u3.state$5942' from module `\processorci_top'. Removing unused output signal $flatten\mriscvcore_inst.\MULT_inst.\u3.$procmux$5291_CMP. Removing unused output signal $flatten\mriscvcore_inst.\MULT_inst.\u3.$0\state[1:0] [0]. Removing unused output signal $flatten\mriscvcore_inst.\MULT_inst.\u3.$0\state[1:0] [1]. Optimizing FSM `$fsm$\mriscvcore_inst.MULT_inst.u5.state$5948' from module `\processorci_top'. Removing unused output signal $flatten\mriscvcore_inst.\MULT_inst.\u5.$procmux$3042_CMP. Removing unused output signal $flatten\mriscvcore_inst.\MULT_inst.\u5.$0\state[1:0] [0]. Removing unused output signal $flatten\mriscvcore_inst.\MULT_inst.\u5.$0\state[1:0] [1]. 20.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5914' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5921' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- Recoding FSM `$fsm$\mriscvcore_inst.FSM_inst.state$5927' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> ----1 0100 -> ---1- 0010 -> --1-- 0001 -> -1--- 0011 -> 1---- Recoding FSM `$fsm$\mriscvcore_inst.MULT_inst.u1.state$5936' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- Recoding FSM `$fsm$\mriscvcore_inst.MULT_inst.u3.state$5942' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- Recoding FSM `$fsm$\mriscvcore_inst.MULT_inst.u5.state$5948' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- 20.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5914' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$5914 (\Controller.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \Controller.Uart.i_uart_rx.payload_done 1: \Controller.Uart.i_uart_rx.next_bit 2: \Controller.Uart.i_uart_rx.rxd_reg 3: \ResetBootSystem.reset_o Output signals: 0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1342_Y 1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1333_Y 2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1329_Y 3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1328_Y 4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1316_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'01-- -> 0 5'01010 1: 0 4'1--- -> 0 5'01010 2: 0 4'00-- -> 2 5'01010 3: 1 4'1--- -> 0 5'00100 4: 1 4'0--0 -> 1 5'00100 5: 1 4'0--1 -> 3 5'00100 6: 2 4'1--- -> 0 5'00011 7: 2 4'0-1- -> 1 5'00011 8: 2 4'0-0- -> 2 5'00011 9: 3 4'0-1- -> 0 5'10010 10: 3 4'1--- -> 0 5'10010 11: 3 4'0-0- -> 3 5'10010 ------------------------------------- FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5921' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$5921 (\Controller.Uart.tx_fifo_read_state): Number of input signals: 2 Number of output signals: 2 Number of state bits: 4 Input signals: 0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1202_Y 1: \ResetBootSystem.reset_o Output signals: 0: $flatten\Controller.\Uart.$procmux$2506_CMP 1: $flatten\Controller.\Uart.$procmux$2512_CMP State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 2'00 -> 0 2'01 1: 0 2'1- -> 0 2'01 2: 0 2'01 -> 2 2'01 3: 1 2'1- -> 0 2'10 4: 1 2'0- -> 3 2'10 5: 2 2'1- -> 0 2'00 6: 2 2'0- -> 1 2'00 7: 3 2'-- -> 0 2'00 ------------------------------------- FSM `$fsm$\mriscvcore_inst.FSM_inst.state$5927' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\mriscvcore_inst.FSM_inst.state$5927 (\mriscvcore_inst.FSM_inst.state): Number of input signals: 6 Number of output signals: 6 Number of state bits: 5 Input signals: 0: \Controller.Interpreter.core_reset 1: \mriscvcore_inst.FSM_inst.aligned_mem 2: \mriscvcore_inst.FSM_inst.done_exec 3: \mriscvcore_inst.FSM_inst.en_mem 4: \mriscvcore_inst.FSM_inst.is_mem 5: \mriscvcore_inst.FSM_inst.is_illisn Output signals: 0: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4601_CMP 1: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4610_CMP 2: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4617_CMP 3: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4621_CMP 4: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4624_CMP 5: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4633_CMP State encoding: 0: 5'----1 <RESET STATE> 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 6'--0-10 -> 0 6'100000 1: 0 6'-----1 -> 0 6'100000 2: 0 6'----00 -> 1 6'100000 3: 0 6'--1-10 -> 3 6'100000 4: 1 6'-----1 -> 0 6'000000 5: 1 6'-----0 -> 1 6'000000 6: 2 6'-0-110 -> 0 6'000100 7: 2 6'-----1 -> 0 6'000100 8: 2 6'----00 -> 1 6'000100 9: 2 6'-0-010 -> 2 6'000100 10: 2 6'-1--10 -> 4 6'000100 11: 3 6'-----1 -> 0 6'001000 12: 3 6'----00 -> 1 6'001000 13: 3 6'1---10 -> 1 6'001000 14: 3 6'0---10 -> 2 6'001000 15: 4 6'--1-10 -> 0 6'000010 16: 4 6'-----1 -> 0 6'000010 17: 4 6'----00 -> 1 6'000010 18: 4 6'--0-10 -> 4 6'000010 ------------------------------------- FSM `$fsm$\mriscvcore_inst.MULT_inst.u1.state$5936' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\mriscvcore_inst.MULT_inst.u1.state$5936 (\mriscvcore_inst.MULT_inst.u1.state): Number of input signals: 3 Number of output signals: 3 Number of state bits: 4 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\mriscvcore_inst.\MULT_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:227$279_Y 2: \mriscvcore_inst.MULT_inst.u1.Enable Output signals: 0: $flatten\mriscvcore_inst.\MULT_inst.\u1.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:42$239_Y 1: $flatten\mriscvcore_inst.\MULT_inst.\u1.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:41$238_Y 2: $flatten\mriscvcore_inst.\MULT_inst.\u1.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:40$237_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 3'0-0 -> 0 3'100 1: 0 3'--1 -> 0 3'100 2: 0 3'1-0 -> 2 3'100 3: 1 3'--1 -> 0 3'001 4: 1 3'-00 -> 1 3'001 5: 1 3'-10 -> 3 3'001 6: 2 3'--1 -> 0 3'010 7: 2 3'--0 -> 1 3'010 8: 3 3'0-0 -> 0 3'000 9: 3 3'--1 -> 0 3'000 10: 3 3'1-0 -> 3 3'000 ------------------------------------- FSM `$fsm$\mriscvcore_inst.MULT_inst.u3.state$5942' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\mriscvcore_inst.MULT_inst.u3.state$5942 (\mriscvcore_inst.MULT_inst.u3.state): Number of input signals: 3 Number of output signals: 3 Number of state bits: 4 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\mriscvcore_inst.\MULT_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:231$285_Y 2: \mriscvcore_inst.MULT_inst.u1.Enable Output signals: 0: $flatten\mriscvcore_inst.\MULT_inst.\u3.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:42$903_Y 1: $flatten\mriscvcore_inst.\MULT_inst.\u3.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:41$902_Y 2: $flatten\mriscvcore_inst.\MULT_inst.\u3.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:40$901_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 3'0-0 -> 0 3'100 1: 0 3'--1 -> 0 3'100 2: 0 3'1-0 -> 2 3'100 3: 1 3'--1 -> 0 3'001 4: 1 3'-00 -> 1 3'001 5: 1 3'-10 -> 3 3'001 6: 2 3'--1 -> 0 3'010 7: 2 3'--0 -> 1 3'010 8: 3 3'0-0 -> 0 3'000 9: 3 3'--1 -> 0 3'000 10: 3 3'1-0 -> 3 3'000 ------------------------------------- FSM `$fsm$\mriscvcore_inst.MULT_inst.u5.state$5948' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\mriscvcore_inst.MULT_inst.u5.state$5948 (\mriscvcore_inst.MULT_inst.u5.state): Number of input signals: 3 Number of output signals: 3 Number of state bits: 4 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\mriscvcore_inst.\MULT_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:235$291_Y 2: \mriscvcore_inst.MULT_inst.u1.Enable Output signals: 0: $flatten\mriscvcore_inst.\MULT_inst.\u5.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:42$239_Y 1: $flatten\mriscvcore_inst.\MULT_inst.\u5.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:41$238_Y 2: $flatten\mriscvcore_inst.\MULT_inst.\u5.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:40$237_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 3'0-0 -> 0 3'100 1: 0 3'--1 -> 0 3'100 2: 0 3'1-0 -> 2 3'100 3: 1 3'--1 -> 0 3'001 4: 1 3'-00 -> 1 3'001 5: 1 3'-10 -> 3 3'001 6: 2 3'--1 -> 0 3'010 7: 2 3'--0 -> 1 3'010 8: 3 3'0-0 -> 0 3'000 9: 3 3'--1 -> 0 3'000 10: 3 3'1-0 -> 3 3'000 ------------------------------------- 20.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5914' from module `\processorci_top'. Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5921' from module `\processorci_top'. Mapping FSM `$fsm$\mriscvcore_inst.FSM_inst.state$5927' from module `\processorci_top'. Mapping FSM `$fsm$\mriscvcore_inst.MULT_inst.u1.state$5936' from module `\processorci_top'. Mapping FSM `$fsm$\mriscvcore_inst.MULT_inst.u3.state$5942' from module `\processorci_top'. Mapping FSM `$fsm$\mriscvcore_inst.MULT_inst.u5.state$5948' from module `\processorci_top'. 20.13. Executing OPT pass (performing simple optimizations). 20.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~25 debug messages> 20.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~45 debug messages> Removed a total of 15 cells. 20.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/3 on $pmux $flatten\mriscvcore_inst.\FSM_inst.$procmux$4665. dead port 1/3 on $pmux $flatten\mriscvcore_inst.\FSM_inst.$procmux$4707. dead port 1/4 on $pmux $flatten\mriscvcore_inst.\FSM_inst.$procmux$4740. Removed 3 multiplexer ports. <suppressed ~153 debug messages> 20.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 20.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\mriscvcore_inst.\UTILITY_inst.$procdff$5659 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2748_Y, Q = \mriscvcore_inst.UTILITY_inst.PC_N2, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6177 ($sdff) from module processorci_top (D = \mriscvcore_inst.UTILITY_inst.PC_N, Q = \mriscvcore_inst.UTILITY_inst.PC_N2). Adding SRST signal on $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$procdff$5665 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$memrd$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:35$306_DATA, Q = \mriscvcore_inst.REG_FILE_inst.MEM_FILE.q_b, rval = 0). Adding SRST signal on $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$procdff$5664 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\REG_FILE_inst.\MEM_FILE.$memrd$\ram$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:34$303_DATA, Q = \mriscvcore_inst.REG_FILE_inst.MEM_FILE.q_a, rval = 0). Adding SRST signal on $flatten\mriscvcore_inst.\MULT_inst.$procdff$5671 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\MULT_inst.$2\cont1[4:0], Q = \mriscvcore_inst.MULT_inst.cont1, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$6181 ($sdff) from module processorci_top (D = $flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:228$282_Y [4:0], Q = \mriscvcore_inst.MULT_inst.cont1). Adding SRST signal on $flatten\mriscvcore_inst.\MULT_inst.$procdff$5670 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\MULT_inst.$2\cont2[4:0], Q = \mriscvcore_inst.MULT_inst.cont2, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$6183 ($sdff) from module processorci_top (D = $flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:232$288_Y [4:0], Q = \mriscvcore_inst.MULT_inst.cont2). Adding SRST signal on $flatten\mriscvcore_inst.\MULT_inst.$procdff$5669 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\MULT_inst.$2\cont3[4:0], Q = \mriscvcore_inst.MULT_inst.cont3, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$6185 ($sdff) from module processorci_top (D = $flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:236$294_Y [4:0], Q = \mriscvcore_inst.MULT_inst.cont3). Adding SRST signal on $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procdff$5682 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$3\nexstate[3:0], Q = \mriscvcore_inst.MEMORY_INTERFACE_inst.state, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6187 ($sdff) from module processorci_top (D = 4'0000, Q = \mriscvcore_inst.MEMORY_INTERFACE_inst.state). Adding SRST signal on $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procdff$5680 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3073_Y, Q = \mriscvcore_inst.MEMORY_INTERFACE_inst.inst, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6199 ($sdff) from module processorci_top (D = \mriscvcore_inst.MEMORY_INTERFACE_inst.Rdata_mem, Q = \mriscvcore_inst.MEMORY_INTERFACE_inst.inst). Adding SRST signal on $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procdff$5678 ($dff) from module processorci_top (D = \mriscvcore_inst.MEMORY_INTERFACE_inst.Wdataq, Q = \mriscvcore_inst.MEMORY_INTERFACE_inst.Wdata, rval = 0). Adding EN signal on $flatten\mriscvcore_inst.\IRQ_inst.$procdff$5683 ($dff) from module processorci_top (D = 0, Q = \mriscvcore_inst.IRQ_inst.pc_c_q). Adding SRST signal on $flatten\mriscvcore_inst.\FSM_inst.$procdff$5713 ($dff) from module processorci_top (D = \mriscvcore_inst.FSM_inst.enable_pc_fsm, Q = \mriscvcore_inst.FSM_inst.enable_pc_aux, rval = 1'0). Adding SRST signal on $flatten\mriscvcore_inst.\FSM_inst.$procdff$5711 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\FSM_inst.$procmux$4656_Y, Q = \mriscvcore_inst.FSM_inst.enable_pc_fsm, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6204 ($sdff) from module processorci_top (D = $flatten\mriscvcore_inst.\FSM_inst.$procmux$4649_Y, Q = \mriscvcore_inst.FSM_inst.enable_pc_fsm). Adding SRST signal on $flatten\mriscvcore_inst.\FSM_inst.$procdff$5710 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\FSM_inst.$procmux$4677_Y, Q = \mriscvcore_inst.FSM_inst.enable_exec_mem, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6214 ($sdff) from module processorci_top (D = $flatten\mriscvcore_inst.\FSM_inst.$procmux$4673_Y, Q = \mriscvcore_inst.FSM_inst.enable_exec_mem). Adding SRST signal on $flatten\mriscvcore_inst.\FSM_inst.$procdff$5709 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\FSM_inst.$procmux$4698_Y, Q = \mriscvcore_inst.FSM_inst.enable_exec, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6218 ($sdff) from module processorci_top (D = $flatten\mriscvcore_inst.\FSM_inst.$procmux$4691_Y, Q = \mriscvcore_inst.FSM_inst.enable_exec). Adding SRST signal on $flatten\mriscvcore_inst.\FSM_inst.$procdff$5708 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\FSM_inst.$procmux$4731_Y, Q = \mriscvcore_inst.FSM_inst.en_mem, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6228 ($sdff) from module processorci_top (D = $flatten\mriscvcore_inst.\FSM_inst.$procmux$4715_Y, Q = \mriscvcore_inst.FSM_inst.en_mem). Adding SRST signal on $flatten\mriscvcore_inst.\FSM_inst.$procdff$5707 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\FSM_inst.$procmux$4764_Y, Q = \mriscvcore_inst.FSM_inst.W_R_mem, rval = 2'00). Adding EN signal on $auto$ff.cc:266:slice$6232 ($sdff) from module processorci_top (D = $flatten\mriscvcore_inst.\FSM_inst.$procmux$4740_Y, Q = \mriscvcore_inst.FSM_inst.W_R_mem). Adding SRST signal on $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$procdff$5572 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$procmux$1360_Y, Q = \mriscvcore_inst.ALU_inst.ALU_sXXx_inst.count, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$6238 ($sdff) from module processorci_top (D = $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$procmux$1360_Y, Q = \mriscvcore_inst.ALU_inst.ALU_sXXx_inst.count). Adding SRST signal on $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$procdff$5568 ($dff) from module processorci_top (D = $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$procmux$1408_Y, Q = \mriscvcore_inst.ALU_inst.ALU_sXXx_inst.sl_ok, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6242 ($sdff) from module processorci_top (D = 1'1, Q = \mriscvcore_inst.ALU_inst.ALU_sXXx_inst.sl_ok). Adding SRST signal on $flatten\mriscvcore_inst.\ALU_inst.$procdff$5730 ($dff) from module processorci_top (D = \mriscvcore_inst.FSM_inst.enable_exec, Q = \mriscvcore_inst.ALU_inst.en_reg, rval = 1'0). Adding SRST signal on $flatten\mriscvcore_inst.\ALU_inst.$procdff$5729 ($dff) from module processorci_top (D = { \mriscvcore_inst.ALU_inst.is_inst_reg [0] \mriscvcore_inst.ALU_inst.is_inst_nr }, Q = \mriscvcore_inst.ALU_inst.is_inst_reg, rval = 2'00). Adding SRST signal on $flatten\mriscvcore_inst.\ALU_inst.$procdff$5728 ($dff) from module processorci_top (D = { \mriscvcore_inst.ALU_inst.is_rd_reg [0] \mriscvcore_inst.ALU_inst.is_rd_nr }, Q = \mriscvcore_inst.ALU_inst.is_rd_reg, rval = 2'00). Adding EN signal on $flatten\ResetBootSystem.$procdff$5658 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$5657 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5600 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1728_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1722_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1713_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1704_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1695_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1686_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1668_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1677_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6273 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$6273 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1722_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1713_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1704_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1695_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1686_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1668_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1677_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5598 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1644_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6278 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1644_Y, Q = \Controller.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5597 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1633_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$6284 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1296_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5596 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5595 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1622_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$6289 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1622_Y, Q = \Controller.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5594 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1611_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6295 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5592 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1588_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1579_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1570_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1561_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1552_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1543_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1525_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1534_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6297 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5591 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1507_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6301 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1336_Y, Q = \Controller.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5590 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1502_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6305 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5589 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1494_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$6307 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1347_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5587 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5586 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$5585 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1471_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6313 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1156_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr). Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$5584 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1153_DATA, Q = \Controller.Uart.TX_FIFO.read_data). Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$5580 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1466_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6320 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1172_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr). Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$5585 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1471_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6322 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1156_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr). Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$5584 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1153_DATA, Q = \Controller.Uart.RX_FIFO.read_data). Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$5580 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1466_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6329 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1172_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5648 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2642_Y, Q = \Controller.Uart.state_read, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6331 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2642_Y, Q = \Controller.Uart.state_read). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5647 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2667_Y, Q = \Controller.Uart.counter_read, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$6335 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2667_Y, Q = \Controller.Uart.counter_read). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5646 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2631_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5645 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2682_Y, Q = \Controller.Uart.read_data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6352 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2680_Y, Q = \Controller.Uart.read_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5644 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2620_Y, Q = \Controller.Uart.read_response, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5643 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2564_Y, Q = \Controller.Uart.state_write, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6359 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2564_Y, Q = \Controller.Uart.state_write). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5642 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2586_Y, Q = \Controller.Uart.counter_write, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$6363 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2586_Y, Q = \Controller.Uart.counter_write). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5641 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2600_Y, Q = \Controller.Uart.write_data_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6373 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2600_Y, Q = \Controller.Uart.write_data_buffer). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5640 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2614_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6383 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5639 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2546_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5638 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2556_Y, Q = \Controller.Uart.write_response, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5637 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2537_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6397 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5636 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2532_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5634 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2527_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6400 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5633 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2503_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5632 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2511_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5631 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2050_Y, Q = \Controller.Interpreter.temp_buffer). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5630 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2093_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6417 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2093_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]). Adding EN signal on $auto$ff.cc:266:slice$6417 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2093_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5629 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2103_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6432 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2103_Y, Q = \Controller.Interpreter.timeout_counter). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5628 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5627 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2144_Y, Q = \Controller.Interpreter.read_buffer). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5626 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2172_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6448 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5625 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2197_Y, Q = \Controller.Interpreter.num_of_positions). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5624 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2219_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6459 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5623 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2225_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6461 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2225_Y, Q = \Controller.Interpreter.return_state). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5622 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2249_Y, Q = \Controller.Interpreter.memory_page_number). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5621 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2257_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6476 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2257_Y, Q = \Controller.Interpreter.memory_mux_selector). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5620 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2297_Y, Q = \Controller.Interpreter.end_position, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6480 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2297_Y, Q = \Controller.Interpreter.end_position). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5618 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2339_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6484 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2339_Y, Q = \Controller.Interpreter.bus_mode). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5617 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1878_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5616 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2350_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5615 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1983_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5614 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2360_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6497 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2360_Y, Q = \Controller.Interpreter.core_clk_enable). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5613 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5612 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2002_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5611 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2025_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5610 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1935_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5609 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2436_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6513 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2436_Y, Q = \Controller.Interpreter.counter). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5608 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2460_Y, Q = \Controller.Interpreter.write_data). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5607 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2486_Y, Q = \Controller.Interpreter.address). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5606 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1902_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5605 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1924_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5604 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1778_Y, Q = \Controller.Interpreter.state, rval = 8'00000000). Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$5601 ($dff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1752_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6536 ($sdff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1752_Y, Q = \Controller.ClkDivider.pulse_counter). Adding SRST signal on $flatten\Controller.$procdff$5655 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2703_Y, Q = \Controller.finish_execution, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6544 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2703_Y, Q = \Controller.finish_execution). Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6436 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6436 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6436 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6436 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6436 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6436 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6436 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6436 ($dffe) from module processorci_top. Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6202 ($dffe) from module processorci_top. Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$6192 ($sdffe) from module processorci_top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$6192 ($sdffe) from module processorci_top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6192 ($sdffe) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6192 ($sdffe) from module processorci_top. 20.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 171 unused cells and 224 unused wires. <suppressed ~173 debug messages> 20.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~38 debug messages> 20.13.9. Rerunning OPT passes. (Maybe there is more to do..) 20.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/3 on $pmux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4222. dead port 3/3 on $pmux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4222. dead port 1/3 on $pmux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4254. dead port 3/3 on $pmux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4254. dead port 1/3 on $pmux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4288. dead port 3/3 on $pmux $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$4288. Removed 6 multiplexer ports. <suppressed ~115 debug messages> 20.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$6303: { \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o } Optimizing cells in module \processorci_top. Performed a total of 1 changes. 20.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~90 debug messages> Removed a total of 30 cells. 20.13.13. Executing OPT_DFF pass (perform DFF optimizations). 20.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 39 unused wires. <suppressed ~2 debug messages> 20.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.13.16. Rerunning OPT passes. (Maybe there is more to do..) 20.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~113 debug messages> 20.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 20.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.13.20. Executing OPT_DFF pass (perform DFF optimizations). 20.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 20.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.13.23. Finished OPT passes. (There is nothing left to do.) 20.14. Executing WREDUCE pass (reducing word size of cells). Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$5732 (Controller.Data_Memory.memory). Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$963 (Controller.Data_Memory.memory). Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$5732 (Controller.Memory.memory). Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$963 (Controller.Memory.memory). Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$5731 (Controller.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1153 (Controller.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$5731 (Controller.Uart.TX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1153 (Controller.Uart.TX_FIFO.memory). Removed top 2 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6241 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6263 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5988 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1254 ($gt). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1211 ($eq). Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1215 ($add). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1218 ($add). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1227 ($lt). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1232 ($eq). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1234 ($ge). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1779_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1780_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1782 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1784_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1785_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1786_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1787_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1788_CMP0 ($eq). Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1790 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1792_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1793_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1795 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1797_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1798_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1802_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1803_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1804_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1806 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1808_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1809_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1810_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1812 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1814_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1816 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1818_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1819_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1820_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1821_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1822_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1823_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1824_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1826 ($mux). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1828_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1830 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1832_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1833_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1835 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1837_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1838_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1841_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1840 ($pmux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1842_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1843_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1844_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1845_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1846_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1847_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1848_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1849_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1850_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1851_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1852_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1853_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1854_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1855_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1856_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1857_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1858_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1859_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1860_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1861_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1862_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1863_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1864_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1866 ($mux). Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1868_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1870 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1904_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1905_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1906_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1939_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2094_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2095_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2096_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2139_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2265_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2298_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2299_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2372_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2373_CMP0 ($eq). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$1185 ($lt). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1190 ($lt). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6064 ($eq). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2551_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2557_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2558_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2570_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2572 ($mux). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2621_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2622_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2636_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2644_CMP0 ($eq). Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2652 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1463 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1451 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1173 ($sub). Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1173 ($sub). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1172 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1171 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1170 ($eq). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1156 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1155 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1154 ($eq). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1463 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1451 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1173 ($sub). Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1173 ($sub). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1172 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1171 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1170 ($eq). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1156 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1155 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1154 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6055 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1325 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1324 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1323 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1322 ($mux). Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1317 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1315 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1291 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1283 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1281 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1278 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1277 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1273 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1268 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1267 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1266 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1265 ($mux). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1261 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1259 ($eq). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2694 ($mux). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2694 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$940 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$924 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$923 ($mux). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2720_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$910 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$909 ($add). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$909 ($add). Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$908 ($lt). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5974 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6549 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6539 ($ne). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\mriscvcore_inst.\FSM_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:34$89 ($eq). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\mriscvcore_inst.\FSM_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:34$90 ($eq). Removed top 4 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\FSM_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:37$95 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6051 ($eq). Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\mriscvcore_inst.\FSM_inst.$procmux$4748 ($mux). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\mriscvcore_inst.\UTILITY_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:82$326 ($add). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2755_CMP0 ($eq). Removed top 5 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2756_CMP0 ($eq). Removed top 5 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2757_CMP0 ($eq). Removed top 6 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2775_CMP0 ($eq). Removed top 7 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2776_CMP0 ($eq). Removed top 5 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\UTILITY_inst.$procmux$2779_CMP0 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:228$282 ($add). Removed top 27 bits (of 32) from port Y of cell processorci_top.$flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:228$282 ($add). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:232$288 ($add). Removed top 27 bits (of 32) from port Y of cell processorci_top.$flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:232$288 ($add). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:236$294 ($add). Removed top 27 bits (of 32) from port Y of cell processorci_top.$flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:236$294 ($add). Removed top 1 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\MULT_inst.$procmux$2887_CMP0 ($eq). Removed top 1 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\MULT_inst.$procmux$2896_CMP0 ($eq). Removed top 1 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\MULT_inst.$procmux$2908_CMP0 ($eq). Removed top 1 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\MULT_inst.$procmux$2909_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6025 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6013 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5424_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5425_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5426_CMP0 ($eq). Removed top 4 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5427_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5428_CMP0 ($eq). Removed top 5 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5429_CMP0 ($eq). Removed top 1 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5459_CMP0 ($eq). Removed top 4 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5461_CMP0 ($eq). Removed top 4 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5462_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5463_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5464_CMP0 ($eq). Removed top 3 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5471_CMP0 ($eq). Removed top 3 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5472_CMP0 ($eq). Removed top 3 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5473_CMP0 ($eq). Removed top 3 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5474_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5475_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5476_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5477_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5478_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5479_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5480_CMP0 ($eq). Removed top 6 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5482_CMP0 ($eq). Removed top 7 bits (of 12) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.$procmux$5483_CMP0 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$sub$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:633$862 ($sub). Removed top 27 bits (of 32) from port Y of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$sub$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:633$862 ($sub). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$sub$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:628$857 ($sub). Removed top 27 bits (of 32) from port Y of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$sub$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:628$857 ($sub). Removed top 2 bits (of 5) from port B of cell processorci_top.$flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$ge$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:623$853 ($ge). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\mriscvcore_inst.\DECO_INSTR_inst.$ne$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:80$79 ($ne). Removed top 6 bits (of 7) from port B of cell processorci_top.$flatten\mriscvcore_inst.\DECO_INSTR_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:96$81 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4785_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4902_CMP0 ($eq). Removed top 1 bits (of 12) from mux cell processorci_top.$flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4940 ($mux). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4943_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4985_CMP0 ($eq). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5036_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5217_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5217_CMP1 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:79$170 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5963 ($eq). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$ternary$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:227$216 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$ternary$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:232$218 ($mux). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3152_CMP0 ($eq). Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$923_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_ADDR[31:0]$967. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1782_Y. Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1790_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1795_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1806_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1812_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1816_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1826_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1830_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1840_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1866_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1870_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$961_ADDR[31:0]$967. Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2572_Y. Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2652_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_ADDR[5:0]$1158. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_ADDR[5:0]$1167. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1155_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1171_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1172_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_ADDR[5:0]$1158. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1148_ADDR[5:0]$1167. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1155_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1171_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1156_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1172_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1322_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1323_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1324_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1325_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1265_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1266_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1267_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1268_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$909_Y. Removed top 27 bits (of 32) from wire processorci_top.$flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$sub$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:628$857_Y. Removed top 27 bits (of 32) from wire processorci_top.$flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$sub$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:633$862_Y. Removed top 1 bits (of 12) from wire processorci_top.$flatten\mriscvcore_inst.\DECO_INSTR_inst.$6\codif[11:0]. Removed top 1 bits (of 2) from wire processorci_top.$flatten\mriscvcore_inst.\FSM_inst.$procmux$4748_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$ternary$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:227$216_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$ternary$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:232$218_Y. Removed top 27 bits (of 32) from wire processorci_top.$flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:228$282_Y. 20.15. Executing PEEPOPT pass (run peephole optimizers). 20.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 43 unused wires. <suppressed ~1 debug messages> 20.17. Executing SHARE pass (SAT-based resource sharing). Found 2 cells in module processorci_top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$963 ($memrd): Found 2 activation_patterns using ctrl signal { \Controller.Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1822_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }. No candidates found. Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$963 ($memrd): Found 1 activation_patterns using ctrl signal { \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1822_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }. No candidates found. 20.18. Executing TECHMAP pass (map to technology primitives). 20.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/cmp2lut.v Parsing Verilog input from `/usr/local/share/synlig/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 20.18.2. Continuing TECHMAP pass. Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt. No more expansions possible. <suppressed ~223 debug messages> 20.19. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 6 unused wires. <suppressed ~1 debug messages> 20.21. Executing TECHMAP pass (map to technology primitives). 20.21.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/mul2dsp.v Parsing Verilog input from `/usr/local/share/synlig/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 20.21.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/dsp_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 20.21.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 20.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module processorci_top: creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1255 ($sub). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1210 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1214 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1215 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1218 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1225 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1229 ($add). creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1217 ($sub). creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1192 ($add). creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1187 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1155 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1171 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1173 ($sub). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1155 ($add). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1171 ($add). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1173 ($sub). creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1336 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1347 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1285 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1296 ($add). creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$909 ($add). creating $macc model for $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$sub$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:628$857 ($sub). creating $macc model for $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$sub$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:633$862 ($sub). creating $macc model for $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:210$212 ($add). creating $macc model for $flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:228$282 ($add). creating $macc model for $flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:232$288 ($add). creating $macc model for $flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:236$294 ($add). creating $macc model for $flatten\mriscvcore_inst.\UTILITY_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:72$323 ($add). creating $macc model for $flatten\mriscvcore_inst.\UTILITY_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:82$326 ($add). creating $alu model for $macc $flatten\mriscvcore_inst.\UTILITY_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:82$326. creating $alu model for $macc $flatten\mriscvcore_inst.\UTILITY_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:72$323. creating $alu model for $macc $flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:236$294. creating $alu model for $macc $flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:232$288. creating $alu model for $macc $flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:228$282. creating $alu model for $macc $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:210$212. creating $alu model for $macc $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$sub$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:633$862. creating $alu model for $macc $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$sub$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:628$857. creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$909. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1296. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1285. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1347. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1336. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1173. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1171. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1155. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1173. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1171. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1155. creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1187. creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1192. creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1217. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1229. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1225. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1218. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1215. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1214. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1210. creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1255. creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1254 ($gt): new $alu creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1234 ($ge): new $alu creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1227 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1234. creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$908 ($lt): new $alu creating $alu model for $flatten\mriscvcore_inst.\ALU_inst.\ALU_blt_inst.$lt$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:575$867 ($lt): new $alu creating $alu model for $flatten\mriscvcore_inst.\ALU_inst.\ALU_bltu_inst.$lt$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:593$865 ($lt): new $alu creating $alu model for $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$ge$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:623$853 ($ge): new $alu creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1232 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1234. creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$910 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$908. creating $alu model for $flatten\mriscvcore_inst.\ALU_inst.\ALU_beq_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:557$869 ($eq): merged with $flatten\mriscvcore_inst.\ALU_inst.\ALU_bltu_inst.$lt$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:593$865. creating $alu cell for $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$ge$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:623$853: $auto$alumacc.cc:485:replace_alu$6606 creating $alu cell for $flatten\mriscvcore_inst.\ALU_inst.\ALU_bltu_inst.$lt$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:593$865, $flatten\mriscvcore_inst.\ALU_inst.\ALU_beq_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:557$869: $auto$alumacc.cc:485:replace_alu$6615 creating $alu cell for $flatten\mriscvcore_inst.\ALU_inst.\ALU_blt_inst.$lt$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:575$867: $auto$alumacc.cc:485:replace_alu$6622 creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$908, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$910: $auto$alumacc.cc:485:replace_alu$6629 creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1234, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1227, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1232: $auto$alumacc.cc:485:replace_alu$6640 creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1254: $auto$alumacc.cc:485:replace_alu$6653 creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1255: $auto$alumacc.cc:485:replace_alu$6658 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1210: $auto$alumacc.cc:485:replace_alu$6661 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1214: $auto$alumacc.cc:485:replace_alu$6664 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1215: $auto$alumacc.cc:485:replace_alu$6667 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1218: $auto$alumacc.cc:485:replace_alu$6670 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1225: $auto$alumacc.cc:485:replace_alu$6673 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1229: $auto$alumacc.cc:485:replace_alu$6676 creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1217: $auto$alumacc.cc:485:replace_alu$6679 creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1192: $auto$alumacc.cc:485:replace_alu$6682 creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1187: $auto$alumacc.cc:485:replace_alu$6685 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1155: $auto$alumacc.cc:485:replace_alu$6688 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1171: $auto$alumacc.cc:485:replace_alu$6691 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1173: $auto$alumacc.cc:485:replace_alu$6694 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1155: $auto$alumacc.cc:485:replace_alu$6697 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1171: $auto$alumacc.cc:485:replace_alu$6700 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1173: $auto$alumacc.cc:485:replace_alu$6703 creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1336: $auto$alumacc.cc:485:replace_alu$6706 creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1347: $auto$alumacc.cc:485:replace_alu$6709 creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1285: $auto$alumacc.cc:485:replace_alu$6712 creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1296: $auto$alumacc.cc:485:replace_alu$6715 creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$909: $auto$alumacc.cc:485:replace_alu$6718 creating $alu cell for $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$sub$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:628$857: $auto$alumacc.cc:485:replace_alu$6721 creating $alu cell for $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$sub$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:633$862: $auto$alumacc.cc:485:replace_alu$6724 creating $alu cell for $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:210$212: $auto$alumacc.cc:485:replace_alu$6727 creating $alu cell for $flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:228$282: $auto$alumacc.cc:485:replace_alu$6730 creating $alu cell for $flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:232$288: $auto$alumacc.cc:485:replace_alu$6733 creating $alu cell for $flatten\mriscvcore_inst.\MULT_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:236$294: $auto$alumacc.cc:485:replace_alu$6736 creating $alu cell for $flatten\mriscvcore_inst.\UTILITY_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:72$323: $auto$alumacc.cc:485:replace_alu$6739 creating $alu cell for $flatten\mriscvcore_inst.\UTILITY_inst.$add$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:82$326: $auto$alumacc.cc:485:replace_alu$6742 created 35 $alu and 0 $macc cells. 20.23. Executing OPT pass (performing simple optimizations). 20.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~4 debug messages> 20.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~113 debug messages> 20.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 20.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 20.23.6. Executing OPT_DFF pass (perform DFF optimizations). 20.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 13 unused wires. <suppressed ~1 debug messages> 20.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.23.9. Rerunning OPT passes. (Maybe there is more to do..) 20.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~113 debug messages> 20.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 20.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.23.13. Executing OPT_DFF pass (perform DFF optimizations). 20.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 20.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.23.16. Finished OPT passes. (There is nothing left to do.) 20.24. Executing MEMORY pass. 20.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 20.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 20.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing processorci_top.Controller.Data_Memory.memory write port 0. Analyzing processorci_top.Controller.Memory.memory write port 0. Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0. Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0. Analyzing processorci_top.mriscvcore_inst.REG_FILE_inst.MEM_FILE.ram write port 0. 20.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 20.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\mriscvcore_inst.REG_FILE_inst.MEM_FILE.ram'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\mriscvcore_inst.REG_FILE_inst.MEM_FILE.ram'[1] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found. Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found. 20.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 4 unused cells and 84 unused wires. <suppressed ~5 debug messages> 20.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory processorci_top.mriscvcore_inst.REG_FILE_inst.MEM_FILE.ram by address: 20.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 20.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 20.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 20.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 20.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0] mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0] mapping memory processorci_top.mriscvcore_inst.REG_FILE_inst.MEM_FILE.ram via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.mriscvcore_inst.REG_FILE_inst.MEM_FILE.ram: $\mriscvcore_inst.REG_FILE_inst.MEM_FILE.ram$rdreg[0] Extracted data FF from read port 1 of processorci_top.mriscvcore_inst.REG_FILE_inst.MEM_FILE.ram: $\mriscvcore_inst.REG_FILE_inst.MEM_FILE.ram$rdreg[1] <suppressed ~2603 debug messages> 20.27. Executing TECHMAP pass (map to technology primitives). 20.27.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/lutrams_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 20.27.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/brams_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 20.27.3. Continuing TECHMAP pass. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~1078 debug messages> 20.28. Executing OPT pass (performing simple optimizations). 20.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~295 debug messages> 20.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 20.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\ResetBootSystem.$procdff$5656 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Adding SRST signal on $auto$ff.cc:266:slice$6469 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1229_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6408 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2050_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]). Adding SRST signal on $auto$ff.cc:266:slice$6257 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2717_Y, Q = \ResetBootSystem.counter, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6239 ($sdffe) from module processorci_top (D = $flatten\mriscvcore_inst.\ALU_inst.\ALU_sXXx_inst.$procmux$1360_Y [1:0], Q = \mriscvcore_inst.ALU_inst.ALU_sXXx_inst.count [1:0]). Adding SRST signal on $auto$ff.cc:266:slice$6201 ($sdff) from module processorci_top (D = $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$2\Wdataq[31:0], Q = \mriscvcore_inst.MEMORY_INTERFACE_inst.Wdata, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6178 ($sdffe) from module processorci_top (D = \mriscvcore_inst.UTILITY_inst.PC_N [1:0], Q = \mriscvcore_inst.UTILITY_inst.PC_N2 [1:0]). 20.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 10 unused cells and 7519 unused wires. <suppressed ~12 debug messages> 20.28.5. Rerunning OPT passes. (Removed registers in this run.) 20.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~5 debug messages> 20.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$9249 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$6588 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). 20.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 3 unused wires. <suppressed ~2 debug messages> 20.28.10. Rerunning OPT passes. (Removed registers in this run.) 20.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.28.13. Executing OPT_DFF pass (perform DFF optimizations). 20.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 20.28.15. Finished fast OPT passes. 20.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 20.30. Executing OPT pass (performing simple optimizations). 20.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~74 debug messages> 20.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$9258: { $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3290_CMP $flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$eq$/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:79$170_Y \Controller.Interpreter.core_reset } New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$9247: { $auto$opt_dff.cc:194:make_patterns_logic$9244 $auto$fsm_map.cc:74:implement_pattern_cache$6008 $auto$opt_dff.cc:194:make_patterns_logic$6411 $auto$opt_dff.cc:194:make_patterns_logic$6409 } Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$923: Old ports: A=\Controller.core_address_memory [11:0], B={ \Controller.Interpreter.memory_page_number [5:0] \Controller.core_address_memory [5:0] }, Y=$auto$wreduce.cc:461:run$6553 [11:0] New ports: A=\Controller.core_address_memory [11:6], B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$6553 [11:6] New connections: $auto$wreduce.cc:461:run$6553 [5:0] = \Controller.core_address_memory [5:0] Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1790: Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$6556 [2:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$6556 [2] $auto$wreduce.cc:461:run$6556 [0] } New connections: $auto$wreduce.cc:461:run$6556 [1] = $auto$wreduce.cc:461:run$6556 [0] Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1795: Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$6557 [6:0] New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$6557 [1:0] New connections: $auto$wreduce.cc:461:run$6557 [6:2] = { $auto$wreduce.cc:461:run$6557 [1] 3'010 $auto$wreduce.cc:461:run$6557 [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1806: Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$6558 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6558 [2] New connections: { $auto$wreduce.cc:461:run$6558 [3] $auto$wreduce.cc:461:run$6558 [1:0] } = { $auto$wreduce.cc:461:run$6558 [2] 2'00 } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1816: Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$6560 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6560 [0] New connections: $auto$wreduce.cc:461:run$6560 [3:1] = { $auto$wreduce.cc:461:run$6560 [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1830: Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$6562 [6:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$6562 [0] New connections: $auto$wreduce.cc:461:run$6562 [6:1] = { $auto$wreduce.cc:461:run$6562 [0] 1'0 $auto$wreduce.cc:461:run$6562 [0] 3'011 } Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2225: Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$2225_Y New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$2225_Y [4:0] New connections: $flatten\Controller.\Interpreter.$procmux$2225_Y [7:5] = 3'000 Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2350: Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2350_Y New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2350_Y [23:0] New connections: $flatten\Controller.\Interpreter.$procmux$2350_Y [31:24] = 8'00000000 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2360: $auto$opt_reduce.cc:137:opt_pmux$5795 Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2564: Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$6567 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2564_Y New ports: A=3'000, B={ $auto$wreduce.cc:461:run$6567 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2564_Y [2:0] New connections: $flatten\Controller.\Uart.$procmux$2564_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2572: Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$6567 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$6567 [2] New connections: $auto$wreduce.cc:461:run$6567 [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2648: Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2648_Y New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2648_Y [2:1] New connections: { $flatten\Controller.\Uart.$procmux$2648_Y [3] $flatten\Controller.\Uart.$procmux$2648_Y [0] } = 2'00 Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1606: Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$6580 [0] 1'0 $auto$wreduce.cc:461:run$6581 [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$6583 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$6580 [0] $auto$wreduce.cc:461:run$6581 [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$6583 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1325: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$6583 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6583 [0] New connections: $auto$wreduce.cc:461:run$6583 [1] = $auto$wreduce.cc:461:run$6583 [0] Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1743: Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$6585 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$6587 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$6585 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$6587 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1268: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$6587 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6587 [0] New connections: $auto$wreduce.cc:461:run$6587 [1] = $auto$wreduce.cc:461:run$6587 [0] New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2735: { $flatten\ResetBootSystem.$procmux$2721_CMP $flatten\ResetBootSystem.$procmux$2720_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2738: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2738_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2738_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2738_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4782: Old ports: A=12'111111111111, B={ 2'00 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\codif[11:0] New ports: A=11'11111111111, B={ 1'0 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\codif[11:0] [10:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\codif[11:0] [11] = $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\codif[11:0] [10] Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4806: Old ports: A=32'11111111111111111111111111111111, B={ \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31:20] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] New ports: A=12'111111111111, B=\mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31:20], Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [31:12] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$10\immr[31:0] [11] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4813: Old ports: A=12'111111111111, B={ 2'00 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\codif[11:0] New ports: A=11'11111111111, B={ 1'0 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\codif[11:0] [10:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\codif[11:0] [11] = $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\codif[11:0] [10] Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4823: Old ports: A=32'11111111111111111111111111111111, B={ 20'00000000000000000000 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31:20] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] New ports: A=13'1111111111111, B={ 1'0 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31:20] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [31:13] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4833: Old ports: A=5'11111, B=5'00000, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\rs2i[4:0] New ports: A=1'1, B=1'0, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\rs2i[4:0] [0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\rs2i[4:0] [4:1] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\rs2i[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\rs2i[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\rs2i[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\rs2i[4:0] [0] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4907: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] New ports: A=1'1, B=1'0, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [31:1] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$7\immr[31:0] [0] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4940: Old ports: A={ \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [30] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, B={ 1'0 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$auto$wreduce.cc:461:run$6591 [10:0] New ports: A=\mriscvcore_inst.MEMORY_INTERFACE_inst.inst [30], B=1'0, Y=$auto$wreduce.cc:461:run$6591 [10] New connections: $auto$wreduce.cc:461:run$6591 [9:0] = { \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4982: Old ports: A=12'111111111111, B={ 2'00 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\codif[11:0] New ports: A=11'11111111111, B={ 1'0 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\codif[11:0] [10:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\codif[11:0] [11] = $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\codif[11:0] [10] Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4992: Old ports: A=5'11111, B=5'00000, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\rdi[4:0] New ports: A=1'1, B=1'0, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\rdi[4:0] [0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\rdi[4:0] [4:1] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\rdi[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\rdi[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\rdi[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\rdi[4:0] [0] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5022: Old ports: A=32'11111111111111111111111111111111, B={ \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31:25] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [11:7] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] New ports: A=12'111111111111, B={ \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31:25] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [11:7] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [31:12] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$5\immr[31:0] [11] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5033: Old ports: A=12'111111111111, B={ 2'00 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\codif[11:0] New ports: A=11'11111111111, B={ 1'0 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\codif[11:0] [10:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\codif[11:0] [11] = $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\codif[11:0] [10] Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5044: Old ports: A=5'11111, B=5'00000, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\rs2i[4:0] New ports: A=1'1, B=1'0, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\rs2i[4:0] [0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\rs2i[4:0] [4:1] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\rs2i[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\rs2i[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\rs2i[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\rs2i[4:0] [0] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5077: Old ports: A=32'11111111111111111111111111111111, B={ \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31:20] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] New ports: A=12'111111111111, B=\mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31:20], Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [31:12] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$4\immr[31:0] [11] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5089: Old ports: A=12'111111111111, B={ 2'00 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\codif[11:0] New ports: A=11'11111111111, B={ 1'0 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\codif[11:0] [10:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\codif[11:0] [11] = $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\codif[11:0] [10] Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5125: Old ports: A=5'11111, B=5'00000, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\rdi[4:0] New ports: A=1'1, B=1'0, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\rdi[4:0] [0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\rdi[4:0] [4:1] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\rdi[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\rdi[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\rdi[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\rdi[4:0] [0] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5137: Old ports: A=32'11111111111111111111111111111111, B={ \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [7] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [30:25] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [11:8] 1'0 }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] New ports: A=13'1111111111111, B={ \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [7] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [30:25] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [11:8] 1'0 }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [31:13] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$3\immr[31:0] [12] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5150: Old ports: A=12'111111111111, B={ 2'00 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\codif[11:0] New ports: A=11'11111111111, B={ 1'0 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [14:12] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\codif[11:0] [10:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\codif[11:0] [11] = $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\codif[11:0] [10] Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5163: Old ports: A=5'11111, B=5'00000, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\rs2i[4:0] New ports: A=1'1, B=1'0, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\rs2i[4:0] [0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\rs2i[4:0] [4:1] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\rs2i[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\rs2i[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\rs2i[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\rs2i[4:0] [0] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$5202: Old ports: A=32'11111111111111111111111111111111, B={ \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31:20] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] New ports: A=12'111111111111, B=\mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31:20], Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [31:12] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$2\immr[31:0] [11] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\FSM_inst.$procmux$4760: Old ports: A=2'11, B=2'00, Y=$flatten\mriscvcore_inst.\FSM_inst.$procmux$4760_Y New ports: A=1'1, B=1'0, Y=$flatten\mriscvcore_inst.\FSM_inst.$procmux$4760_Y [0] New connections: $flatten\mriscvcore_inst.\FSM_inst.$procmux$4760_Y [1] = $flatten\mriscvcore_inst.\FSM_inst.$procmux$4760_Y [0] Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\MULT_inst.\u1.$procmux$3018: Old ports: A=3'000, B=3'101, Y=$flatten\mriscvcore_inst.\MULT_inst.\u1.$3\OutFSM[2:0] New ports: A=1'0, B=1'1, Y=$flatten\mriscvcore_inst.\MULT_inst.\u1.$3\OutFSM[2:0] [0] New connections: $flatten\mriscvcore_inst.\MULT_inst.\u1.$3\OutFSM[2:0] [2:1] = { $flatten\mriscvcore_inst.\MULT_inst.\u1.$3\OutFSM[2:0] [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\MULT_inst.\u3.$procmux$5267: Old ports: A=3'000, B=3'101, Y=$flatten\mriscvcore_inst.\MULT_inst.\u3.$3\OutFSM[2:0] New ports: A=1'0, B=1'1, Y=$flatten\mriscvcore_inst.\MULT_inst.\u3.$3\OutFSM[2:0] [0] New connections: $flatten\mriscvcore_inst.\MULT_inst.\u3.$3\OutFSM[2:0] [2:1] = { $flatten\mriscvcore_inst.\MULT_inst.\u3.$3\OutFSM[2:0] [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\MULT_inst.\u5.$procmux$3018: Old ports: A=3'000, B=3'101, Y=$flatten\mriscvcore_inst.\MULT_inst.\u5.$3\OutFSM[2:0] New ports: A=1'0, B=1'1, Y=$flatten\mriscvcore_inst.\MULT_inst.\u5.$3\OutFSM[2:0] [0] New connections: $flatten\mriscvcore_inst.\MULT_inst.\u5.$3\OutFSM[2:0] [2:1] = { $flatten\mriscvcore_inst.\MULT_inst.\u5.$3\OutFSM[2:0] [0] 1'0 } Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2642: Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2648_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2642_Y New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2648_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2642_Y [2:0] New connections: $flatten\Controller.\Uart.$procmux$2642_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2744: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2738_Y, Y=$flatten\ResetBootSystem.$procmux$2744_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2738_Y [1], Y=$flatten\ResetBootSystem.$procmux$2744_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2744_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4863: Old ports: A=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\codif[11:0], B={ 4'0000 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [20] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\codif[11:0] New ports: A=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\codif[11:0] [10:0], B={ 3'000 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [20] \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [6:0] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\codif[11:0] [10:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\codif[11:0] [11] = $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\codif[11:0] [10] Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4870: Old ports: A=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0], B={ 20'00000000000000000000 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31:20] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] New ports: A=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\immr[31:0] [12:0], B={ 1'0 \mriscvcore_inst.MEMORY_INTERFACE_inst.inst [31:20] }, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12:0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [31:13] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\immr[31:0] [12] } Consolidated identical input bits for $mux cell $flatten\mriscvcore_inst.\DECO_INSTR_inst.$procmux$4877: Old ports: A=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\rs2i[4:0], B=5'00000, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\rs2i[4:0] New ports: A=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$9\rs2i[4:0] [0], B=1'0, Y=$flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\rs2i[4:0] [0] New connections: $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\rs2i[4:0] [4:1] = { $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\rs2i[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\rs2i[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\rs2i[4:0] [0] $flatten\mriscvcore_inst.\DECO_INSTR_inst.$8\rs2i[4:0] [0] } Optimizing cells in module \processorci_top. Performed a total of 50 changes. 20.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 20.30.6. Executing OPT_DFF pass (perform DFF optimizations). 20.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 3 unused wires. <suppressed ~2 debug messages> 20.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 20.30.9. Rerunning OPT passes. (Maybe there is more to do..) 20.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~76 debug messages> 20.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 20.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.30.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6288 ($sdff) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6332 ($sdffe) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6360 ($sdffe) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6462 ($sdffe) from module processorci_top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6462 ($sdffe) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6462 ($sdffe) from module processorci_top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6489 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6489 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6489 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6489 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6489 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6489 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6489 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6489 ($dffe) from module processorci_top. 20.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 20.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~4 debug messages> 20.30.16. Rerunning OPT passes. (Maybe there is more to do..) 20.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~76 debug messages> 20.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1800: Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1800_Y New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1800_Y [4:0] New connections: $flatten\Controller.\Interpreter.$procmux$1800_Y [7:5] = 3'000 Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1778: Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$6565 [0] 6'000000 $auto$wreduce.cc:461:run$6559 [1:0] 1'0 $auto$wreduce.cc:461:run$6563 [6:0] 14'00001101000011 $flatten\Controller.\Interpreter.$procmux$1835_Y [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$6562 [6] 1'0 $auto$wreduce.cc:461:run$6562 [6] 3'011 $auto$wreduce.cc:461:run$6562 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$6558 [3] 2'00 $auto$wreduce.cc:461:run$6558 [3] 6'000010 $auto$wreduce.cc:461:run$6559 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$6558 [3] $auto$wreduce.cc:461:run$6558 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1800_Y 1'0 $auto$wreduce.cc:461:run$6557 [6] 3'010 $auto$wreduce.cc:461:run$6557 [2] $auto$wreduce.cc:461:run$6557 [6] $auto$wreduce.cc:461:run$6557 [2] 13'0001001100010 $auto$wreduce.cc:461:run$6556 [2:1] $auto$wreduce.cc:461:run$6556 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$6555 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1778_Y New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$6565 [0] 5'00000 $auto$wreduce.cc:461:run$6559 [1:0] $auto$wreduce.cc:461:run$6563 [6:0] 12'000110100011 $flatten\Controller.\Interpreter.$procmux$1835_Y [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$6562 [6] 1'0 $auto$wreduce.cc:461:run$6562 [6] 3'011 $auto$wreduce.cc:461:run$6562 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$6558 [3] 2'00 $auto$wreduce.cc:461:run$6558 [3] 5'00010 $auto$wreduce.cc:461:run$6559 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$6558 [3] $auto$wreduce.cc:461:run$6558 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1800_Y [4:0] $auto$wreduce.cc:461:run$6557 [6] 3'010 $auto$wreduce.cc:461:run$6557 [2] $auto$wreduce.cc:461:run$6557 [6] $auto$wreduce.cc:461:run$6557 [2] 11'00100110010 $auto$wreduce.cc:461:run$6556 [2:1] $auto$wreduce.cc:461:run$6556 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$6555 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1778_Y [6:0] New connections: $flatten\Controller.\Interpreter.$procmux$1778_Y [7] = 1'0 Optimizing cells in module \processorci_top. Performed a total of 2 changes. 20.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.30.20. Executing OPT_DFF pass (perform DFF optimizations). 20.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 20.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.30.23. Rerunning OPT passes. (Maybe there is more to do..) 20.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~76 debug messages> 20.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 20.30.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.30.27. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6535 ($sdff) from module processorci_top. 20.30.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 20.30.29. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 20.30.30. Rerunning OPT passes. (Maybe there is more to do..) 20.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~76 debug messages> 20.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 20.30.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.30.34. Executing OPT_DFF pass (perform DFF optimizations). 20.30.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 20.30.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.30.37. Finished OPT passes. (There is nothing left to do.) 20.31. Executing TECHMAP pass (map to technology primitives). 20.31.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 20.31.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/arith_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 20.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $lut. Using template $paramod$03eba0cdd46566f6651a3011e0b5671fa6b5e494\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $mux. Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu. Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu. Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $dffe. Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu. Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu. Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux. Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux. Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux. Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux. Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux. Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux. Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $sdff. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $sdffce. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu. Using template $paramod$b8c0a997bce700f23568a5ada79cc6781d1f5ca0\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $bmux. Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux. Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux. Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ecp5_alu for cells of type $alu. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using template $paramod$672a140277c71df8314410f22acc08d55222c3c7\_80_ecp5_alu for cells of type $alu. Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_80_ecp5_alu for cells of type $alu. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_pmux for cells of type $pmux. Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux. Using template $paramod$dc04b7d98e503a7bab16fce2df70e6e2c5ca34d6\_80_ecp5_alu for cells of type $alu. Using template $paramod$a93995b8b533c9c51271ffe70384f459e79c5d76\_90_pmux for cells of type $pmux. Using template $paramod$f587f97d3019cb6509bb9d96ec321cde2ec5fd64\_90_pmux for cells of type $pmux. Using template $paramod$730057d8259da96d4776b15a47b747852ed4c479\_90_pmux for cells of type $pmux. Using template $paramod$104d3d1e82b09b030a785dad8a5e608a6d4401f7\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $pos. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~4418 debug messages> 20.32. Executing OPT pass (performing simple optimizations). 20.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~10624 debug messages> 20.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6060 debug messages> Removed a total of 2020 cells. 20.32.3. Executing OPT_DFF pass (perform DFF optimizations). 20.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1413 unused cells and 5472 unused wires. <suppressed ~1419 debug messages> 20.32.5. Finished fast OPT passes. 20.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 20.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 20.35. Executing TECHMAP pass (map to technology primitives). 20.35.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 20.35.2. Continuing TECHMAP pass. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. No more expansions possible. <suppressed ~1036 debug messages> 20.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~109 debug messages> 20.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 20.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in processorci_top. 20.39. Executing ATTRMVCP pass (move or copy attributes). 20.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 5034 unused wires. <suppressed ~1 debug messages> 20.41. Executing TECHMAP pass (map to technology primitives). 20.41.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/latches_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 20.41.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 20.42. Executing ABC9 pass. 20.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 20.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 20.42.3. Executing PROC pass (convert processes to netlists). 20.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$38861'. Cleaned up 1 empty switch. 20.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$38862 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 20.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 20.42.3.4. Executing PROC_INIT pass (extract init attributes). 20.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 20.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 20.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$38862'. 1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$38860_EN[3:0]$38868 2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$38860_DATA[3:0]$38867 3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$38860_ADDR[3:0]$38866 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$38861'. 20.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 20.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38853_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38854_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38858_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38849_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38855_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38850_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38856_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38846_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38847_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38852_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38844_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38859_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38848_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38857_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38851_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$38845_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$38860_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$38862'. created $dff cell `$procdff$38912' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$38860_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$38862'. created $dff cell `$procdff$38913' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$38860_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$38862'. created $dff cell `$procdff$38914' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$38861'. created direct connection (no actual register cell created). 20.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 20.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$38886'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$38862'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$38861'. Cleaned up 1 empty switch. 20.42.3.12. Executing OPT_EXPR pass (perform const folding). 20.42.4. Executing SCC pass (detecting logic loops). Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$21156 $auto$simplemap.cc:38:simplemap_not$28571 $auto$ff.cc:266:slice$14398 $auto$ff.cc:479:convert_ce_over_srst$37697 $auto$simplemap.cc:126:simplemap_reduce$9631 $auto$simplemap.cc:38:simplemap_not$28572 $auto$alumacc.cc:485:replace_alu$6629.slice[0].ccu2c_i $auto$ff.cc:266:slice$14399 $auto$ff.cc:479:convert_ce_over_srst$37699 $auto$ff.cc:266:slice$14400 $auto$ff.cc:479:convert_ce_over_srst$37701 $auto$alumacc.cc:485:replace_alu$6629.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$9635 $auto$simplemap.cc:126:simplemap_reduce$9632 $auto$simplemap.cc:38:simplemap_not$30123 $auto$ff.cc:266:slice$14401 $auto$ff.cc:479:convert_ce_over_srst$37703 $auto$ff.cc:266:slice$14402 $auto$ff.cc:479:convert_ce_over_srst$37705 $auto$simplemap.cc:38:simplemap_not$9638 $auto$alumacc.cc:485:replace_alu$6629.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$9447 $auto$simplemap.cc:126:simplemap_reduce$9637 $auto$simplemap.cc:126:simplemap_reduce$9633 $auto$simplemap.cc:38:simplemap_not$30125 $auto$ff.cc:266:slice$14403 $auto$ff.cc:479:convert_ce_over_srst$37707 $auto$simplemap.cc:126:simplemap_reduce$9461 $auto$simplemap.cc:126:simplemap_reduce$9459 $auto$simplemap.cc:126:simplemap_reduce$9450 $auto$simplemap.cc:126:simplemap_reduce$9448 $auto$simplemap.cc:38:simplemap_not$9651 $auto$simplemap.cc:75:simplemap_bitop$9652 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$37199 $auto$ff.cc:266:slice$13718 $auto$simplemap.cc:126:simplemap_reduce$13878 $auto$simplemap.cc:126:simplemap_reduce$13863 $auto$ff.cc:266:slice$13717 $auto$opt_expr.cc:617:replace_const_cells$37231 $auto$ff.cc:266:slice$13715 $auto$opt_expr.cc:617:replace_const_cells$37219 $auto$simplemap.cc:267:simplemap_mux$28606 $auto$simplemap.cc:126:simplemap_reduce$28620 $auto$simplemap.cc:126:simplemap_reduce$28617 $auto$simplemap.cc:75:simplemap_bitop$28610 $auto$simplemap.cc:196:simplemap_lognot$13882 $auto$simplemap.cc:126:simplemap_reduce$13880 $auto$simplemap.cc:126:simplemap_reduce$13877 $auto$simplemap.cc:267:simplemap_mux$13849 $auto$simplemap.cc:225:simplemap_logbin$13852 $auto$simplemap.cc:196:simplemap_lognot$13867 $auto$simplemap.cc:126:simplemap_reduce$13865 $auto$simplemap.cc:126:simplemap_reduce$13862 $auto$ff.cc:266:slice$13716 $auto$simplemap.cc:126:simplemap_reduce$9485 $auto$simplemap.cc:126:simplemap_reduce$9483 $auto$simplemap.cc:225:simplemap_logbin$13808 $auto$simplemap.cc:196:simplemap_lognot$13818 $auto$simplemap.cc:126:simplemap_reduce$13816 $auto$opt_expr.cc:617:replace_const_cells$37217 $auto$simplemap.cc:267:simplemap_mux$28607 $auto$simplemap.cc:126:simplemap_reduce$28625 $auto$simplemap.cc:126:simplemap_reduce$28622 $auto$simplemap.cc:75:simplemap_bitop$28609 Found an SCC: $auto$ff.cc:266:slice$13727 $auto$ff.cc:266:slice$13726 $auto$ff.cc:266:slice$13724 $auto$opt_expr.cc:617:replace_const_cells$37195 $auto$ff.cc:266:slice$13722 $auto$simplemap.cc:126:simplemap_reduce$13899 $auto$opt_expr.cc:617:replace_const_cells$37193 $auto$ff.cc:266:slice$13723 $auto$simplemap.cc:126:simplemap_reduce$13898 $auto$ff.cc:266:slice$13721 $auto$ff.cc:266:slice$13720 $auto$simplemap.cc:126:simplemap_reduce$13902 $auto$simplemap.cc:126:simplemap_reduce$13897 $auto$simplemap.cc:38:simplemap_not$28521 $auto$ff.cc:266:slice$13719 $auto$opt_expr.cc:617:replace_const_cells$37191 $auto$ff.cc:266:slice$13725 $auto$simplemap.cc:126:simplemap_reduce$9489 $auto$simplemap.cc:196:simplemap_lognot$13909 $auto$simplemap.cc:126:simplemap_reduce$13907 $auto$simplemap.cc:126:simplemap_reduce$13905 $auto$simplemap.cc:126:simplemap_reduce$13903 $auto$simplemap.cc:126:simplemap_reduce$13900 $auto$simplemap.cc:38:simplemap_not$28528 Found an SCC: $auto$ff.cc:266:slice$13573 $auto$ff.cc:266:slice$13572 $auto$simplemap.cc:126:simplemap_reduce$13697 $auto$opt_expr.cc:617:replace_const_cells$36627 $auto$simplemap.cc:126:simplemap_reduce$13670 $auto$ff.cc:266:slice$13571 $auto$ff.cc:266:slice$13579 $auto$simplemap.cc:38:simplemap_not$28633 $auto$ff.cc:266:slice$13578 $auto$opt_expr.cc:617:replace_const_cells$36631 $auto$ff.cc:266:slice$13576 $auto$simplemap.cc:126:simplemap_reduce$13672 $auto$simplemap.cc:126:simplemap_reduce$13699 $auto$simplemap.cc:38:simplemap_not$28630 $auto$ff.cc:266:slice$13575 $auto$simplemap.cc:126:simplemap_reduce$13702 $auto$simplemap.cc:126:simplemap_reduce$13698 $auto$opt_expr.cc:617:replace_const_cells$36625 $auto$ff.cc:266:slice$13574 $auto$simplemap.cc:196:simplemap_lognot$13709 $auto$simplemap.cc:126:simplemap_reduce$13707 $auto$simplemap.cc:126:simplemap_reduce$13705 $auto$simplemap.cc:126:simplemap_reduce$13703 $auto$simplemap.cc:126:simplemap_reduce$13700 $auto$simplemap.cc:126:simplemap_reduce$13676 $auto$simplemap.cc:126:simplemap_reduce$13673 $auto$opt_expr.cc:617:replace_const_cells$36621 $auto$ff.cc:266:slice$13577 $auto$simplemap.cc:167:logic_reduce$14532 $auto$simplemap.cc:225:simplemap_logbin$13654 $auto$simplemap.cc:225:simplemap_logbin$13655 $auto$simplemap.cc:196:simplemap_lognot$13682 $auto$simplemap.cc:126:simplemap_reduce$13680 $auto$simplemap.cc:126:simplemap_reduce$13678 $auto$simplemap.cc:126:simplemap_reduce$13675 $auto$simplemap.cc:126:simplemap_reduce$13671 $auto$simplemap.cc:38:simplemap_not$28628 Found an SCC: $auto$ff.cc:266:slice$17856 $auto$simplemap.cc:126:simplemap_reduce$17847 $auto$ff.cc:266:slice$17857 $auto$ff.cc:266:slice$17858 $auto$simplemap.cc:126:simplemap_reduce$17850 $auto$simplemap.cc:126:simplemap_reduce$17848 $auto$ff.cc:266:slice$17859 $auto$simplemap.cc:196:simplemap_lognot$17854 $auto$simplemap.cc:126:simplemap_reduce$17852 $auto$opt_expr.cc:617:replace_const_cells$37021 $auto$ff.cc:266:slice$17860 $auto$simplemap.cc:167:logic_reduce$9390 Found an SCC: $auto$simplemap.cc:38:simplemap_not$25054 $auto$ff.cc:266:slice$17832 $auto$simplemap.cc:126:simplemap_reduce$17823 $auto$ff.cc:266:slice$17833 $auto$ff.cc:266:slice$17834 $auto$opt_expr.cc:617:replace_const_cells$36951 $auto$ff.cc:266:slice$17836 $auto$simplemap.cc:167:logic_reduce$22162 $auto$simplemap.cc:196:simplemap_lognot$17830 $auto$simplemap.cc:126:simplemap_reduce$17828 $auto$simplemap.cc:126:simplemap_reduce$17826 $auto$simplemap.cc:126:simplemap_reduce$17824 $auto$ff.cc:266:slice$17835 Found an SCC: $auto$ff.cc:266:slice$17790 $auto$simplemap.cc:126:simplemap_reduce$17781 $auto$ff.cc:266:slice$17791 $auto$ff.cc:266:slice$17792 $auto$simplemap.cc:126:simplemap_reduce$17784 $auto$simplemap.cc:126:simplemap_reduce$17782 $auto$ff.cc:266:slice$17793 $auto$simplemap.cc:167:logic_reduce$14569 $auto$simplemap.cc:196:simplemap_lognot$17788 $auto$simplemap.cc:126:simplemap_reduce$17786 $auto$simplemap.cc:38:simplemap_not$33626 $auto$ff.cc:266:slice$17794 Found 7 SCCs in module processorci_top. Found 7 SCCs. 20.42.5. Executing ABC9_OPS pass (helper functions for ABC9). 20.42.6. Executing PROC pass (convert processes to netlists). 20.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 20.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 20.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 20.42.6.4. Executing PROC_INIT pass (extract init attributes). 20.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 20.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 20.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 20.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 20.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). 20.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 20.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 20.42.6.12. Executing OPT_EXPR pass (perform const folding). 20.42.7. Executing TECHMAP pass (map to technology primitives). 20.42.7.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 20.42.7.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~162 debug messages> 20.42.8. Executing OPT pass (performing simple optimizations). 20.42.8.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 20.42.8.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 20.42.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 20.42.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Performed a total of 0 changes. 20.42.8.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 20.42.8.6. Executing OPT_DFF pass (perform DFF optimizations). 20.42.8.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. 20.42.8.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 20.42.8.9. Finished OPT passes. (There is nothing left to do.) 20.42.9. Executing TECHMAP pass (map to technology primitives). 20.42.9.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_map.v Parsing Verilog input from `/usr/local/share/synlig/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 20.42.9.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~1063 debug messages> 20.42.10. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_model.v Parsing Verilog input from `/usr/local/share/synlig/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 20.42.11. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 20.42.12. Executing ABC9_OPS pass (helper functions for ABC9). 20.42.13. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 20.42.14. Executing TECHMAP pass (map to technology primitives). 20.42.14.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 20.42.14.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~201 debug messages> 20.42.15. Executing OPT pass (performing simple optimizations). 20.42.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~18 debug messages> 20.42.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 20.42.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 20.42.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 20.42.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.42.15.6. Executing OPT_DFF pass (perform DFF optimizations). 20.42.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 20.42.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.42.15.9. Rerunning OPT passes. (Maybe there is more to do..) 20.42.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 20.42.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 20.42.15.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 20.42.15.13. Executing OPT_DFF pass (perform DFF optimizations). 20.42.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 20.42.15.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 20.42.15.16. Finished OPT passes. (There is nothing left to do.) 20.42.16. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 20.42.17. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 7098 cells with 44991 new cells, skipped 4944 cells. replaced 3 cell types: 1565 $_OR_ 150 $_XOR_ 5383 $_MUX_ not replaced 8 cell types: 38 $scopeinfo 488 $_NOT_ 1109 $_AND_ 921 TRELLIS_FF 1060 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1060 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 267 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 1 $__ABC9_SCC_BREAKER 20.42.17.1. Executing ABC9_OPS pass (helper functions for ABC9). 20.42.17.2. Executing ABC9_OPS pass (helper functions for ABC9). 20.42.17.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 19273 AND gates and 57843 wires from module `processorci_top' to a netlist network with 5175 inputs and 1282 outputs. 20.42.17.4. Executing ABC9_EXE pass (technology mapping using ABC9). 20.42.17.5. Executing ABC9. Running ABC command: "built in abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 5175/ 1282 and = 17972 lev = 26 (2.22) mem = 0.55 MB box = 1327 bb = 1060 ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 1 carries. ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 5175/ 1282 and = 23430 lev = 35 (1.76) mem = 0.61 MB ch = 2387 box = 1324 bb = 1060 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 64. Obj = 148. Set = 672. CutMin = no ABC: Node = 23430. Ch = 1703. Total mem = 7.16 MB. Peak cut mem = 0.21 MB. ABC: P: Del = 4568.00. Ar = 18768.0. Edge = 21777. Cut = 338196. T = 0.15 sec ABC: P: Del = 4504.00. Ar = 18669.0. Edge = 21673. Cut = 339274. T = 0.16 sec ABC: P: Del = 4504.00. Ar = 9732.0. Edge = 18659. Cut = 667635. T = 0.29 sec ABC: F: Del = 4504.00. Ar = 7882.0. Edge = 17765. Cut = 430122. T = 0.19 sec ABC: A: Del = 4504.00. Ar = 7240.0. Edge = 16768. Cut = 401702. T = 0.27 sec ABC: A: Del = 4504.00. Ar = 7136.0. Edge = 16710. Cut = 399502. T = 0.27 sec ABC: Total time = 1.33 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 5175/ 1282 and = 15098 lev = 24 (1.84) mem = 0.51 MB box = 1306 bb = 1060 ABC: Mapping (K=7) : lut = 4121 edge = 16492 lev = 9 (0.85) Boxes are not in a topological order. Switching to level computation without boxes. ABC: levB = 24 mem = 0.24 MB ABC: LUT = 4121 : 2=467 11.3 % 3=683 16.6 % 4=1953 47.4 % 5=648 15.7 % 6=133 3.2 % 7=237 5.8 % Ave = 4.00 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 10.37 seconds, total: 10.37 seconds 20.42.17.6. Executing AIGER frontend. <suppressed ~12947 debug messages> Removed 20817 unused cells and 47714 unused wires. 20.42.17.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 4139 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 1060 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 246 ABC RESULTS: input signals: 1147 ABC RESULTS: output signals: 302 Removing temp directory. 20.42.18. Executing TECHMAP pass (map to technology primitives). 20.42.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_unmap.v Parsing Verilog input from `/usr/local/share/synlig/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 20.42.18.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000111 for cells of type $__ABC9_SCC_BREAKER. No more expansions possible. <suppressed ~2386 debug messages> Removed 344 unused cells and 73806 unused wires. 20.43. Executing TECHMAP pass (map to technology primitives). 20.43.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 20.43.2. Continuing TECHMAP pass. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod$b4e9ea3921e02bce0d630933f106608ba1bed76e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$977490006f4a840fd1689395e12c974fb072d2ed\$lut for cells of type $lut. Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$91d6743ceb0f093b57d242b538f7f23d2346d4c9\$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$e5f6bb4c336301dfe5a121d6589fab23eaee704a\$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$a670b08a47dd8a34f954c50cd06e9996d77e8467\$lut for cells of type $lut. Using template $paramod$eaea85d27cc0950ed001348e061727a194f5cf9c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut. Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut. Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b\$lut for cells of type $lut. Using template $paramod$6e64c13666511ae2ccc90ab6ddaf8be09bda5af2\$lut for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut. Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut. Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut. Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$0a4d85497e20c50068555dd5ad9ad3a7952cab73\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$f34232779a0569d5ac41d2d692536961128467b0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut. Using template $paramod$07b1b12ce0305f55108770e958fd02caedfebdf8\$lut for cells of type $lut. Using template $paramod$f782c0d9db8308022a9483df75860b2e163a6660\$lut for cells of type $lut. Using template $paramod$08e09ab8d949b13687b44104a69ce0d3a2496be5\$lut for cells of type $lut. Using template $paramod$f87bcf1791971b4eaa30f3f28437044fef878a04\$lut for cells of type $lut. Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod$516c9deb5d9610c8f0d10ff2bb662050159fbb17\$lut for cells of type $lut. Using template $paramod$6f998cf38cebbb6e06e3187277050023f7734eb6\$lut for cells of type $lut. Using template $paramod$7b30e7cb2eab5ef9107c960d71614fd597d826ef\$lut for cells of type $lut. Using template $paramod$338a7a4eec3a9a3a3eb715f4c65bfdf73a2fea59\$lut for cells of type $lut. Using template $paramod$46d981b5eabc08c1691f743d7a017e4435316de4\$lut for cells of type $lut. Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$71c291be5a30cbd4d8da4720549295c11c0232eb\$lut for cells of type $lut. Using template $paramod$52d96bfa17866bab828b9f1286c638d27fce0ef0\$lut for cells of type $lut. Using template $paramod$f0773b2e1ec54f4b5730a332b99958a07b433091\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$d42eb623c894d365b500e30bf895d8466a2cf3cb\$lut for cells of type $lut. Using template $paramod$edb77d50aceb5fd5281195660e4e297e6a761362\$lut for cells of type $lut. Using template $paramod$8410e3fb232e10c46cfabbf6670ff46053dd8eb7\$lut for cells of type $lut. Using template $paramod$6ab0c0dc70deff66bd932c82ca16b95e0015fa64\$lut for cells of type $lut. Using template $paramod$305ccde234bf31b1ee1911e7aaabb7dad1abc8b4\$lut for cells of type $lut. Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a\$lut for cells of type $lut. Using template $paramod$4558cbe9e5e02f8a0297a1c93179d5f7f51d4e85\$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. Using template $paramod$6e424bd4a747f8421ac946af3d9bb3a47fd0b233\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$40882341c54dcd36f630f00dd7e46a35652abd36\$lut for cells of type $lut. Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut. Using template $paramod$e5761adfcc530461835be17350166b9d43dfadee\$lut for cells of type $lut. Using template $paramod$20798777255c214e32de3304ce8faa1fdfa2f474\$lut for cells of type $lut. Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut. Using template $paramod$f0e96eead45e414d00cd3483116e37b02f724538\$lut for cells of type $lut. Using template $paramod$7b0d2a2ffb3b8f28d614fe2eb48a97cfa46f63f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. Using template $paramod$d6a246575d0ba3dcbbccd768ad41b602f82ff057\$lut for cells of type $lut. Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut. Using template $paramod$660a72f63d46a844bb0ddab189b65027c878fc6b\$lut for cells of type $lut. Using template $paramod$150ee00bee81b2fcb159e621f4ef27bccb5ede20\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut. Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\$lut for cells of type $lut. Using template $paramod$1c7d8014a4d7918ee35a20538945662d20569ae6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut. Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut. Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$d1239dea58a04f3eb43994cd44236e98b306ac2c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$3c5eb16fa418cfbbe1710d24d17e7d0b5448c3c1\$lut for cells of type $lut. Using template $paramod$d204630841d4b2793bc7d88db78fa2d9975da1ca\$lut for cells of type $lut. Using template $paramod$c6bcc46fa3ab3e93fb9e1dd465343adac18fec92\$lut for cells of type $lut. Using template $paramod$4062cf70671465f0a81555c918e539e42ee3eab2\$lut for cells of type $lut. Using template $paramod$a9ba23df824f693c44e722629fd8c1fae157385c\$lut for cells of type $lut. Using template $paramod$424ed2fb59da90e546e5b1ca8ecac079e8f359ae\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut. Using template $paramod$1343edce7d3a957b4ed0f1f83825df9a2e0b3f18\$lut for cells of type $lut. Using template $paramod$dd3fb0b6061f2daaaedd5e300347a303c89566f9\$lut for cells of type $lut. Using template $paramod$628969b6b47c3b8995c67ab8d27a147e7831d402\$lut for cells of type $lut. Using template $paramod$a30ad272e59e727528e9ae74ad3bd2ee75b3b011\$lut for cells of type $lut. Using template $paramod$07620d52cb536ce2865a3d1bba2ad2f7a88140f9\$lut for cells of type $lut. Using template $paramod$a7d9b4ab0321c8125e5b895183ee6b84cdb4a31b\$lut for cells of type $lut. Using template $paramod$8c14e6d85060218e346675600ae1194fdf5a803e\$lut for cells of type $lut. Using template $paramod$28573d64e05cfef986b669757c9bc724facdf28b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$ff315d5084ed3c80e34901fe05add0db5feb0b93\$lut for cells of type $lut. Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut. Using template $paramod$a842d819659c3c266ebe1593af717c4143bc2f9a\$lut for cells of type $lut. Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod$cb9ec208ed3f93c67a792a740b808eaed5b5d6d3\$lut for cells of type $lut. Using template $paramod$9309e865df2c90ed2610d17af606a0ac9631ea81\$lut for cells of type $lut. Using template $paramod$faf4b69e2195a9ce52b7c3bce83fa5ea343bc378\$lut for cells of type $lut. Using template $paramod$653b67ac034534e77376908a617ba88c09379223\$lut for cells of type $lut. Using template $paramod$0dc999d2ffa7482e7708162151ed9ad308d249ba\$lut for cells of type $lut. Using template $paramod$1df6d41de86e48fa0e114cfe35ac61195abc3952\$lut for cells of type $lut. Using template $paramod$7f6adb65fc9817e5f782902d8b5e425a354ea225\$lut for cells of type $lut. Using template $paramod$72999a7ffa547571d7240ef55378d6675343dc1c\$lut for cells of type $lut. Using template $paramod$76b69988499323c223a91b64a512926500d4c698\$lut for cells of type $lut. Using template $paramod$75876453a005b95ebef3b0503ce2bb989784f8b8\$lut for cells of type $lut. Using template $paramod$b31b45fff019f012ba9f9758d832f23a9b11490c\$lut for cells of type $lut. Using template $paramod$f6205ea4d16154fcc0de4d21dff0bd55a57f1ba0\$lut for cells of type $lut. Using template $paramod$70c4f8567ff78303251984e5dc69b479d6acf30f\$lut for cells of type $lut. Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut. Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut. Using template $paramod$b431bfd938e35871dd0b7668e1503c7e8b9d491c\$lut for cells of type $lut. Using template $paramod$b7685cb0c8a6753256bc84bc31d36a443c15fab7\$lut for cells of type $lut. Using template $paramod$6e3a03c79073e44642e8ed2dab4ee82dfd40dfba\$lut for cells of type $lut. Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut. Using template $paramod$016b22223dd60ce2de7d5de8fe6d5aa659e67737\$lut for cells of type $lut. Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001001 for cells of type $lut. Using template $paramod$38400b76de2b00d7d5f8f09de118b82fd1b8be0a\$lut for cells of type $lut. Using template $paramod$00b535f5faed668e4cd5c38955a5410cae662986\$lut for cells of type $lut. Using template $paramod$09194da5f2c8e08bed8f609fd0e254d8629b24b3\$lut for cells of type $lut. Using template $paramod$b53357ee6fde5ef3078cb0414ab34f9bac50e1b4\$lut for cells of type $lut. Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut. Using template $paramod$b009a26b33c3ca109c016cf968a774c0d66687bb\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut. Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut. Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut. Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut. Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut. Using template $paramod$f5ee2886f0cf3b7fd61b8ea4cb426db115ff04a2\$lut for cells of type $lut. Using template $paramod$2f9969e97b40bbbf9ca9e8fad1e184542373359b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut. Using template $paramod$253532b742d151c01e8e51f153c24d934b8f6185\$lut for cells of type $lut. Using template $paramod$02fbe8c67d33eabc42a06d471f5fbd85b121dbcc\$lut for cells of type $lut. Using template $paramod$ffdb063eb19e9f472876ebedf8721cdc7ba0dc9e\$lut for cells of type $lut. Using template $paramod$0b802c26b52838b873ce4c0b3d8fe72914c72603\$lut for cells of type $lut. Using template $paramod$8c11a155773d2e4aba9b1022fc059160b55313e8\$lut for cells of type $lut. Using template $paramod$25fb5de0c1b1ab120cbff6b4ddf0f1a13cbd2503\$lut for cells of type $lut. Using template $paramod$060fe3a9a87c070316bade86e73c95c5eaa2139d\$lut for cells of type $lut. Using template $paramod$a6cdd4a48df0609f38a8ef356cce7e7aef82f66f\$lut for cells of type $lut. Using template $paramod$6b62468353a716e43972563d3074fa328b3ddcae\$lut for cells of type $lut. Using template $paramod$bdb70def730e65d3dfe4589c8075e8e4ee443325\$lut for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut. Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut. Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut. Using template $paramod$87ff84199e04aa17d0b707d6d74a7573636ce9ed\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$04b674496422df8889c01c3744b94097628ccfbc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. Using template $paramod$72043e0aa7fa64cb454e3c2ca3dbe1636171896a\$lut for cells of type $lut. Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut. Using template $paramod$12e9049d8709286a770fe60b59ec4d94c39ce3c9\$lut for cells of type $lut. Using template $paramod$9f6bc32305fc769fa11e4327bee073e3fbe84018\$lut for cells of type $lut. Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut. Using template $paramod$ff74d3b36221c7c7b417c242545ab45c7d96a8ff\$lut for cells of type $lut. Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut. Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut. Using template $paramod$e718d2f5eb562e6029d6a1b1e060511bf1c65df1\$lut for cells of type $lut. Using template $paramod$e10953846cca08ec47dc3219af842bddaf473ada\$lut for cells of type $lut. Using template $paramod$f464e8ee635b255785618aa5657b4cb388e7c29e\$lut for cells of type $lut. Using template $paramod$ef56f9a7c1ad9b8282f306459adf7d0a10da74cc\$lut for cells of type $lut. Using template $paramod$6bc00ddefc0f984400c51bbb3bf28e20f4beacbc\$lut for cells of type $lut. Using template $paramod$672e798a02b8bcc43378b3bcf167b71b5747401f\$lut for cells of type $lut. Using template $paramod$db1ca260d4f04cd4385e44ff35df16acbfdf76fc\$lut for cells of type $lut. Using template $paramod$e846a90bf756f527f545bdf004e83d5b124706b6\$lut for cells of type $lut. Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut. Using template $paramod$508c2000b84feb5620c4a9d86fba027147e34ff1\$lut for cells of type $lut. Using template $paramod$c1e8855410306fd7198e5d148431aeee82b6fdcd\$lut for cells of type $lut. Using template $paramod$ab2d8c2b9d8aa7f76721394c261b87284f763090\$lut for cells of type $lut. Using template $paramod$fa9a9929a034821b7e453075ef98a4240297b3c5\$lut for cells of type $lut. Using template $paramod$28d8107f897ca0b9bcf6f0c92ed1adb53060639d\$lut for cells of type $lut. Using template $paramod$9a2a223399d2b073cac3b4fce3b9abd7b8c5ba3b\$lut for cells of type $lut. Using template $paramod$8b6508a5ab9aca311450220eeef2be7fa209e0a5\$lut for cells of type $lut. Using template $paramod$79a1d065fabc3c00274e2fbe8ea6b98194fd2189\$lut for cells of type $lut. Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9\$lut for cells of type $lut. Using template $paramod$30d0a2190ad4c97308be50f413b03ae693dcb1d5\$lut for cells of type $lut. Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut. Using template $paramod$5bb4589aef4e67d4113ef14e01c5bb618a3e9139\$lut for cells of type $lut. Using template $paramod$58b33073d6510d6145ff01c28a604d07765b1342\$lut for cells of type $lut. Using template $paramod$ee6944635a66b35a2c008244d1b98fdaec97fc5f\$lut for cells of type $lut. Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut. Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut. Using template $paramod$946e4ba6cc6d5f643745e6b56089375901ce6d2c\$lut for cells of type $lut. Using template $paramod$8075729953f49b6cb1b4d863b2fb20da9818d304\$lut for cells of type $lut. Using template $paramod$0b871dbd0fe7bf5ae91e0e18c1b37856c84e532c\$lut for cells of type $lut. Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut. Using template $paramod$6acdbf5a9b2b4778d33125be6bed8d464c708ed6\$lut for cells of type $lut. Using template $paramod$aea1c03749b88ed34d454cc6e8153e829d5d62e7\$lut for cells of type $lut. Using template $paramod$a0560de7091f619730ebeff566013f93558ff713\$lut for cells of type $lut. Using template $paramod$019d676de54ad046ee622227e7a6fd53173158a8\$lut for cells of type $lut. Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. Using template $paramod$ebec0c2052bf3d47692d0a862109ad9b99ecf9d2\$lut for cells of type $lut. Using template $paramod$2f407302e7fa007cf603a8472ce6ead93966bd91\$lut for cells of type $lut. Using template $paramod$ad24441560918d8a80bbd5a1da20c2d9d45f26dc\$lut for cells of type $lut. Using template $paramod$53779c84fe4b43160ea73b6cf8d4b75327ff7a08\$lut for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut. Using template $paramod$022f25e351f4370d3db4af915ee589ef82048c31\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568\$lut for cells of type $lut. Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef\$lut for cells of type $lut. Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut. Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut. Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67\$lut for cells of type $lut. Using template $paramod$da50fd91f0a124a27a799b06adedf1b9696d7a66\$lut for cells of type $lut. Using template $paramod$2c56adda0f23d3add745fd9eb8ad3ffc02c981b6\$lut for cells of type $lut. Using template $paramod$49b4d47dab45283a5bca35b8996da0a3c24bef1f\$lut for cells of type $lut. Using template $paramod$0225bab1951d47190ef75d19c1e8910e2f3d5083\$lut for cells of type $lut. Using template $paramod$20eeafe61aeaceb3763b92996e53135220b182f1\$lut for cells of type $lut. Using template $paramod$1fe287df1573511e96dc6e9e5ebd525b50dc8b00\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod$7da6a3d375590798104e6970494bd85e29d896ab\$lut for cells of type $lut. Using template $paramod$e5ca65a4ef689621b3aeabada05c2009697d651c\$lut for cells of type $lut. Using template $paramod$7172c591dbc20477c74967033bf9f4d27a36231d\$lut for cells of type $lut. Using template $paramod$9a3e28b389c1f3cb6cf0807228c461506fb829f5\$lut for cells of type $lut. Using template $paramod$3e45df178f87cae7b22686270af206e8594cc30e\$lut for cells of type $lut. Using template $paramod$f0a8d60cc979850c90b8106514f770a701d4bea2\$lut for cells of type $lut. Using template $paramod$a4a9e215ab6881a8e5582e8e6abccd5e8f8c831d\$lut for cells of type $lut. Using template $paramod$ab0b2f86668b4ceb1d5bf8df14e7e2fbac829c46\$lut for cells of type $lut. Using template $paramod$f6d844001a1ac2d696a737787d23d1e23e5704f1\$lut for cells of type $lut. Using template $paramod$570232e3a63190e7f35a3a70dbc054ddda1110ca\$lut for cells of type $lut. Using template $paramod$edd190708942da2f36989f2e8def8342d029335b\$lut for cells of type $lut. Using template $paramod$4f79d472867f62e55dd736f8b9b25cd05a56667d\$lut for cells of type $lut. Using template $paramod$370310bd6d542aea8376470decc807a62e208fcb\$lut for cells of type $lut. Using template $paramod$563acb1d1bf0bfccf04043ec6296c30447924991\$lut for cells of type $lut. Using template $paramod$0cf29a4557396093145f91210175c275306af2f2\$lut for cells of type $lut. Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut. Using template $paramod$e0286d7bdebdb6346cb367bb1962e01892ba2e32\$lut for cells of type $lut. Using template $paramod$fc6d1d5d922f69cdc5ce89d141a4cfdf356a2ad8\$lut for cells of type $lut. Using template $paramod$1ec3fb8fd1fa98216cb96b4422de32c4ba5f6c9c\$lut for cells of type $lut. Using template $paramod$37be11c6c8d2b9c52a2237d19b839661720eff1e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut. Using template $paramod$5c5a4c80185a252668d50e0d14bb02b87876367b\$lut for cells of type $lut. Using template $paramod$88c045b95abf554491d84741742d3991e7f29600\$lut for cells of type $lut. Using template $paramod$23d143b740ec56dfd15faed9990f4a998727b8ad\$lut for cells of type $lut. Using template $paramod$cc21ac5de47c8e9e03b09089bdcb5a432c963cfd\$lut for cells of type $lut. Using template $paramod$48e5d3f533c24c092a2c7693e2ee5c2ad7fb1d8a\$lut for cells of type $lut. Using template $paramod$ee01f8aaa86cdcd4b779fec0dec9c9062f5b2128\$lut for cells of type $lut. Using template $paramod$0b4903be815181a236dc0408b3dc10605c577e9f\$lut for cells of type $lut. Using template $paramod$6eea68b0cebbb56cefb069b20d1b1a201a85aa44\$lut for cells of type $lut. Using template $paramod$b28066912c648b5e1db8eca536ab1a11a6dcff85\$lut for cells of type $lut. Using template $paramod$284267df938459b9413fa2429dd65c56f230d038\$lut for cells of type $lut. Using template $paramod$28d06ca838ce859392c72faa79ad165900ba5228\$lut for cells of type $lut. Using template $paramod$9e28a6f93c9b67713335a4223dcd6ae94af8c020\$lut for cells of type $lut. Using template $paramod$707701b498a5cd123a043548b93e61e0b6bdc440\$lut for cells of type $lut. Using template $paramod$c08a774c89ef1ea6ee2ef4d8c3b071eb141d4259\$lut for cells of type $lut. Using template $paramod$428455bf683af997b0aced216a36aa68a8816e79\$lut for cells of type $lut. Using template $paramod$51b138c6601401861f3f66aa30cc9212c6a6619a\$lut for cells of type $lut. Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut. Using template $paramod$90fd787c45e964c3d33b628aa0fed4882c4814c9\$lut for cells of type $lut. Using template $paramod$36e77cf68e95b3b8cccf1bb5b64409630f2c88d1\$lut for cells of type $lut. Using template $paramod$5cdd6c45be1730619480254670476c4ed2df25cf\$lut for cells of type $lut. Using template $paramod$12c89aedec282308b36752520f3a983cb933df99\$lut for cells of type $lut. Using template $paramod$76ac84a4d83d1bfe9020ed040d9c928a5977264e\$lut for cells of type $lut. Using template $paramod$d8a851edf04260eb28aaaf93d5a60542d6e72d32\$lut for cells of type $lut. Using template $paramod$ae61b877d17eb7903daa877f74511c12aafab0d1\$lut for cells of type $lut. Using template $paramod$e4857636d35dc9b5293045a985a317a436a4713f\$lut for cells of type $lut. Using template $paramod$0849e7554b11a7bd7d350473b61b905912ea19fd\$lut for cells of type $lut. Using template $paramod$3b46d9708782bb72eca71a7fede35ade633e9947\$lut for cells of type $lut. Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut. Using template $paramod$2d70e360329f2b83357618532825d0cf30a325f3\$lut for cells of type $lut. Using template $paramod$03d7da0d848b4f563fda6bc83a08135cc5ded340\$lut for cells of type $lut. Using template $paramod$c7eaad6a588218ef0ba5a17502d003bdff2bbd3e\$lut for cells of type $lut. Using template $paramod$5fae40e7e039f35b2e4514771a6f18123f0e0a25\$lut for cells of type $lut. Using template $paramod$28817d89f5472fcc664c2c9c33f74ca219183c24\$lut for cells of type $lut. Using template $paramod$7e3de18263fb7d0a2e12a4401120994e66bde6a4\$lut for cells of type $lut. Using template $paramod$b089060a61c5d29ddce66d73edb5ee493ec9de27\$lut for cells of type $lut. Using template $paramod$248ad907ba23dea94672fccffbd51dfbf074636b\$lut for cells of type $lut. Using template $paramod$13162dab747ee1e52bfdba3be872c6d5a3be6de5\$lut for cells of type $lut. Using template $paramod$67ed851dcd4a972c20f6ecfb6a1f8766cd1ed285\$lut for cells of type $lut. Using template $paramod$b40080b643baa8bb528ec249e10d82b2d80dfed9\$lut for cells of type $lut. Using template $paramod$3b1a23b0ebe5a82de8684af0fbdd7666d6fb625c\$lut for cells of type $lut. Using template $paramod$912cf622adc9bd99771a3792f165476315a967eb\$lut for cells of type $lut. Using template $paramod$152933c3c10a0b6565167a91c2a9ea06871b8166\$lut for cells of type $lut. Using template $paramod$dd351332a44263d6274369352ca1bd334f12f053\$lut for cells of type $lut. Using template $paramod$d00da410a391e7b8f4fec71cf8cee3263c056906\$lut for cells of type $lut. Using template $paramod$60e04b33e2c800ab56e4f066327c20046666bc4d\$lut for cells of type $lut. Using template $paramod$81bc37815d1d01eaff204267e4c7cad035645797\$lut for cells of type $lut. Using template $paramod$f832053af8d41762375745e70da856bb418d7a3c\$lut for cells of type $lut. Using template $paramod$88042169380e5061327dbbab80daa18c75c82b9b\$lut for cells of type $lut. Using template $paramod$f74938286b747bef2f99f29cc09a910c9e894ca5\$lut for cells of type $lut. Using template $paramod$fb80ef4fc978a87dfdc28557c70de63f9fc68a1c\$lut for cells of type $lut. Using template $paramod$b0cd46553deec6c777257090aadc2b7320d012dc\$lut for cells of type $lut. Using template $paramod$72d1f6b5b78c4e4da0e7b24951cfaeaa9c9ef7ef\$lut for cells of type $lut. Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut. Using template $paramod$c6a0421f5b5114b68e9782f0585d571421cf8f01\$lut for cells of type $lut. Using template $paramod$f8ebec45000729276574044ae838ec1e40a7eaec\$lut for cells of type $lut. Using template $paramod$e332cff882edd417f410bab5fe07a0f88572cce3\$lut for cells of type $lut. Using template $paramod$3be30a5a9f993377f0c44a54aadf0fabaaafa2c9\$lut for cells of type $lut. Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut. Using template $paramod$18df3812bc12364e5ebcb6c3ed05c0294e4c26fc\$lut for cells of type $lut. Using template $paramod$903bfb3b8ff2a95ced68eefa92dd97bd548db7b1\$lut for cells of type $lut. Using template $paramod$2bde02b8b9e7d4618088fbf4dd7d45ed8df60d20\$lut for cells of type $lut. Using template $paramod$416b7b6a26876a32f662afcb2b99ea9b9c8baca8\$lut for cells of type $lut. Using template $paramod$aa06180ac352044cba83618906fa3360cf0615aa\$lut for cells of type $lut. Using template $paramod$66754b920090fe989284bc0797d5a930436a2de0\$lut for cells of type $lut. Using template $paramod$99f2b19ae05302cea25a16e76420f3ae5aef83b9\$lut for cells of type $lut. Using template $paramod$b4178000258689c4950cbc4ecbfd97b7475eee0f\$lut for cells of type $lut. Using template $paramod$2544b251d66d989c4320ed418292c435e4d2705d\$lut for cells of type $lut. Using template $paramod$c2165fb95198480d04ae129ac9b17201c582f652\$lut for cells of type $lut. Using template $paramod$47575332e0fdaf576eb9eca567ef7e0f0911db91\$lut for cells of type $lut. Using template $paramod$32db4c9f1fc949aa9bfcbd93a9d73241c68dfa86\$lut for cells of type $lut. Using template $paramod$39c9be6aa3afd0cc982f047a71ee1b8ff5c18f3d\$lut for cells of type $lut. Using template $paramod$021904a6d3cd28c5646f5dad6a4a7f12484f0a2e\$lut for cells of type $lut. Using template $paramod$954d97ebaa3c5e304444e84dba0fc4af0822cfec\$lut for cells of type $lut. Using template $paramod$a3533a63e10070005764d6cd65a719cf1eef9698\$lut for cells of type $lut. Using template $paramod$b3326472661fdc7b812e5688b0e7e6c1e8a02a00\$lut for cells of type $lut. Using template $paramod$74126468aaace72876184a46cb47e46a6d4ae807\$lut for cells of type $lut. Using template $paramod$f2eac3381386b9ecc95d140724a90398d1a2bf19\$lut for cells of type $lut. Using template $paramod$4758b3a0d27b377126260368fa74e779acea8540\$lut for cells of type $lut. Using template $paramod$0b882155407a550c277c1350c62de1e07016a18c\$lut for cells of type $lut. Using template $paramod$2c3b20c11ca3d067eff4c2caaf30e7c9ad5cd4b1\$lut for cells of type $lut. Using template $paramod$ad9e952f8b3ae04f51b06e96c8defd513918ccd8\$lut for cells of type $lut. Using template $paramod$68e3d3f27e6a41c3bf8782ac6aac602773fca3a6\$lut for cells of type $lut. Using template $paramod$02a5bb891d1c4f3fa6df7595e62e72cb2aeb9e74\$lut for cells of type $lut. Using template $paramod$6503767725ffcf7ad16e0e10d60e51b1df515827\$lut for cells of type $lut. Using template $paramod$9dbe36982f6b8ca20db05cfcd5650178f13179f3\$lut for cells of type $lut. Using template $paramod$3f8d2779c1578cddfa32829af18964a285c558a9\$lut for cells of type $lut. Using template $paramod$97128c8e71f4612b23a4b06d9993ef384a6c0ebe\$lut for cells of type $lut. Using template $paramod$d52cb446bc89fafcaa49f2b908e540f513a4d760\$lut for cells of type $lut. Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut. Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod$cfbf37299badb827c5c40df39bb2930556c46367\$lut for cells of type $lut. Using template $paramod$85326c33b06102735dac438f0e9bd24d7e9c2d4f\$lut for cells of type $lut. Using template $paramod$2f475f429a646b0881efa2d9980ab6a15e61751c\$lut for cells of type $lut. Using template $paramod$b4b843bbfe0f9f8c7d5242e088ab48ae92aad1cb\$lut for cells of type $lut. Using template $paramod$4be15e4607bebd450adfaf7f162fdba50a9c2ab9\$lut for cells of type $lut. Using template $paramod$64f43dc318f4c77b4186c3ebcba0aa7863e84359\$lut for cells of type $lut. Using template $paramod$00ebdbe2589b8c79566dcbaac62668d02c58fb07\$lut for cells of type $lut. Using template $paramod$3ac59147570c20e97d0ca2fc88acccf2c61c4dc8\$lut for cells of type $lut. Using template $paramod$c5d791b2dd3d8afd456f4384acfd996b0f093f14\$lut for cells of type $lut. Using template $paramod$3047492e26a89986a585d0cb18765b19c46a7824\$lut for cells of type $lut. Using template $paramod$c1b1e295769db1b6655cd9fa7f1823a266fa6d67\$lut for cells of type $lut. Using template $paramod$edb78bf6097bd1610bf429917d83de43c0242af1\$lut for cells of type $lut. Using template $paramod$7489689203c080fe2bdc1890c3de0b7c2b1b5b09\$lut for cells of type $lut. Using template $paramod$609507c437a4959e4ac849d732c034940a1a2117\$lut for cells of type $lut. Using template $paramod$1875a64980687d84476cca9206287369bec7f34d\$lut for cells of type $lut. Using template $paramod$3ae9f1cda205b669870c653a21d45eee50078e98\$lut for cells of type $lut. Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut. Using template $paramod$add9e883962c7421ff9cf2b6033d4a1407a949a9\$lut for cells of type $lut. Using template $paramod$be0d52b4adde38396aa8d181484c99080ee57661\$lut for cells of type $lut. Using template $paramod$a32d9355e964cad7e49a14608b1905218d3a1edf\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$a9be4a8168292a351c95ac88246179f671ce1c87\$lut for cells of type $lut. Using template $paramod$f6679f526a60a0c1a198cb43515c07945a39064b\$lut for cells of type $lut. Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut. Using template $paramod$06457edff985ac2621f32f6418c0f1e49baaf820\$lut for cells of type $lut. Using template $paramod$4510fd209bba60d6262358777611af3f9cb61cb3\$lut for cells of type $lut. Using template $paramod$7fed74f2cef975f9d09dcb0a10cb49d92a5c6372\$lut for cells of type $lut. Using template $paramod$d5d15fdfd4bf86c80cf2b60aef264e01c24bd422\$lut for cells of type $lut. Using template $paramod$46969734f619307bdfb8ca4ad5af273b11115f8d\$lut for cells of type $lut. Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. Using template $paramod$fd162c28b2bebacde3725617f1d8fd3b2af74fa9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. Using template $paramod$85c7f1c03948301cd74969020591aefec4c7026e\$lut for cells of type $lut. Using template $paramod$4f6010b665ae0a9dad0da17d003cad094f3b125b\$lut for cells of type $lut. Using template $paramod$26d61dbbb4a3fbeae4cc735bce01ecfd88aba73b\$lut for cells of type $lut. Using template $paramod$99da62c5d1e98e5c59772fe785351d264a36022e\$lut for cells of type $lut. Using template $paramod$35c99f2ec4da953c239fd93a25af1883d676b374\$lut for cells of type $lut. Using template $paramod$31c6e83feb54a85b90ab5aa922fc78a347dbb89c\$lut for cells of type $lut. Using template $paramod$4c2970170dabd794ae0d59c321dfead6888cd5cf\$lut for cells of type $lut. Using template $paramod$df396b558e71a9f352b2b05b9ffa45354a9e7ca6\$lut for cells of type $lut. Using template $paramod$63b3ffd6e543b0e90905ac46ac405617f2d419f0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut. Using template $paramod$a7e3cbe69f4404dcf382c6eaceb14eca39820e3f\$lut for cells of type $lut. Using template $paramod$653ed1fca2cbea6092fc92115114dddd9158d22d\$lut for cells of type $lut. Using template $paramod$563ad9329518494993cf356d9c4147657223641b\$lut for cells of type $lut. Using template $paramod$2de4c1290f3205dbd0981c23d2ec502f35d07a1b\$lut for cells of type $lut. Using template $paramod$3748372c69162fbf635bee017e3436df2c43d04c\$lut for cells of type $lut. Using template $paramod$71e40ea63245c8f6b1cc20b211b39b427ce373fa\$lut for cells of type $lut. Using template $paramod$0260ba258d9e1a608f5e349a51c65fb9e84b9283\$lut for cells of type $lut. Using template $paramod$898d152e3c89e47b0a43cc4f8545777e36ddd3ea\$lut for cells of type $lut. Using template $paramod$a462117541566384a2f7b7f7d9d41b1139721862\$lut for cells of type $lut. Using template $paramod$39b8c8fb7502b00cbe1f8dd1daa8dec2b5befd08\$lut for cells of type $lut. Using template $paramod$2198eac8c23607f1d24ec209a6dc23be26364398\$lut for cells of type $lut. Using template $paramod$e019cb14313283ce60b57907d30cf3eefa00a93d\$lut for cells of type $lut. Using template $paramod$7933cfc92cabda9fe594c5309ad3f6b3b7ed68e1\$lut for cells of type $lut. Using template $paramod$587c9c27559ae76284a18d7bfaa60e9f2ba5f87f\$lut for cells of type $lut. Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut. Using template $paramod$26918802e6ed329b7afdcbcae3efbad76693779f\$lut for cells of type $lut. Using template $paramod$a6ebbaa6a871fce0ba6b67532ec10e64b7230a4e\$lut for cells of type $lut. Using template $paramod$bede69817e2e368cfc571c971b3ce6211497732f\$lut for cells of type $lut. Using template $paramod$01d1badebdb17f5d737fb2d89d208cb7f0ffab68\$lut for cells of type $lut. Using template $paramod$97aad10eeec1080a92bba752f9b085a6e1a07646\$lut for cells of type $lut. Using template $paramod$581fe280dfb9dbc558694a9668a01071f06d0cba\$lut for cells of type $lut. Using template $paramod$f01e41fa5de8c1ef6b1654fa1a8fa6353864023a\$lut for cells of type $lut. Using template $paramod$599473914bc3ac689be7055f09340760a27068de\$lut for cells of type $lut. Using template $paramod$5f32cb05e8745593351a530ca1124e41655442c6\$lut for cells of type $lut. Using template $paramod$4bae2e883ed1efd2d87504f6ca30e93887cd7bc7\$lut for cells of type $lut. Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. Using template $paramod$7c3227eb2ea5eb3827c84ab62e53dffcb38a18b9\$lut for cells of type $lut. Using template $paramod$de07eb062963514b9c819aacc3e74a1253bffd53\$lut for cells of type $lut. Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut. Using template $paramod$f059a10831dfeb9172d167214a1cf9882570ae5d\$lut for cells of type $lut. Using template $paramod$44c0fe996e6f3f4ba8bae2e194245aa82c30fa47\$lut for cells of type $lut. Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f\$lut for cells of type $lut. Using template $paramod$abc1867b96935d02275105ce32b761b6de109609\$lut for cells of type $lut. Using template $paramod$99fa5fd2276c547e17d8151ce237c123a1909d28\$lut for cells of type $lut. Using template $paramod$f448042cbf43e478e93408e5e83c7e8fa9872fe6\$lut for cells of type $lut. Using template $paramod$b5afa9fe7803265dd86f3240d7e6a4c0b39e059b\$lut for cells of type $lut. Using template $paramod$4beb8658e4bde673aa5dc5ebc1cf9b8df3ae4dc8\$lut for cells of type $lut. Using template $paramod$2357431a20f3891da5d1d21801bc815b057e2dac\$lut for cells of type $lut. Using template $paramod$82a00bf0f959a345aaec45c197de61b70ee9c703\$lut for cells of type $lut. Using template $paramod$3dc8df1b07971bda7726ddf94f6377e60804ab64\$lut for cells of type $lut. Using template $paramod$3eba914fcdb889cf79f644e8e516ea34b1958f4e\$lut for cells of type $lut. Using template $paramod$2dee3fd6f13c981fb3e29fa15149d6201346339e\$lut for cells of type $lut. Using template $paramod$9111d68cf2c15cd98e35433450e2eb92b679070f\$lut for cells of type $lut. Using template $paramod$6d4cc4f82cbeec9f11ee20382d2e8cbca780ab4d\$lut for cells of type $lut. Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut. Using template $paramod$25276620941218706745e8e30698403f5fe815fc\$lut for cells of type $lut. Using template $paramod$3f37efd356116fb56e2aef83e1db05f69a9349b9\$lut for cells of type $lut. Using template $paramod$2901db385db9c9ed336329e529961d8bab9446d5\$lut for cells of type $lut. Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037\$lut for cells of type $lut. Using template $paramod$16459dc2d44f653c326b0e48bbda08f0d51227d1\$lut for cells of type $lut. Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut. Using template $paramod$172fda622523249889ee53d3df68f1b5af6444cd\$lut for cells of type $lut. Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut. Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut. Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut. Using template $paramod$8266cf8e475d26c19cb85a5a78b5b86b3b4c3bc9\$lut for cells of type $lut. Using template $paramod$a63014c5e66a56dc5e61848489c809a59ebe7c34\$lut for cells of type $lut. Using template $paramod$0356e7120d5ef5b23745ea9a0e3299cea5209599\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut. Using template $paramod$cf93df6a751c015d454aef52e32716809f254f3e\$lut for cells of type $lut. Using template $paramod$1d4e07f01cbdd8c141b2d32b06395e0766a918e1\$lut for cells of type $lut. Using template $paramod$1cc3573fc38464bd5eee925a03019a5abc12686d\$lut for cells of type $lut. Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut. Using template $paramod$041d8da78ef6962347d0fffa220ffed87c89d4fd\$lut for cells of type $lut. Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut. Using template $paramod$6a9b42dd2737c91073e6a695b8ac858c4a8587d7\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$7c085cdbf0919cd3ad402d9495d97f0d71e4db93\$lut for cells of type $lut. Using template $paramod$0c845bc01566011ca86cb05dae2d5f3ad02b38d3\$lut for cells of type $lut. Using template $paramod$8863cacda5a7abe69583309d0b7c476d2498e468\$lut for cells of type $lut. Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f\$lut for cells of type $lut. Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut. Using template $paramod$23da582b86241546eace0c8bedadb42614eea4c1\$lut for cells of type $lut. Using template $paramod$99198f069916089f682c8c9ab51f54ad804bbcc4\$lut for cells of type $lut. Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut. Using template $paramod$69cdd61f52c7066219b4775e909bf69f1c5bb8bd\$lut for cells of type $lut. Using template $paramod$6891203b84e6673470aebe7b3ca14e65c7e30601\$lut for cells of type $lut. Using template $paramod$e4e09968bccb8665ed1d2532c6979f937ac17a70\$lut for cells of type $lut. Using template $paramod$f9c81b962a1f11539ade42d0381fc20910f0e361\$lut for cells of type $lut. Using template $paramod$542e2fdf39f66ee0d9684372297ec1f9c72087d5\$lut for cells of type $lut. Using template $paramod$2652a5fa98784a3fa88f71a554d4e8679646c901\$lut for cells of type $lut. Using template $paramod$d80c9b99dacb354fa564a6fcc23ca30753bf6623\$lut for cells of type $lut. Using template $paramod$3f49790c1a630e24be73b29bdc5b4f0a5289d171\$lut for cells of type $lut. Using template $paramod$efc60783c939ae41b2f3555af407b17c007b27f8\$lut for cells of type $lut. Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707\$lut for cells of type $lut. Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut. Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut. Using template $paramod$4bb876346cbc5d13aef9f873277f12d388c5d51a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. Using template $paramod$0517fb01044da31a3b22edd53ea8ef5543f8966c\$lut for cells of type $lut. Using template $paramod$7bd891a4dd7bedcda59febd0a80cb966e32b529a\$lut for cells of type $lut. Using template $paramod$9e394303e290a474880b56f98766417009256d93\$lut for cells of type $lut. Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut. Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut. Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476\$lut for cells of type $lut. Using template $paramod$ebd2b6cc033eef093962735d53d63caaef92a499\$lut for cells of type $lut. Using template $paramod$60ed61082d71c633be3584267d2b82518936d2bd\$lut for cells of type $lut. Using template $paramod$83f73e18d12eec6b707efa72adda1fb2038938b7\$lut for cells of type $lut. Using template $paramod$1f8d11827cfe27dfc297d495f53d8a969cf90bec\$lut for cells of type $lut. Using template $paramod$80988c43f318602d7fbaedec0644aee2e766b204\$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. Using template $paramod$6b5191f4b2f0510664142e127fa5456923c730e7\$lut for cells of type $lut. Using template $paramod$4c5119bb88a973ab4f4242c30fcba8815107791b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut. Using template $paramod$f52df4b90f46c2ab9e801e1f39516c9cb1bb6ae7\$lut for cells of type $lut. Using template $paramod$3238e658c9406d1ce6d0fb872e3850470bfbad27\$lut for cells of type $lut. Using template $paramod$fef3c7c7c35003319050b073aba7ca913533bd9b\$lut for cells of type $lut. Using template $paramod$36029a484c4db41fcf0d3e0169beb2a352708863\$lut for cells of type $lut. Using template $paramod$8bfc6dd665a091a96bc14e081a8935d079651aa7\$lut for cells of type $lut. Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut. Using template $paramod$c5530d5da7dea9ed65ab6ff0fe28191b981c1937\$lut for cells of type $lut. Using template $paramod$8c7278cdec599cbc2866d6fba884b16264e2dde5\$lut for cells of type $lut. Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut. Using template $paramod$e4b832d686d12318ec0715f027fe549b42e45c20\$lut for cells of type $lut. Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut. Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut. Using template $paramod$833582361e14b3ee2e66ad676022ab35d7aa7e28\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$8cbea7472fe8ec8b0d9b301f17edad7f1c398048\$lut for cells of type $lut. Using template $paramod$4d5fa0c21aaa9745a301eda7465c650b5896bed0\$lut for cells of type $lut. Using template $paramod$92313a79c645caaee997f61828723c5df8d65bfa\$lut for cells of type $lut. Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. Using template $paramod$00dfa99b7aecc2e72490719b192118cbd6549a2c\$lut for cells of type $lut. Using template $paramod$f94cf08026d21db794b98b1a8efaec5f34ff8975\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101011 for cells of type $lut. Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut. Using template $paramod$d4fae2c0d9ad2966369cd4e39b81c71bcd1327c9\$lut for cells of type $lut. Using template $paramod$d50aaf7bc91b84437dde85e30486261cdbeeccac\$lut for cells of type $lut. Using template $paramod$17c27ffdda03355f95b2ba5edc73ca082237c935\$lut for cells of type $lut. Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut. Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut. Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut. Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut. Using template $paramod$4da2782c2e024b3eded45331a6607870b9d0254f\$lut for cells of type $lut. Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110100 for cells of type $lut. Using template $paramod$bab0ea0d717fb03593996e2a9f716c39db2520fb\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$5c6bc258377827df3257d2ecbf87d53a2377fcda\$lut for cells of type $lut. Using template $paramod$fdb61c7c613ba40ec1f7cb3a6e1f35d0fc57666f\$lut for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. Using template $paramod$1de2f8bf3cf20e1a0d108540aad77f5d1061f20d\$lut for cells of type $lut. Using template $paramod$8be603794459732f9a374f76041b510fc63b115b\$lut for cells of type $lut. Using template $paramod$de5328836923c44c99600bcab852423201246f91\$lut for cells of type $lut. Using template $paramod$fddfaafad20e385d20971828336f8fb14f3d4f32\$lut for cells of type $lut. Using template $paramod$2991ce5fd02924db4f85641df086c8f9e75470e5\$lut for cells of type $lut. Using template $paramod$aae9ca9917d459d5338463ab9843dad4578b88dd\$lut for cells of type $lut. Using template $paramod$9f2f146893d269900bb68ba0244b254b88c2c459\$lut for cells of type $lut. Using template $paramod$f9b715fbf1040e81e900b2461c2390d17ed5e988\$lut for cells of type $lut. Using template $paramod$97ab785d669e270c3b8f40f252565ab3b3008b09\$lut for cells of type $lut. No more expansions possible. <suppressed ~11868 debug messages> 20.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in processorci_top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130603.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130497.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130447.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130682.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23547.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22917.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$21607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$21349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$21224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$flatten\Controller.\Interpreter.$procmux$2144.Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19596.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18977.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18973.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$flatten\Controller.\Interpreter.$procmux$2144.Y[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18221.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16619.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$flatten\Controller.\Interpreter.$procmux$2144.Y[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16039.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16039.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16039.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$15776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$15750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$15705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$15705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$15628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$15628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$flatten\Controller.\Interpreter.$procmux$2144.Y[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$15465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$15388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$15242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$13832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$13832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$13680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$13530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13464.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$13141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$13102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$13009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$flatten\Controller.\Interpreter.$procmux$2144.Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$12838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$12606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$12606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$12598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$12572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$12213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$11869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$11861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$11849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$11849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$11823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$11792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$11741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$11733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$10955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$10955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$10955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$10937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$10897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$130421$lut$auto$abc9_ops.cc:595:break_scc$40066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$flatten\Controller.\Interpreter.$procmux$2144.Y[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10333.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10385.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10656.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10774.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$10791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$10808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$10873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$10897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$10937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$10959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$11010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$11028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11721.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$11741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$11792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$11823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$11861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$11869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$11895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11901.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12424.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12451.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12572.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$12576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$12653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$12660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$13610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$13649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13744.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$13765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13836.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$13980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14033.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14207.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14279.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14682.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$14738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$14983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$14992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15075.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$15242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15355.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$15634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$15793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$15852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$15935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15945.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$15965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16039.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16249.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16353.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$16761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$16977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$16984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$16996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17195.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$17879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$17885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18083.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18179.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18408.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18723.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$18973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$18989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$18998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19013.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19023.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$19088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$19140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$19194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19293.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$19517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$19521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$19528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19575.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$19626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$19733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$19791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$19860.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$19867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$19901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$19914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$19937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20259.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20575.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20883.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$20959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$20986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21081.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$21224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$21239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$21269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$21622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$21727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$21739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$21973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$21985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$21985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22009.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$22895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$22925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23362.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23757.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$23835.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23901.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$23984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$23998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24391.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24403.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$24847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$24896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$24958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$aiger130420$24997.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$25023.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$25031.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$25064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$25100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$25146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$auto$fsm_map.cc:170:map_fsm$5954[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$13222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$20717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$11039.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$12490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$auto$opt_dff.cc:219:make_patterns_logic$6343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$auto$opt_dff.cc:219:make_patterns_logic$9264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut$auto$rtlil.cc:2724:Not$6386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130761.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$10637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$flatten\Controller.\Interpreter.$procmux$2144.Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$20371.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$23512.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$flatten\Controller.\Interpreter.$procmux$2144.Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$22705.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$13386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$22329.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$auto$opt_dff.cc:219:make_patterns_logic$6252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$auto$fsm_map.cc:170:map_fsm$5954[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$auto$opt_dff.cc:219:make_patterns_logic$6264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3269.Y[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3269.Y[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3269.Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3269.Y[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3269.Y[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3269.Y[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3269.Y[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$flatten\mriscvcore_inst.\MEMORY_INTERFACE_inst.$procmux$3269.Y[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$17289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$17885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut$aiger130420$18255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut\mriscvcore_inst.MEMORY_INTERFACE_inst.Rdata_mem[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$130421$lut$aiger130420$14992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$130421$lut\mriscvcore_inst.UTILITY_inst.PC_N[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130488.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130505.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130591.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130703.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130529.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130547.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130599.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130694.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130593.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$130421$lut$aiger130420$13423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Removed 0 unused cells and 12819 unused wires. 20.45. Executing AUTONAME pass. Renamed 316160 objects in module processorci_top (177 iterations). <suppressed ~19887 debug messages> 20.46. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `processorci_top'. Setting top module to processorci_top. 20.46.1. Analyzing design hierarchy.. Top module: \processorci_top 20.46.2. Analyzing design hierarchy.. Top module: \processorci_top Removed 0 unused modules. 20.47. Printing statistics. === processorci_top === Number of wires: 9565 Number of wire bits: 25093 Number of public wires: 9565 Number of public wire bits: 25093 Number of ports: 10 Number of port bits: 10 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 11816 $scopeinfo 38 CCU2C 246 L6MUX21 844 LUT4 6845 PFUMX 1862 TRELLIS_DPR16X4 1060 TRELLIS_FF 921 20.48. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Found and reported 0 problems. 20.49. Executing JSON backend. Warnings: 109 unique messages, 109 total End of script. Logfile hash: cbccd90ba4, CPU: user 38.90s system 0.34s, MEM: 293.53 MB peak Time spent: 26% 1x abc9_exe (10 sec), 16% 11x techmap (6 sec), ... /eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \ --lpf /eda/processor_ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \ --speed 6 --lpf-allow-unconstrained --ignore-loops /eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config --bit colorlight_i9.bit [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) [Pipeline] dir Running in /var/jenkins_home/workspace/mriscv/mriscv [Pipeline] { [Pipeline] echo Flashing FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mriscv -b colorlight_i9 -l Final configuration file generated at /var/jenkins_home/workspace/mriscv/mriscv/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 (null) Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE Loading: [==== ] 7.96% Loading: [======== ] 15.63% Loading: [============ ] 23.29% Loading: [================ ] 30.96% Loading: [==================== ] 38.92% Loading: [======================== ] 46.88% Loading: [============================ ] 54.84% Loading: [================================ ] 62.80% Loading: [==================================== ] 70.17% Loading: [======================================== ] 78.13% Loading: [=========================================== ] 85.80% Loading: [=============================================== ] 93.76% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test colorlight_i9) [Pipeline] echo Testing FPGA colorlight_i9. [Pipeline] dir Running in /var/jenkins_home/workspace/mriscv/mriscv [Pipeline] { [Pipeline] sh + echo Test for FPGA in /dev/ttyACM0 Test for FPGA in /dev/ttyACM0 [Pipeline] sh + python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0 Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'} [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Final configuration file generated at /var/jenkins_home/workspace/mriscv/mriscv/build_digilent_arty_a7_100t.tcl Makefile executed successfully. Makefile output: Building the Design... /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/mriscv/mriscv/build_digilent_arty_a7_100t.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096" ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source /var/jenkins_home/workspace/mriscv/mriscv/build_digilent_arty_a7_100t.tcl # read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1307.602 ; gain = 0.023 ; free physical = 2566 ; free virtual = 24738 # read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v # read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v # read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v # read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v # read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v # read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v # read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v # read_verilog /var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v # read_verilog /eda/processor_ci/rtl/mriscv.v # read_verilog /eda/processor-ci-controller/modules/uart.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v # read_verilog /eda/processor-ci-controller/src/fifo.v # read_verilog /eda/processor-ci-controller/src/reset.v # read_verilog /eda/processor-ci-controller/src/clk_divider.v # read_verilog /eda/processor-ci-controller/src/memory.v # read_verilog /eda/processor-ci-controller/src/interpreter.v # read_verilog /eda/processor-ci-controller/src/controller.v # set ID [lindex $argv 0] # set CLOCK_FREQ [lindex $argv 1] # set MEMORY_SIZE [lindex $argv 2] # set HIGH_CLK 1 # read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc" # set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] # synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE \ # -verilog_define $HIGH_CLK Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096 -verilog_define 1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 3390324 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2032.301 ; gain = 403.629 ; free physical = 1340 ; free virtual = 23523 --------------------------------------------------------------------------------- INFO: [Synth 8-11241] undeclared symbol 'rdw_rsrn', assumed default net type 'wire' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:130] INFO: [Synth 8-11241] undeclared symbol 'enable_pc', assumed default net type 'wire' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:204] INFO: [Synth 8-11241] undeclared symbol 'done_exec', assumed default net type 'wire' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:223] INFO: [Synth 8-11241] undeclared symbol 'enable_exec', assumed default net type 'wire' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:231] INFO: [Synth 8-11241] undeclared symbol 'enable_exec_mem', assumed default net type 'wire' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:232] CRITICAL WARNING: [Synth 8-9339] data object 'reset_o' is already declared [/eda/processor_ci/rtl/mriscv.v:166] INFO: [Synth 8-6826] previous declaration of 'reset_o' is from here [/eda/processor_ci/rtl/mriscv.v:29] CRITICAL WARNING: [Synth 8-11152] second declaration of 'reset_o' is ignored [/eda/processor_ci/rtl/mriscv.v:166] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16] WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15] WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16] WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17] WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84] WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85] INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/mriscv.v:1] INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer Parameter ID bound to: 0 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1] Parameter COUNTER_BITS bound to: 32 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1] INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter ID bound to: 0 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213] INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1] Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1] INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1] INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1] Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1] WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268] INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1] INFO: [Synth 8-6157] synthesizing module 'mriscvcore' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:10] INFO: [Synth 8-6157] synthesizing module 'MEMORY_INTERFACE' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:3] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:225] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:256] INFO: [Synth 8-6155] done synthesizing module 'MEMORY_INTERFACE' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:3] INFO: [Synth 8-6157] synthesizing module 'DECO_INSTR' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:3] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:28] INFO: [Synth 8-6155] done synthesizing module 'DECO_INSTR' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/DECO_INSTR/DECO_INSTR.v:3] INFO: [Synth 8-6157] synthesizing module 'REG_FILE' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:40] INFO: [Synth 8-6157] synthesizing module 'true_dpram_sclk' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:17] INFO: [Synth 8-6155] done synthesizing module 'true_dpram_sclk' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:17] INFO: [Synth 8-6155] done synthesizing module 'REG_FILE' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/REG_FILE/REG_FILE.v:40] INFO: [Synth 8-6157] synthesizing module 'ALU' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:3] INFO: [Synth 8-6157] synthesizing module 'ALU_add' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:387] Parameter REG_ALU bound to: 1'b1 Parameter REG_OUT bound to: 1'b1 INFO: [Synth 8-6155] done synthesizing module 'ALU_add' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:387] INFO: [Synth 8-6157] synthesizing module 'ALU_sub' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:419] Parameter REG_ALU bound to: 1'b1 Parameter REG_OUT bound to: 1'b1 INFO: [Synth 8-6155] done synthesizing module 'ALU_sub' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:419] INFO: [Synth 8-6157] synthesizing module 'ALU_and' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:450] Parameter REG_ALU bound to: 1'b1 Parameter REG_OUT bound to: 1'b1 INFO: [Synth 8-6155] done synthesizing module 'ALU_and' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:450] INFO: [Synth 8-6157] synthesizing module 'ALU_xor' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:481] Parameter REG_ALU bound to: 1'b1 Parameter REG_OUT bound to: 1'b1 INFO: [Synth 8-6155] done synthesizing module 'ALU_xor' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:481] INFO: [Synth 8-6157] synthesizing module 'ALU_or' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:512] Parameter REG_ALU bound to: 1'b1 Parameter REG_OUT bound to: 1'b1 INFO: [Synth 8-6155] done synthesizing module 'ALU_or' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:512] INFO: [Synth 8-6157] synthesizing module 'ALU_beq' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:543] Parameter REG_ALU bound to: 1'b1 Parameter REG_OUT bound to: 1'b1 INFO: [Synth 8-6155] done synthesizing module 'ALU_beq' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:543] INFO: [Synth 8-6157] synthesizing module 'ALU_blt' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:561] Parameter REG_ALU bound to: 1'b1 Parameter REG_OUT bound to: 1'b1 INFO: [Synth 8-6155] done synthesizing module 'ALU_blt' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:561] INFO: [Synth 8-6157] synthesizing module 'ALU_bltu' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:579] Parameter REG_ALU bound to: 1'b1 Parameter REG_OUT bound to: 1'b1 INFO: [Synth 8-6155] done synthesizing module 'ALU_bltu' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:579] INFO: [Synth 8-6157] synthesizing module 'ALU_sXXx' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:597] Parameter REG_ALU bound to: 1'b1 Parameter REG_OUT bound to: 1'b1 INFO: [Synth 8-6155] done synthesizing module 'ALU_sXXx' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:597] INFO: [Synth 8-6155] done synthesizing module 'ALU' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/ALU/ALU.v:3] INFO: [Synth 8-6157] synthesizing module 'IRQ' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:114] INFO: [Synth 8-6157] synthesizing module 'Count' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:41] INFO: [Synth 8-6157] synthesizing module 'divM' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:3] INFO: [Synth 8-6155] done synthesizing module 'divM' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:3] INFO: [Synth 8-6155] done synthesizing module 'Count' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:41] INFO: [Synth 8-6155] done synthesizing module 'IRQ' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:114] INFO: [Synth 8-6157] synthesizing module 'MULT' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:105] INFO: [Synth 8-6157] synthesizing module 'FSM_Booth' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:3] INFO: [Synth 8-6155] done synthesizing module 'FSM_Booth' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:3] INFO: [Synth 8-6157] synthesizing module 'Alg_Booth' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:47] INFO: [Synth 8-6155] done synthesizing module 'Alg_Booth' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:47] INFO: [Synth 8-6157] synthesizing module 'FSM_Booth__parameterized0' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:3] Parameter BITS_BOOTH bound to: 17 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FSM_Booth__parameterized0' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:3] INFO: [Synth 8-6157] synthesizing module 'Alg_Booth__parameterized0' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:47] Parameter SWORD bound to: 18 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Alg_Booth__parameterized0' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:47] INFO: [Synth 8-6155] done synthesizing module 'MULT' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:105] INFO: [Synth 8-6157] synthesizing module 'UTILITY' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:3] INFO: [Synth 8-6155] done synthesizing module 'UTILITY' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/UTILITIES/UTILITY.v:3] INFO: [Synth 8-6157] synthesizing module 'FSM' [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:3] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:77] INFO: [Synth 8-6155] done synthesizing module 'FSM' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/FSM/FSM.v:3] INFO: [Synth 8-6155] done synthesizing module 'mriscvcore' (0#1) [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/mriscvcore.v:10] WARNING: [Synth 8-7071] port 'outirr' of module 'mriscvcore' is unconnected for instance 'mriscvcore_inst' [/eda/processor_ci/rtl/mriscv.v:98] WARNING: [Synth 8-7023] instance 'mriscvcore_inst' of module 'mriscvcore' has 22 connections declared, but only 21 given [/eda/processor_ci/rtl/mriscv.v:98] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1] Parameter CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1] WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/mriscv.v:170] WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/mriscv.v:170] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/mriscv.v:170] INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/mriscv.v:1] WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25] WARNING: [Synth 8-6014] Unused sequential element rdu_reg was removed. [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v:324] WARNING: [Synth 8-6014] Unused sequential element timer_count_reg was removed. [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/IRQ/IRQ.v:151] WARNING: [Synth 8-6014] Unused sequential element aux_reg was removed. [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:79] WARNING: [Synth 8-6014] Unused sequential element aux_reg was removed. [/var/jenkins_home/workspace/mriscv/mriscv/mriscvcore/MULT/MULT.v:79] WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/mriscv.v:21] WARNING: [Synth 8-7129] Port busy_mem in module FSM is either unconnected or has no load WARNING: [Synth 8-7129] Port is_exec in module FSM is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[31] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[30] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[29] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[28] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[27] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[26] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[25] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[24] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[23] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[22] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[21] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[20] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[19] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[18] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[17] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[16] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[15] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[14] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[13] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[12] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[11] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[10] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[9] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[8] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[7] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[6] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port oper2[5] in module ALU_sXXx is either unconnected or has no load WARNING: [Synth 8-7129] Port clk in module ALU_bltu is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module ALU_bltu is either unconnected or has no load WARNING: [Synth 8-7129] Port clk in module ALU_blt is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module ALU_blt is either unconnected or has no load WARNING: [Synth 8-7129] Port clk in module ALU_beq is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module ALU_beq is either unconnected or has no load WARNING: [Synth 8-7129] Port rst in module true_dpram_sclk is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2131.270 ; gain = 502.598 ; free physical = 1229 ; free virtual = 23413 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2149.082 ; gain = 520.410 ; free physical = 1226 ; free virtual = 23411 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2149.082 ; gain = 520.410 ; free physical = 1226 ; free virtual = 23411 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2149.082 ; gain = 0.000 ; free physical = 1226 ; free virtual = 23411 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2297.832 ; gain = 0.000 ; free physical = 1195 ; free virtual = 23379 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2297.867 ; gain = 0.000 ; free physical = 1189 ; free virtual = 23374 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1102 ; free virtual = 23286 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1102 ; free virtual = 23286 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1102 ; free virtual = 23286 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'MEMORY_INTERFACE' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'FSM_Booth' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'FSM_Booth__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 READ | 001 | 0001 COPY_READ_BUFFER | 010 | 0100 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 COPY_WRITE_BUFFER | 001 | 0100 WRITE | 010 | 0001 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 0001 | 00 iSTATE0 | 0010 | 01 iSTATE1 | 0100 | 10 iSTATE2 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- reposo | 000 | 0000 SR1 | 001 | 0010 SR2 | 010 | 0011 SW0 | 011 | 0101 SW1 | 100 | 0110 SW2 | 101 | 0111 SWB | 110 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'MEMORY_INTERFACE' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE1 | 00 | 00 iSTATE | 01 | 01 iSTATE0 | 10 | 10 iSTATE2 | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'FSM_Booth' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE1 | 00 | 00 iSTATE | 01 | 01 iSTATE0 | 10 | 10 iSTATE2 | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'FSM_Booth__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RESET_COUNTER | 00 | 01 IDLE | 01 | 10 INIT | 10 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1097 ; free virtual = 23283 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 3 3 Input 64 Bit Adders := 1 4 Input 36 Bit Adders := 1 2 Input 33 Bit Adders := 1 2 Input 32 Bit Adders := 14 3 Input 32 Bit Adders := 1 2 Input 24 Bit Adders := 2 3 Input 18 Bit Adders := 1 2 Input 18 Bit Adders := 1 3 Input 17 Bit Adders := 2 2 Input 17 Bit Adders := 4 2 Input 10 Bit Adders := 2 2 Input 8 Bit Adders := 1 2 Input 6 Bit Adders := 4 2 Input 5 Bit Adders := 6 2 Input 4 Bit Adders := 2 2 Input 3 Bit Adders := 2 +---XORs : 2 Input 32 Bit XORs := 1 2 Input 1 Bit XORs := 1 +---Registers : 64 Bit Registers := 3 37 Bit Registers := 1 35 Bit Registers := 2 33 Bit Registers := 1 32 Bit Registers := 40 24 Bit Registers := 5 18 Bit Registers := 1 17 Bit Registers := 2 12 Bit Registers := 1 10 Bit Registers := 2 8 Bit Registers := 11 6 Bit Registers := 1 5 Bit Registers := 4 4 Bit Registers := 4 3 Bit Registers := 2 2 Bit Registers := 3 1 Bit Registers := 45 +---RAMs : 32K Bit (1024 X 32 bit) RAMs := 2 1024 Bit (32 X 32 bit) RAMs := 1 64 Bit (8 X 8 bit) RAMs := 2 +---Muxes : 4 Input 64 Bit Muxes := 1 2 Input 64 Bit Muxes := 2 48 Input 64 Bit Muxes := 2 3 Input 37 Bit Muxes := 1 6 Input 37 Bit Muxes := 1 4 Input 37 Bit Muxes := 1 2 Input 37 Bit Muxes := 1 2 Input 36 Bit Muxes := 1 3 Input 35 Bit Muxes := 2 6 Input 35 Bit Muxes := 2 4 Input 35 Bit Muxes := 2 2 Input 35 Bit Muxes := 2 2 Input 34 Bit Muxes := 2 2 Input 32 Bit Muxes := 45 5 Input 32 Bit Muxes := 2 3 Input 32 Bit Muxes := 3 4 Input 32 Bit Muxes := 4 11 Input 32 Bit Muxes := 1 12 Input 32 Bit Muxes := 1 26 Input 32 Bit Muxes := 1 10 Input 32 Bit Muxes := 1 48 Input 24 Bit Muxes := 1 2 Input 24 Bit Muxes := 4 2 Input 16 Bit Muxes := 2 2 Input 12 Bit Muxes := 9 2 Input 9 Bit Muxes := 1 48 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 4 24 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 2 2 Input 6 Bit Muxes := 4 3 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 27 11 Input 5 Bit Muxes := 1 3 Input 5 Bit Muxes := 1 9 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 3 Input 4 Bit Muxes := 2 5 Input 4 Bit Muxes := 1 11 Input 4 Bit Muxes := 2 26 Input 4 Bit Muxes := 1 5 Input 3 Bit Muxes := 4 2 Input 3 Bit Muxes := 7 26 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 3 6 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 25 48 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 8 3 Input 2 Bit Muxes := 2 9 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 96 48 Input 1 Bit Muxes := 22 3 Input 1 Bit Muxes := 7 4 Input 1 Bit Muxes := 5 5 Input 1 Bit Muxes := 12 7 Input 1 Bit Muxes := 8 26 Input 1 Bit Muxes := 3 6 Input 1 Bit Muxes := 1 8 Input 1 Bit Muxes := 9 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met WARNING: [Synth 8-7129] Port busy_mem in module FSM is either unconnected or has no load WARNING: [Synth 8-7129] Port is_exec in module FSM is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:24 ; elapsed = 00:01:25 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1053 ; free virtual = 23262 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------+---------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+---------------------+---------------+----------------+ |Interpreter | memory_mux_selector | 256x1 | LUT | |Interpreter | memory_mux_selector | 256x1 | LUT | +------------+---------------------+---------------+----------------+ Block RAM: Preliminary Mapping Report (see note below) +----------------+--------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +----------------+--------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |mriscvcore_inst | REG_FILE_inst/MEM_FILE/ram_reg | 32 x 32(READ_FIRST) | W | R | 32 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +----------------+--------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. Distributed RAM: Preliminary Mapping Report (see note below) +----------------+------------------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +----------------+------------------------------------+-----------+----------------------+------------------+ |processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |processorci_top | Controller/Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |processorci_top | Controller/Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | +----------------+------------------------------------+-----------+----------------------+------------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:35 ; elapsed = 00:01:37 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1051 ; free virtual = 23260 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:49 ; elapsed = 00:01:51 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1059 ; free virtual = 23268 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +----------------+--------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +----------------+--------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |mriscvcore_inst | REG_FILE_inst/MEM_FILE/ram_reg | 32 x 32(READ_FIRST) | W | R | 32 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +----------------+--------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Distributed RAM: Final Mapping Report +----------------+------------------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +----------------+------------------------------------+-----------+----------------------+------------------+ |processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |processorci_top | Controller/Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |processorci_top | Controller/Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | +----------------+------------------------------------+-----------+----------------------+------------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-7052] The timing for the instance mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:01:55 ; elapsed = 00:01:57 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1057 ; free virtual = 23266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:02:06 ; elapsed = 00:02:08 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1060 ; free virtual = 23269 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:02:06 ; elapsed = 00:02:08 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1060 ; free virtual = 23269 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1060 ; free virtual = 23269 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1060 ; free virtual = 23269 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1060 ; free virtual = 23269 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1060 ; free virtual = 23269 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 2| |2 |CARRY4 | 276| |3 |LUT1 | 159| |4 |LUT2 | 472| |5 |LUT3 | 584| |6 |LUT4 | 444| |7 |LUT5 | 298| |8 |LUT6 | 1096| |9 |MUXF7 | 37| |10 |RAM256X1S | 256| |11 |RAM32M | 2| |12 |RAM32X1D | 4| |13 |RAMB36E1 | 1| |14 |FDRE | 1548| |15 |FDSE | 15| |16 |IBUF | 2| |17 |OBUF | 1| |18 |OBUFT | 2| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1060 ; free virtual = 23269 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 35 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:02:02 ; elapsed = 00:02:05 . Memory (MB): peak = 2297.867 ; gain = 520.410 ; free physical = 1060 ; free virtual = 23269 Synthesis Optimization Complete : Time (s): cpu = 00:02:09 ; elapsed = 00:02:11 . Memory (MB): peak = 2297.867 ; gain = 669.195 ; free physical = 1060 ; free virtual = 23269 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2297.867 ; gain = 0.000 ; free physical = 1344 ; free virtual = 23553 INFO: [Netlist 29-17] Analyzing 576 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2361.863 ; gain = 0.000 ; free physical = 1351 ; free virtual = 23560 INFO: [Project 1-111] Unisim Transformation Summary: A total of 262 instances were transformed. RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances Synth Design complete | Checksum: 806e8896 INFO: [Common 17-83] Releasing license: Synthesis 117 Infos, 125 Warnings, 4 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:02:28 ; elapsed = 00:02:25 . Memory (MB): peak = 2361.898 ; gain = 1054.297 ; free physical = 1337 ; free virtual = 23546 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2050.420; main = 1758.843; forked = 434.457 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3248.125; main = 2361.867; forked = 982.305 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2425.895 ; gain = 63.996 ; free physical = 1343 ; free virtual = 23553 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1ef27351b Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2530.707 ; gain = 104.812 ; free physical = 1285 ; free virtual = 23494 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 1ef27351b Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2780.582 ; gain = 0.000 ; free physical = 1012 ; free virtual = 23222 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1ef27351b Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2780.582 ; gain = 0.000 ; free physical = 1012 ; free virtual = 23222 Phase 1 Initialization | Checksum: 1ef27351b Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2780.582 ; gain = 0.000 ; free physical = 1012 ; free virtual = 23222 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 1ef27351b Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2780.582 ; gain = 0.000 ; free physical = 1012 ; free virtual = 23221 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 1ef27351b Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2780.582 ; gain = 0.000 ; free physical = 1012 ; free virtual = 23221 Phase 2 Timer Update And Timing Data Collection | Checksum: 1ef27351b Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2780.582 ; gain = 0.000 ; free physical = 1012 ; free virtual = 23221 Phase 3 Retarget INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 7 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 17fc5446e Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2780.582 ; gain = 0.000 ; free physical = 1012 ; free virtual = 23221 Retarget | Checksum: 17fc5446e INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 6 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 141701c09 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.98 . Memory (MB): peak = 2780.582 ; gain = 0.000 ; free physical = 1012 ; free virtual = 23221 Constant propagation | Checksum: 141701c09 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 1249ea0bd Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2780.582 ; gain = 0.000 ; free physical = 1011 ; free virtual = 23221 Sweep | Checksum: 1249ea0bd INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 1249ea0bd Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2812.598 ; gain = 32.016 ; free physical = 999 ; free virtual = 23209 BUFG optimization | Checksum: 1249ea0bd INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 1249ea0bd Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2812.598 ; gain = 32.016 ; free physical = 998 ; free virtual = 23207 Shift Register Optimization | Checksum: 1249ea0bd INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 1249ea0bd Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2812.598 ; gain = 32.016 ; free physical = 994 ; free virtual = 23203 Post Processing Netlist | Checksum: 1249ea0bd INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 129bae359 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2812.598 ; gain = 32.016 ; free physical = 1001 ; free virtual = 23210 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2812.598 ; gain = 0.000 ; free physical = 1007 ; free virtual = 23216 Phase 9.2 Verifying Netlist Connectivity | Checksum: 129bae359 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2812.598 ; gain = 32.016 ; free physical = 1007 ; free virtual = 23216 Phase 9 Finalization | Checksum: 129bae359 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2812.598 ; gain = 32.016 ; free physical = 1006 ; free virtual = 23216 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 4 | 6 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 129bae359 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2812.598 ; gain = 32.016 ; free physical = 1006 ; free virtual = 23215 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2812.598 ; gain = 0.000 ; free physical = 1005 ; free virtual = 23214 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2 Ending PowerOpt Patch Enables Task | Checksum: 129bae359 Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1007 ; free virtual = 23216 Ending Power Optimization Task | Checksum: 129bae359 Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2928.621 ; gain = 116.023 ; free physical = 1007 ; free virtual = 23216 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 129bae359 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1007 ; free virtual = 23216 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1007 ; free virtual = 23216 Ending Netlist Obfuscation Task | Checksum: 129bae359 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1007 ; free virtual = 23216 INFO: [Common 17-83] Releasing license: Implementation 24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 2928.621 ; gain = 566.723 ; free physical = 1007 ; free virtual = 23216 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1002 ; free virtual = 23211 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: bb7ce5c3 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1001 ; free virtual = 23211 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1001 ; free virtual = 23210 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 120c36afa Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1003 ; free virtual = 23212 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1476cd24a Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1002 ; free virtual = 23212 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1476cd24a Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1002 ; free virtual = 23212 Phase 1 Placer Initialization | Checksum: 1476cd24a Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1000 ; free virtual = 23210 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 13e6b8d7b Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1000 ; free virtual = 23209 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1bb18ff8b Time (s): cpu = 00:00:17 ; elapsed = 00:00:11 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 998 ; free virtual = 23208 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1bb18ff8b Time (s): cpu = 00:00:17 ; elapsed = 00:00:11 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 998 ; free virtual = 23207 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 216b04441 Time (s): cpu = 00:01:06 ; elapsed = 00:00:41 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 969 ; free virtual = 23179 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 68 LUTNM shape to break, 150 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 34, two critical 34, total 68, new lutff created 3 INFO: [Physopt 32-1138] End 1 Pass. Optimized 131 nets or LUTs. Breaked 68 LUTs, combined 63 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 985 ; free virtual = 23194 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 68 | 63 | 131 | 0 | 1 | 00:00:01 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 68 | 63 | 131 | 0 | 9 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1bb42a2b5 Time (s): cpu = 00:01:10 ; elapsed = 00:00:44 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 984 ; free virtual = 23194 Phase 2.4 Global Placement Core | Checksum: 10eb1536c Time (s): cpu = 00:01:44 ; elapsed = 00:01:02 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 982 ; free virtual = 23192 Phase 2 Global Placement | Checksum: 10eb1536c Time (s): cpu = 00:01:44 ; elapsed = 00:01:02 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 982 ; free virtual = 23192 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: c91e243b Time (s): cpu = 00:01:47 ; elapsed = 00:01:03 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 982 ; free virtual = 23192 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b7d79388 Time (s): cpu = 00:01:53 ; elapsed = 00:01:07 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 982 ; free virtual = 23192 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1b28e29ad Time (s): cpu = 00:01:53 ; elapsed = 00:01:07 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 982 ; free virtual = 23192 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 2035a2d93 Time (s): cpu = 00:01:54 ; elapsed = 00:01:07 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 982 ; free virtual = 23192 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 20e3b4ac8 Time (s): cpu = 00:02:08 ; elapsed = 00:01:18 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 980 ; free virtual = 23190 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 1dd74cf19 Time (s): cpu = 00:02:11 ; elapsed = 00:01:22 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 977 ; free virtual = 23187 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 18dc2bbc0 Time (s): cpu = 00:02:12 ; elapsed = 00:01:23 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 977 ; free virtual = 23187 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1b334c1f5 Time (s): cpu = 00:02:12 ; elapsed = 00:01:23 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 977 ; free virtual = 23187 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 1b79de7c6 Time (s): cpu = 00:02:32 ; elapsed = 00:01:39 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 965 ; free virtual = 23175 Phase 3 Detail Placement | Checksum: 1b79de7c6 Time (s): cpu = 00:02:32 ; elapsed = 00:01:39 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 970 ; free virtual = 23180 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: f06b9f1c Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.548 | TNS=-738.193 | Phase 1 Physical Synthesis Initialization | Checksum: 108ca20ac Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 974 ; free virtual = 23184 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 108ca20ac Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 974 ; free virtual = 23184 Phase 4.1.1.1 BUFG Insertion | Checksum: f06b9f1c Time (s): cpu = 00:02:42 ; elapsed = 00:01:45 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 974 ; free virtual = 23184 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=-1.912. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: e9dc77d7 Time (s): cpu = 00:05:24 ; elapsed = 00:04:22 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1398 ; free virtual = 23651 Time (s): cpu = 00:05:24 ; elapsed = 00:04:22 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1398 ; free virtual = 23651 Phase 4.1 Post Commit Optimization | Checksum: e9dc77d7 Time (s): cpu = 00:05:25 ; elapsed = 00:04:22 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1396 ; free virtual = 23648 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: e9dc77d7 Time (s): cpu = 00:05:25 ; elapsed = 00:04:23 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1395 ; free virtual = 23648 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: e9dc77d7 Time (s): cpu = 00:05:25 ; elapsed = 00:04:23 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1395 ; free virtual = 23647 Phase 4.3 Placer Reporting | Checksum: e9dc77d7 Time (s): cpu = 00:05:25 ; elapsed = 00:04:23 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1404 ; free virtual = 23657 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1403 ; free virtual = 23656 Time (s): cpu = 00:05:25 ; elapsed = 00:04:23 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1403 ; free virtual = 23656 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 13a34b95a Time (s): cpu = 00:05:25 ; elapsed = 00:04:23 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1398 ; free virtual = 23651 Ending Placer Task | Checksum: f20f1a18 Time (s): cpu = 00:05:25 ; elapsed = 00:04:23 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1394 ; free virtual = 23646 37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:05:28 ; elapsed = 00:04:25 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1392 ; free virtual = 23645 # report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt # report_utilization -file digilent_arty_a7_utilization_place.rpt # report_io -file digilent_arty_a7_io.rpt report_io: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1395 ; free virtual = 23648 # report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1395 ; free virtual = 23648 # report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: 97ba79a2 ConstDB: 0 ShapeSum: 5a54a076 RouteDB: 0 Post Restoration Checksum: NetGraph: 7d127a5a | NumContArr: 8dab823b | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 2900ff1cf Time (s): cpu = 00:01:26 ; elapsed = 00:01:12 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1371 ; free virtual = 23624 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 2900ff1cf Time (s): cpu = 00:01:26 ; elapsed = 00:01:12 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1371 ; free virtual = 23624 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 2900ff1cf Time (s): cpu = 00:01:26 ; elapsed = 00:01:12 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1371 ; free virtual = 23624 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2b85280db Time (s): cpu = 00:01:38 ; elapsed = 00:01:19 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1346 ; free virtual = 23599 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.674 | TNS=-64.868| WHS=-0.771 | THS=-399.349| Router Utilization Summary Global Vertical Routing Utilization = 0.012926 % Global Horizontal Routing Utilization = 0.0130719 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 3957 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 3921 Number of Partially Routed Nets = 36 Number of Node Overlaps = 38 Phase 2 Router Initialization | Checksum: 2da67e448 Time (s): cpu = 00:01:43 ; elapsed = 00:01:21 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1339 ; free virtual = 23592 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 2da67e448 Time (s): cpu = 00:01:43 ; elapsed = 00:01:21 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1339 ; free virtual = 23592 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 19bb9376f Time (s): cpu = 00:01:58 ; elapsed = 00:01:27 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1247 ; free virtual = 23500 Phase 3 Initial Routing | Checksum: 19bb9376f Time (s): cpu = 00:01:58 ; elapsed = 00:01:27 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1247 ; free virtual = 23500 INFO: [Route 35-580] Design has 57 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +====================+===================+==========================================================+ | Launch Setup Clock | Launch Hold Clock | Pin | +====================+===================+==========================================================+ | sys_clk_pin | sys_clk_pin | mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg/DIADI[3] | | sys_clk_pin | sys_clk_pin | mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg/DIADI[5] | | sys_clk_pin | sys_clk_pin | mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg/DIADI[14] | | sys_clk_pin | sys_clk_pin | mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg/DIADI[26] | | sys_clk_pin | sys_clk_pin | mriscvcore_inst/REG_FILE_inst/MEM_FILE/ram_reg/DIADI[21] | +--------------------+-------------------+----------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 688 Number of Nodes with overlaps = 64 Number of Nodes with overlaps = 26 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.787 | TNS=-341.645| WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 307c9cf26 Time (s): cpu = 00:02:32 ; elapsed = 00:01:54 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1234 ; free virtual = 23487 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 145 Number of Nodes with overlaps = 27 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.639 | TNS=-356.223| WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 2ff2ab7e2 Time (s): cpu = 00:03:56 ; elapsed = 00:03:16 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1229 ; free virtual = 23482 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 139 Number of Nodes with overlaps = 46 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 28 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.475 | TNS=-333.902| WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 2a5bed705 Time (s): cpu = 00:04:16 ; elapsed = 00:03:33 . Memory (MB): peak = 2928.621 ; gain = 0.000 ; free physical = 1248 ; free virtual = 23501 Phase 4.4 Global Iteration 3 Number of Nodes with overlaps = 41 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 20 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.456 | TNS=-340.857| WHS=N/A | THS=N/A | Phase 4.4 Global Iteration 3 | Checksum: 1acc952d2 Time (s): cpu = 00:09:07 ; elapsed = 00:08:23 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1237 ; free virtual = 23492 Phase 4 Rip-up And Reroute | Checksum: 1acc952d2 Time (s): cpu = 00:09:07 ; elapsed = 00:08:23 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1237 ; free virtual = 23492 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 289c367c8 Time (s): cpu = 00:09:09 ; elapsed = 00:08:24 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1229 ; free virtual = 23485 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.360 | TNS=-332.495| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 310017113 Time (s): cpu = 00:09:11 ; elapsed = 00:08:25 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1223 ; free virtual = 23478 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 310017113 Time (s): cpu = 00:09:11 ; elapsed = 00:08:25 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1221 ; free virtual = 23476 Phase 5 Delay and Skew Optimization | Checksum: 310017113 Time (s): cpu = 00:09:11 ; elapsed = 00:08:25 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1221 ; free virtual = 23476 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 288a0b19a Time (s): cpu = 00:09:14 ; elapsed = 00:08:27 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1223 ; free virtual = 23479 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.360 | TNS=-308.465| WHS=0.056 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 249162e47 Time (s): cpu = 00:09:14 ; elapsed = 00:08:27 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1223 ; free virtual = 23479 Phase 6 Post Hold Fix | Checksum: 249162e47 Time (s): cpu = 00:09:14 ; elapsed = 00:08:27 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1223 ; free virtual = 23479 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 1.2738 % Global Horizontal Routing Utilization = 1.61921 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report North Dir 1x1 Area, Max Cong = 80.1802%, No Congested Regions. South Dir 1x1 Area, Max Cong = 47.7477%, No Congested Regions. East Dir 1x1 Area, Max Cong = 63.2353%, No Congested Regions. West Dir 1x1 Area, Max Cong = 72.0588%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 7 Route finalize | Checksum: 249162e47 Time (s): cpu = 00:09:15 ; elapsed = 00:08:27 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1218 ; free virtual = 23473 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 249162e47 Time (s): cpu = 00:09:15 ; elapsed = 00:08:27 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1218 ; free virtual = 23473 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 24b2d62e8 Time (s): cpu = 00:09:16 ; elapsed = 00:08:29 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1231 ; free virtual = 23487 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=-2.360 | TNS=-308.465| WHS=0.056 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 10 Post Router Timing | Checksum: 24b2d62e8 Time (s): cpu = 00:09:19 ; elapsed = 00:08:30 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1234 ; free virtual = 23489 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 12bed2734 Time (s): cpu = 00:09:19 ; elapsed = 00:08:30 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1234 ; free virtual = 23489 Ending Routing Task | Checksum: 12bed2734 Time (s): cpu = 00:09:20 ; elapsed = 00:08:31 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1234 ; free virtual = 23489 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 16 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:09:23 ; elapsed = 00:08:33 . Memory (MB): peak = 2940.594 ; gain = 11.973 ; free physical = 1222 ; free virtual = 23477 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (1) 6. checking no_output_delay (1) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (1) ------------------------------ There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (1) ------------------------------- There is 1 port with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -2.338 -307.826 571 14332 0.055 0.000 0 14332 3.750 0.000 0 2615 Timing constraints are not met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sck {0.000 50.000} 100.000 10.000 sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin -2.338 -307.826 571 14332 0.055 0.000 0 14332 3.750 0.000 0 2615 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_arty_a7_route_status.rpt # report_drc -file digilent_arty_a7_drc.rpt Command: report_drc -file digilent_arty_a7_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/mriscv/mriscv/digilent_arty_a7_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_arty_a7_power.rpt Command: report_power -file digilent_arty_a7_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "digilent_arty_a7_100t.bit" Command: write_bitstream -force digilent_arty_a7_100t.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./digilent_arty_a7_100t.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 3175.250 ; gain = 162.613 ; free physical = 1002 ; free virtual = 23261 # exit INFO: [Common 17-206] Exiting Vivado at Fri Apr 4 00:52:07 2025... [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) [Pipeline] dir Running in /var/jenkins_home/workspace/mriscv/mriscv [Pipeline] { [Pipeline] echo Flashing FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mriscv -b digilent_arty_a7_100t -l Final configuration file generated at /var/jenkins_home/workspace/mriscv/mriscv/build_digilent_arty_a7_100t.tcl Makefile executed successfully. Makefile output: Flashing the FPGA... /eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit empty Jtag frequency : requested 10.00MHz -> real 10.00MHz Open file DONE Parse file DONE load program Load SRAM: [================ ] 31.00% Load SRAM: [================================ ] 63.00% Load SRAM: [================================================ ] 95.00% Load SRAM: [===================================================] 100.00% Done Shift IR 35 ir: 1 isc_done 1 isc_ena 0 init 1 done 1 [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) [Pipeline] echo Testing FPGA digilent_arty_a7_100t. [Pipeline] dir Running in /var/jenkins_home/workspace/mriscv/mriscv [Pipeline] { [Pipeline] sh + echo Test for FPGA in /dev/ttyUSB1 Test for FPGA in /dev/ttyUSB1 [Pipeline] sh + python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1 Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'} [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 82513758-a47c-4f5b-ba5a-19189ffab111 hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: No test report files were found. Configuration error? Finished: FAILURE