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| rtl/e203 |
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| vsim |
| .gitignore | May 1, 2025, 3:18:09 AM | 46 B | |
| build_digilent_arty_a7_100t.tcl | May 1, 2025, 3:18:16 AM | 8.26 KiB | |
| clockInfo.txt | May 1, 2025, 3:19:14 AM | 375 B | |
| digilent_arty_a7_100t.bit | May 1, 2025, 3:20:08 AM | 3.65 MiB | |
| digilent_arty_a7_clock_utilization.rpt | May 1, 2025, 3:19:18 AM | 16.56 KiB | |
| digilent_arty_a7_control_sets.rpt | May 1, 2025, 3:19:18 AM | 12.48 KiB | |
| digilent_arty_a7_drc.rpt | May 1, 2025, 3:19:50 AM | 2.36 KiB | |
| digilent_arty_a7_io.rpt | May 1, 2025, 3:19:18 AM | 96.82 KiB | |
| digilent_arty_a7_power.rpt | May 1, 2025, 3:19:50 AM | 8.55 KiB | |
| digilent_arty_a7_route_status.rpt | May 1, 2025, 3:19:49 AM | 651 B | |
| digilent_arty_a7_timing.rpt | May 1, 2025, 3:19:50 AM | 18.47 KiB | |
| digilent_arty_a7_utilization_hierarchical_place.rpt | May 1, 2025, 3:19:18 AM | 3.09 KiB | |
| digilent_arty_a7_utilization_place.rpt | May 1, 2025, 3:19:18 AM | 10.57 KiB | |
| e203_core.core | May 1, 2025, 3:18:09 AM | 2.49 KiB | |
| e203_soc.core | May 1, 2025, 3:18:09 AM | 4.26 KiB | |
| LICENSE | May 1, 2025, 3:18:09 AM | 11.09 KiB | |
| processor_ci_defines.vh | May 1, 2025, 3:18:16 AM | 300 B | |
| README.md | May 1, 2025, 3:18:09 AM | 4.18 KiB | |
| simulation.out | May 1, 2025, 3:18:11 AM | 1.82 MiB | |
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