Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
<span class="pipeline-node-3">Running on Jenkins in /var/lib/jenkins/workspace/e203_hbirdv2
</span>[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
<span class="pipeline-node-7">+ rm -rf e203_hbirdv2
</span>[Pipeline] sh
<span class="pipeline-node-8">+ git clone --recursive <a href='https://github.com/riscv-mcu/e203_hbirdv2'>https://github.com/riscv-mcu/e203_hbirdv2</a> e203_hbirdv2
Cloning into 'e203_hbirdv2'...
</span>[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
<span class="pipeline-node-13">Running in /var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2
</span>[Pipeline] {
[Pipeline] sh
<span class="pipeline-node-15">+ iverilog -o simulation.out -g2009 -DDISABLE_SV_ASSERTION=1 -gsupported-assertions -s e203_cpu_top -I rtl/e203/core/ rtl/e203/core/config.v rtl/e203/core/e203_biu.v rtl/e203/core/e203_clk_ctrl.v rtl/e203/core/e203_clkgate.v rtl/e203/core/e203_core.v rtl/e203/core/e203_cpu.v rtl/e203/core/e203_cpu_top.v rtl/e203/core/e203_defines.v rtl/e203/core/e203_dtcm_ctrl.v rtl/e203/core/e203_dtcm_ram.v rtl/e203/core/e203_extend_csr.v rtl/e203/core/e203_exu.v rtl/e203/core/e203_exu_alu.v rtl/e203/core/e203_exu_alu_bjp.v rtl/e203/core/e203_exu_alu_csrctrl.v rtl/e203/core/e203_exu_alu_dpath.v rtl/e203/core/e203_exu_alu_lsuagu.v rtl/e203/core/e203_exu_alu_muldiv.v rtl/e203/core/e203_exu_alu_rglr.v rtl/e203/core/e203_exu_branchslv.v rtl/e203/core/e203_exu_commit.v rtl/e203/core/e203_exu_csr.v rtl/e203/core/e203_exu_decode.v rtl/e203/core/e203_exu_disp.v rtl/e203/core/e203_exu_excp.v rtl/e203/core/e203_exu_longpwbck.v rtl/e203/core/e203_exu_nice.v rtl/e203/core/e203_exu_oitf.v rtl/e203/core/e203_exu_regfile.v rtl/e203/core/e203_exu_wbck.v rtl/e203/core/e203_ifu.v rtl/e203/core/e203_ifu_ifetch.v rtl/e203/core/e203_ifu_ift2icb.v rtl/e203/core/e203_ifu_litebpu.v rtl/e203/core/e203_ifu_minidec.v rtl/e203/core/e203_irq_sync.v rtl/e203/core/e203_itcm_ctrl.v rtl/e203/core/e203_itcm_ram.v rtl/e203/core/e203_lsu.v rtl/e203/core/e203_lsu_ctrl.v rtl/e203/core/e203_reset_ctrl.v rtl/e203/core/e203_srams.v rtl/e203/general/sirv_1cyc_sram_ctrl.v rtl/e203/general/sirv_gnrl_bufs.v rtl/e203/general/sirv_gnrl_dffs.v rtl/e203/general/sirv_gnrl_icbs.v rtl/e203/general/sirv_gnrl_ram.v rtl/e203/general/sirv_gnrl_xchecker.v rtl/e203/general/sirv_sim_ram.v rtl/e203/general/sirv_sram_icb_ctrl.v rtl/e203/subsys/e203_subsys_clint.v rtl/e203/subsys/e203_subsys_gfcm.v rtl/e203/subsys/e203_subsys_hclkgen.v rtl/e203/subsys/e203_subsys_hclkgen_rstsync.v rtl/e203/subsys/e203_subsys_main.v rtl/e203/subsys/e203_subsys_mems.v rtl/e203/subsys/e203_subsys_nice_core.v rtl/e203/subsys/e203_subsys_perips.v rtl/e203/subsys/e203_subsys_plic.v rtl/e203/subsys/e203_subsys_pll.v rtl/e203/subsys/e203_subsys_pllclkdiv.v rtl/e203/subsys/e203_subsys_top.v
+ vvp simulation.out
</span>[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
[Pipeline] lock
<span class="pipeline-node-30">Trying to acquire lock on [Resource: colorlight_i9]
Resource [colorlight_i9] did not exist. Created.
Lock acquired on [Resource: colorlight_i9]
</span>[Pipeline] {
[Pipeline] lock
<span class="pipeline-node-32">Trying to acquire lock on [Resource: digilent_nexys4_ddr]
Resource [digilent_nexys4_ddr] did not exist. Created.
Lock acquired on [Resource: digilent_nexys4_ddr]
</span>[Pipeline] {
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] dir
<span class="pipeline-node-38">Running in /var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2
</span>[Pipeline] {
[Pipeline] dir
<span class="pipeline-node-40">Running in /var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2
</span>[Pipeline] {
[Pipeline] echo
<span class="pipeline-node-42">Iniciando síntese para FPGA colorlight_i9.
</span>[Pipeline] sh
[Pipeline] echo
<span class="pipeline-node-43">+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p e203_hbirdv2 -b colorlight_i9
Traceback (most recent call last):
  File "/eda/processor-ci/main.py", line 79, in &lt;module&gt;
    main(
  File "/eda/processor-ci/main.py", line 17, in main
    processor_data = get_processor_data(config, processor_name)
  File "/eda/processor-ci/core/config.py", line 35, in get_processor_data
    raise ValueError(
ValueError: Processador 'e203_hbirdv2' n��o encontrado na configura����o.
</span><span class="pipeline-node-44">Iniciando síntese para FPGA digilent_nexys4_ddr.
</span>[Pipeline] sh
<span class="pipeline-node-45">+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p e203_hbirdv2 -b digilent_nexys4_ddr
Traceback (most recent call last):
  File "/eda/processor-ci/main.py", line 79, in &lt;module&gt;
    main(
  File "/eda/processor-ci/main.py", line 17, in main
    processor_data = get_processor_data(config, processor_name)
  File "/eda/processor-ci/core/config.py", line 35, in get_processor_data
    raise ValueError(
ValueError: Processador 'e203_hbirdv2' n��o encontrado na configura����o.
</span>[Pipeline] }
[Pipeline] }
[Pipeline] // dir
[Pipeline] // dir
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "Flash colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "Teste colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "Teste digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
<span class="pipeline-node-74">Lock released on resource [Resource: colorlight_i9]
</span>[Pipeline] }
<span class="pipeline-node-75">Lock released on resource [Resource: digilent_nexys4_ddr]
</span>[Pipeline] // lock
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
<span class="pipeline-node-82">Failed in branch colorlight_i9
</span>[Pipeline] }
<span class="pipeline-node-83">Failed in branch digilent_nexys4_ddr
</span>[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
<span class="pipeline-node-89">Running in /var/lib/jenkins/workspace/e203_hbirdv2/e203_hbirdv2
</span>[Pipeline] {
[Pipeline] sh
<span class="pipeline-node-91">+ rm -rf LICENSE README.md doc e203_core.core e203_soc.core fpga pics riscv-tools rtl simulation.out tb vsim
</span>[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE