| .git |
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| doc |
| fpga |
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| riscv-tools |
| rtl/e203 |
| tb |
| vsim |
| .gitignore | Apr 29, 2025, 3:18:07 AM | 46 B | |
| build_digilent_arty_a7_100t.tcl | Apr 29, 2025, 3:18:15 AM | 8.26 KiB | |
| clockInfo.txt | Apr 29, 2025, 3:19:12 AM | 375 B | |
| digilent_arty_a7_100t.bit | Apr 29, 2025, 3:20:07 AM | 3.65 MiB | |
| digilent_arty_a7_clock_utilization.rpt | Apr 29, 2025, 3:19:17 AM | 16.56 KiB | |
| digilent_arty_a7_control_sets.rpt | Apr 29, 2025, 3:19:16 AM | 12.48 KiB | |
| digilent_arty_a7_drc.rpt | Apr 29, 2025, 3:19:48 AM | 2.36 KiB | |
| digilent_arty_a7_io.rpt | Apr 29, 2025, 3:19:16 AM | 96.82 KiB | |
| digilent_arty_a7_power.rpt | Apr 29, 2025, 3:19:49 AM | 8.55 KiB | |
| digilent_arty_a7_route_status.rpt | Apr 29, 2025, 3:19:47 AM | 651 B | |
| digilent_arty_a7_timing.rpt | Apr 29, 2025, 3:19:48 AM | 18.47 KiB | |
| digilent_arty_a7_utilization_hierarchical_place.rpt | Apr 29, 2025, 3:19:16 AM | 3.09 KiB | |
| digilent_arty_a7_utilization_place.rpt | Apr 29, 2025, 3:19:16 AM | 10.57 KiB | |
| e203_core.core | Apr 29, 2025, 3:18:08 AM | 2.49 KiB | |
| e203_soc.core | Apr 29, 2025, 3:18:08 AM | 4.26 KiB | |
| LICENSE | Apr 29, 2025, 3:18:07 AM | 11.09 KiB | |
| processor_ci_defines.vh | Apr 29, 2025, 3:18:15 AM | 300 B | |
| README.md | Apr 29, 2025, 3:18:07 AM | 4.18 KiB | |
| simulation.out | Apr 29, 2025, 3:18:10 AM | 1.82 MiB | |
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