Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/darkriscv
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf darkriscv
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/darklife/darkriscv darkriscv
Cloning into 'darkriscv'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/darkriscv/darkriscv
[Pipeline] {
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s darkriscv -I rtl rtl/darkriscv.v
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/darkriscv/darkriscv
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/darkriscv/darkriscv -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v
Cache-related signals in hps_io.v
Cache-related signals in scandoubler.v
Cache-related signals in sd_card.sv
Cache-related signals in darkuart.v
Possible cache file: darkcache.v
Cache-related signals in darkcache.v
Cache-related signals in darksocv.v
Cache-related signals in mt48lc16m16a2_ctrl.v
Results saved to /jenkins/processor_ci_utils/labels/darkriscv.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
Resource [colorlight_i9] did not exist. Created.
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
Resource [digilent_arty_a7_100t] did not exist. Created.
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/darkriscv/darkriscv
[Pipeline] {
[Pipeline] dir
Running in /var/jenkins_home/workspace/darkriscv/darkriscv
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA colorlight_i9.
[Pipeline] sh
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p darkriscv -b colorlight_i9
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p darkriscv -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/darkriscv/darkriscv/build_colorlight_i9.tcl
Makefile executed successfully.
Makefile output:
/eda/oss-cad-suite/bin/synlig -c /var/jenkins_home/workspace/darkriscv/darkriscv/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096

-- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' --

1. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v
Parsing Verilog input from `/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v' to AST representation.
Generating RTLIL representation for module `\darkriscv'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /eda/processor_ci/rtl/darkriscv.v
Parsing Verilog input from `/eda/processor_ci/rtl/darkriscv.v' to AST representation.
Generating RTLIL representation for module `\processorci_top'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_rx'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tx'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v
Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v
Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v
Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v
Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v
Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation.
Generating RTLIL representation for module `\Interpreter'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v
Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation.
Generating RTLIL representation for module `\Controller'.
Successfully finished Verilog frontend.

12. Executing SYNTH_ECP5 pass.

12.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_sim.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

12.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_bb.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

12.3. Executing HIERARCHY pass (managing design hierarchy).

12.3.1. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     \ResetBootSystem
Used module:     \darkriscv
Used module:     \Controller
Used module:         \Memory
Used module:         \UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \CYCLES = 20

12.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \CPTR = 0

12.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\darkriscv'.
Parameter \CPTR = 0
Generating RTLIL representation for module `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

12.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

12.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

12.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20

12.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12

12.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12
Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

12.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

12.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

12.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

12.3.12. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\darkriscv\CPTR=s32'00000000000000000000000000000000
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         \Memory
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

12.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20

12.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32

12.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32
Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'.

12.3.16. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\darkriscv\CPTR=s32'00000000000000000000000000000000
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

12.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

12.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

12.3.19. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\darkriscv\CPTR=s32'00000000000000000000000000000000
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider

12.3.20. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\darkriscv\CPTR=s32'00000000000000000000000000000000
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Removing unused module `\Controller'.
Removing unused module `\Interpreter'.
Removing unused module `\Memory'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removing unused module `\FIFO'.
Removing unused module `\uart_tx'.
Removing unused module `\uart_rx'.
Removing unused module `\UART'.
Removing unused module `\darkriscv'.
Removed 15 unused modules.

12.4. Executing PROC pass (convert processes to netlists).

12.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$635'.
Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$1054'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$1054'.
Cleaned up 2 empty switches.

12.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$742 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$694 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$636 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$1234 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$1226 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1427 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1425 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1417 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1414 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1408 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1403 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1398 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1389 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1376 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1374 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1366 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1352 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1346 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1341 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1328 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1319 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1283 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1275 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1275 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1270 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1265 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$1260 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$1043 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$1032 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$745 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Removed a total of 1 dead cases.

12.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 4 redundant assignments.
Promoted 111 assignments to connections.

12.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$743'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1259'.
  Set init value: \read_ptr = 6'000000
  Set init value: \write_ptr = 6'000000
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1429'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1382'.
  Set init value: \i = 0
Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1334'.
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
  Set init value: \pulse_counter = 0
Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1312'.
  Set init value: \state = 8'00000000
  Set init value: \counter = 8'00000000
  Set init value: \read_buffer = 0
  Set init value: \timeout = 0
  Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1282'.
  Set init value: \read_response = 1'0
  Set init value: \write_response = 1'0
  Set init value: \read_data = 0
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
  Set init value: \counter_write = 3'000
  Set init value: \counter_read = 3'000
  Set init value: \state_read = 4'0000
  Set init value: \state_write = 4'0000
Found init rule in `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:168$989'.
  Set init value: \FLUSH = 2'11
Found init rule in `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:107$988'.
  Set init value: \IDATA2 = 0
Found init rule in `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:106$987'.
  Set init value: \HLT2 = 1'0
Found init rule in `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:98$986'.
  Set init value: \XRES = 1'1
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$752'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000

12.4.5. Executing PROC_ARST pass (detect async resets in processes).

12.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~94 debug messages>

12.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$743'.
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$742'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$694'.
     1/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$693_EN[3:0]$700
     2/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$693_DATA[3:0]$699
     3/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$693_ADDR[3:0]$698
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$636'.
     1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$634_EN[3:0]$642
     2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$634_DATA[3:0]$641
     3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$634_ADDR[3:0]$640
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$635'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1259'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1234'.
     1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1246
     2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_DATA[7:0]$1245
     3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_ADDR[5:0]$1244
     4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1240
     5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_DATA[7:0]$1239
     6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_ADDR[5:0]$1238
     7/7: $0\write_ptr[5:0]
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1226'.
     1/2: $0\read_ptr[5:0]
     2/2: $0\read_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1429'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1427'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1425'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1417'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1414'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1408'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1403'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1398'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1389'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1382'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1376'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1374'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1366'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1352'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1346'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1341'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1334'.
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1328'.
     1/1: $0\pulse_counter[31:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1319'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1312'.
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
     1/28: $0\state[7:0]
     2/28: $0\reset_bus[0:0]
     3/28: $0\memory_write[0:0]
     4/28: $0\memory_read[0:0]
     5/28: $0\write_pulse[0:0]
     6/28: $0\core_reset[0:0]
     7/28: $0\communication_write[0:0]
     8/28: $0\communication_read[0:0]
     9/28: $0\temp_buffer[63:0]
    10/28: $0\accumulator[63:0]
    11/28: $0\timeout_counter[31:0]
    12/28: $0\timeout[31:0]
    13/28: $0\read_buffer[31:0]
    14/28: $0\communication_buffer[31:0]
    15/28: $0\num_of_positions[23:0]
    16/28: $0\num_of_pages[23:0]
    17/28: $0\return_state[7:0]
    18/28: $0\memory_page_number[23:0]
    19/28: $0\memory_mux_selector[0:0]
    20/28: $0\end_position[31:0]
    21/28: $0\memory_page_size[23:0]
    22/28: $0\bus_mode[0:0]
    23/28: $0\num_of_cycles_to_pulse[31:0]
    24/28: $0\core_clk_enable[0:0]
    25/28: $0\communication_write_data[31:0]
    26/28: $0\counter[7:0]
    27/28: $0\write_data[31:0]
    28/28: $0\address[31:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1282'.
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1275'.
     1/4: $0\tx_fifo_read[0:0]
     2/4: $0\uart_tx_en[0:0]
     3/4: $0\tx_fifo_read_state[1:0]
     4/4: $0\uart_tx_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1270'.
     1/2: $0\rx_fifo_write[0:0]
     2/2: $0\rx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1265'.
     1/6: $0\tx_fifo_write[0:0]
     2/6: $0\write_response[0:0]
     3/6: $0\state_write[3:0]
     4/6: $0\counter_write[2:0]
     5/6: $0\write_data_buffer[31:0]
     6/6: $0\tx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1260'.
     1/5: $0\read_response[0:0]
     2/5: $0\rx_fifo_read[0:0]
     3/5: $0\state_read[3:0]
     4/5: $0\counter_read[2:0]
     5/5: $0\read_data[31:0]
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1053'.
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1043'.
     1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1052
     2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_DATA[31:0]$1051
     3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_ADDR[31:0]$1050
     4/4: $0\read_sync[31:0]
Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1032'.
     1/1: $0\finish_execution[0:0]
Creating decoders for process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:168$989'.
Creating decoders for process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:107$988'.
Creating decoders for process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:106$987'.
Creating decoders for process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:98$986'.
Creating decoders for process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:430$943'.
Creating decoders for process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
Creating decoders for process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:109$754'.
     1/1: $0\IDATA2[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$752'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$745'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]

12.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1398'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1341'.

12.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$742'.
  created $dff cell `$procdff$2765' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$678_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$679_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$680_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$681_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$682_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$683_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$684_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$685_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$686_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$687_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$688_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$689_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$690_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$691_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$692_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$693_ADDR' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$694'.
  created $dff cell `$procdff$2766' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$693_DATA' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$694'.
  created $dff cell `$procdff$2767' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$693_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$694'.
  created $dff cell `$procdff$2768' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$618_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$619_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$620_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$621_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$622_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$623_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$624_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$625_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$626_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$627_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$628_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$629_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$630_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$631_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$632_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$633_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$634_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$636'.
  created $dff cell `$procdff$2769' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$634_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$636'.
  created $dff cell `$procdff$2770' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$634_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$636'.
  created $dff cell `$procdff$2771' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$635'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1234'.
  created $dff cell `$procdff$2772' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1234'.
  created $dff cell `$procdff$2773' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1234'.
  created $dff cell `$procdff$2774' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1234'.
  created $dff cell `$procdff$2775' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1226'.
  created $dff cell `$procdff$2776' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1226'.
  created $dff cell `$procdff$2777' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1427'.
  created $dff cell `$procdff$2778' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1427'.
  created $dff cell `$procdff$2779' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1425'.
  created $dff cell `$procdff$2780' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1417'.
  created $dff cell `$procdff$2781' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1414'.
  created $dff cell `$procdff$2782' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1408'.
  created $dff cell `$procdff$2783' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1403'.
  created $dff cell `$procdff$2784' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1403'.
  created $dff cell `$procdff$2785' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1389'.
  created $dff cell `$procdff$2786' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1376'.
  created $dff cell `$procdff$2787' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1374'.
  created $dff cell `$procdff$2788' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1366'.
  created $dff cell `$procdff$2789' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1352'.
  created $dff cell `$procdff$2790' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1346'.
  created $dff cell `$procdff$2791' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1346'.
  created $dff cell `$procdff$2792' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1328'.
  created $dff cell `$procdff$2793' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1319'.
  created $dff cell `$procdff$2794' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1319'.
  created $dff cell `$procdff$2795' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2796' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2797' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2798' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2799' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2800' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2801' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2802' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2803' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2804' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2805' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2806' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2807' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2808' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2809' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2810' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2811' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2812' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2813' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2814' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2815' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2816' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2817' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2818' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2819' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2820' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2821' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2822' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
  created $dff cell `$procdff$2823' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1275'.
  created $dff cell `$procdff$2824' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1275'.
  created $dff cell `$procdff$2825' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1275'.
  created $dff cell `$procdff$2826' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1275'.
  created $dff cell `$procdff$2827' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1270'.
  created $dff cell `$procdff$2828' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1270'.
  created $dff cell `$procdff$2829' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1265'.
  created $dff cell `$procdff$2830' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1265'.
  created $dff cell `$procdff$2831' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1265'.
  created $dff cell `$procdff$2832' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1265'.
  created $dff cell `$procdff$2833' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1265'.
  created $dff cell `$procdff$2834' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1265'.
  created $dff cell `$procdff$2835' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1260'.
  created $dff cell `$procdff$2836' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1260'.
  created $dff cell `$procdff$2837' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1260'.
  created $dff cell `$procdff$2838' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1260'.
  created $dff cell `$procdff$2839' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1260'.
  created $dff cell `$procdff$2840' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1053'.
  created $dff cell `$procdff$2841' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1053'.
  created $dff cell `$procdff$2842' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1043'.
  created $dff cell `$procdff$2843' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1043'.
  created $dff cell `$procdff$2844' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1043'.
  created $dff cell `$procdff$2845' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1043'.
  created $dff cell `$procdff$2846' with positive edge clock.
Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1032'.
  created $dff cell `$procdff$2847' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XRES' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:430$943'.
  created $dff cell `$procdff$2848' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\FLUSH' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:430$943'.
  created $dff cell `$procdff$2849' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\NXPC2' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:430$943'.
  created $dff cell `$procdff$2850' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\NXPC' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:430$943'.
  created $dff cell `$procdff$2851' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\PC' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:430$943'.
  created $dff cell `$procdff$2852' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_ADDR' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:430$943'.
  created $dff cell `$procdff$2853' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:430$943'.
  created $dff cell `$procdff$2854' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_EN' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:430$943'.
  created $dff cell `$procdff$2855' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XIDATA' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2856' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XLUI' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2857' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XAUIPC' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2858' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XJAL' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2859' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XJALR' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2860' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XBCC' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2861' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XLCC' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2862' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XSCC' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2863' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XMCC' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2864' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XRCC' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2865' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XCUS' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2866' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XSYS' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2867' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XSIMM' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2868' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\XUIMM' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
  created $dff cell `$procdff$2869' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\HLT2' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:109$754'.
  created $dff cell `$procdff$2870' with positive edge clock.
Creating register for signal `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.\IDATA2' using process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:109$754'.
  created $dff cell `$procdff$2871' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$745'.
  created $dff cell `$procdff$2872' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$745'.
  created $dff cell `$procdff$2873' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$745'.
  created $dff cell `$procdff$2874' with positive edge clock.

12.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

12.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$743'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$742'.
Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$742'.
Removing empty process `DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$717'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$694'.
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$660'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$636'.
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$635'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1259'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1234'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1234'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1226'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1226'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1429'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1427'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1427'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1425'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1425'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1417'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1417'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1414'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1414'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1408'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1408'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1403'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1403'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1398'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1398'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1389'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1389'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1382'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1376'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1376'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1374'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1374'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1366'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1366'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1352'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1352'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1346'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1346'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1341'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1341'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1334'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1328'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1328'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1319'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1319'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1312'.
Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1283'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1282'.
Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1275'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1275'.
Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1270'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1270'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1265'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1265'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1260'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1260'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1053'.
Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1043'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1043'.
Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1032'.
Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1032'.
Removing empty process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:168$989'.
Removing empty process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:107$988'.
Removing empty process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:106$987'.
Removing empty process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:98$986'.
Removing empty process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:430$943'.
Removing empty process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:129$758'.
Found and cleaned up 1 empty switch in `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:109$754'.
Removing empty process `$paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:109$754'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$752'.
Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$745'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$745'.
Cleaned up 94 empty switches.

12.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~5 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
<suppressed ~9 debug messages>
Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
<suppressed ~15 debug messages>
Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
<suppressed ~24 debug messages>
Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
<suppressed ~3 debug messages>
Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
<suppressed ~26 debug messages>
Optimizing module $paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.
<suppressed ~13 debug messages>
Optimizing module processorci_top.
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~8 debug messages>

12.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Deleting now unused module $paramod\darkriscv\CPTR=s32'00000000000000000000000000000000.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~12 debug messages>

12.6. Executing TRIBUF pass.

12.7. Executing DEMINOUT pass (demote inout ports to input or output).

12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~71 debug messages>

12.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 131 unused cells and 727 unused wires.
<suppressed ~186 debug messages>

12.10. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Warning: Wire processorci_top.\miso is used but has no driver.
Warning: Wire processorci_top.\intr is used but has no driver.
Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver.
Found and reported 3 problems.

12.11. Executing OPT pass (performing simple optimizations).

12.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~522 debug messages>
Removed a total of 174 cells.

12.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1457.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1463.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1469.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1457.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1463.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1469.
Removed 6 multiplexer ports.
<suppressed ~129 debug messages>

12.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2040: $auto$opt_reduce.cc:137:opt_pmux$2891
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2065: { $flatten\Controller.\Interpreter.$procmux$1833_CMP $auto$opt_reduce.cc:137:opt_pmux$2893 $flatten\Controller.\Interpreter.$procmux$1823_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2118: { $auto$opt_reduce.cc:137:opt_pmux$2897 $auto$opt_reduce.cc:137:opt_pmux$2895 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2187: $auto$opt_reduce.cc:137:opt_pmux$2899
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2212: { $flatten\Controller.\Interpreter.$procmux$1833_CMP $auto$opt_reduce.cc:137:opt_pmux$2901 $flatten\Controller.\Interpreter.$procmux$1823_CMP }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2703:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0]
      New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2240: { $flatten\Controller.\Interpreter.$procmux$1819_CMP $flatten\Controller.\Interpreter.$procmux$1812_CMP $flatten\Controller.\Interpreter.$procmux$1801_CMP $flatten\Controller.\Interpreter.$procmux$1795_CMP $auto$opt_reduce.cc:137:opt_pmux$2903 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2272: { $auto$opt_reduce.cc:137:opt_pmux$2907 $auto$opt_reduce.cc:137:opt_pmux$2905 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2354: { $flatten\Controller.\Interpreter.$procmux$1813_CMP $auto$opt_reduce.cc:137:opt_pmux$2909 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2365: { $flatten\Controller.\Interpreter.$procmux$1954_CMP $flatten\Controller.\Interpreter.$procmux$1853_CMP $auto$opt_reduce.cc:137:opt_pmux$2911 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2375: { $flatten\Controller.\Interpreter.$procmux$1852_CMP $auto$opt_reduce.cc:137:opt_pmux$2915 $auto$opt_reduce.cc:137:opt_pmux$2913 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2451: { $auto$opt_reduce.cc:137:opt_pmux$2917 $flatten\Controller.\Interpreter.$procmux$1852_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1793: { $flatten\Controller.\Interpreter.$procmux$1887_CMP $flatten\Controller.\Interpreter.$procmux$1883_CMP $flatten\Controller.\Interpreter.$procmux$1879_CMP $flatten\Controller.\Interpreter.$procmux$1853_CMP $flatten\Controller.\Interpreter.$procmux$1852_CMP $flatten\Controller.\Interpreter.$procmux$1848_CMP $flatten\Controller.\Interpreter.$procmux$1847_CMP $flatten\Controller.\Interpreter.$procmux$1843_CMP $flatten\Controller.\Interpreter.$procmux$1833_CMP $flatten\Controller.\Interpreter.$procmux$1829_CMP $auto$opt_reduce.cc:137:opt_pmux$2925 $flatten\Controller.\Interpreter.$procmux$1824_CMP $flatten\Controller.\Interpreter.$procmux$1823_CMP $auto$opt_reduce.cc:137:opt_pmux$2923 $flatten\Controller.\Interpreter.$procmux$1818_CMP $flatten\Controller.\Interpreter.$procmux$1817_CMP $flatten\Controller.\Interpreter.$procmux$1812_CMP $flatten\Controller.\Interpreter.$procmux$1808_CMP $flatten\Controller.\Interpreter.$procmux$1807_CMP $auto$opt_reduce.cc:137:opt_pmux$2921 $flatten\Controller.\Interpreter.$procmux$1801_CMP $flatten\Controller.\Interpreter.$procmux$1800_CMP $flatten\Controller.\Interpreter.$procmux$1799_CMP $auto$opt_reduce.cc:137:opt_pmux$2919 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2475: { $flatten\Controller.\Interpreter.$procmux$1920_CMP $flatten\Controller.\Interpreter.$procmux$1919_CMP $auto$opt_reduce.cc:137:opt_pmux$2927 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2501: { $auto$opt_reduce.cc:137:opt_pmux$2929 $flatten\Controller.\Interpreter.$procmux$1919_CMP $flatten\Controller.\Interpreter.$procmux$1838_CMP $flatten\Controller.\Interpreter.$procmux$1833_CMP $flatten\Controller.\Interpreter.$procmux$1823_CMP }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2703:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0]
      New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_EN[31:0]$1046 [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2571: $auto$opt_reduce.cc:137:opt_pmux$2931
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2635: $auto$opt_reduce.cc:137:opt_pmux$2933
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1454:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1454_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1454_Y [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1454_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1454_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1454_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1454_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1454_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1454_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1454_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1454_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1454:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1454_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1454_Y [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1454_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1454_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1454_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1454_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1454_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1454_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1454_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1454_Y [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1998: $auto$opt_reduce.cc:137:opt_pmux$2935
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1893: $auto$opt_reduce.cc:137:opt_pmux$2937
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1917: $auto$opt_reduce.cc:137:opt_pmux$2939
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1939: $auto$opt_reduce.cc:137:opt_pmux$2941
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1950: $auto$opt_reduce.cc:137:opt_pmux$2943
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1472:
      Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1246, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237
      New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1454_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1472:
      Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1246, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237
      New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1454_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_EN[7:0]$1237 [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 27 changes.

12.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~21 debug messages>
Removed a total of 7 cells.

12.11.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $flatten\Core.$procdff$2870 ($dff) from module processorci_top.

12.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 189 unused wires.
<suppressed ~3 debug messages>

12.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~2 debug messages>

12.11.9. Rerunning OPT passes. (Maybe there is more to do..)

12.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~128 debug messages>

12.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2065: { $auto$opt_reduce.cc:137:opt_pmux$2893 $auto$opt_reduce.cc:137:opt_pmux$2945 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2212: { $auto$opt_reduce.cc:137:opt_pmux$2893 $auto$opt_reduce.cc:137:opt_pmux$2947 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2501: { $auto$opt_reduce.cc:137:opt_pmux$2929 $flatten\Controller.\Interpreter.$procmux$1919_CMP $flatten\Controller.\Interpreter.$procmux$1838_CMP $auto$opt_reduce.cc:137:opt_pmux$2949 }
  Optimizing cells in module \processorci_top.
Performed a total of 3 changes.

12.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

12.11.13. Executing OPT_DFF pass (perform DFF optimizations).

12.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 5 unused wires.
<suppressed ~3 debug messages>

12.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.11.16. Rerunning OPT passes. (Maybe there is more to do..)

12.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~128 debug messages>

12.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

12.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.11.20. Executing OPT_DFF pass (perform DFF optimizations).

12.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

12.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.11.23. Finished OPT passes. (There is nothing left to do.)

12.12. Executing FSM pass (extract and optimize FSM).

12.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking processorci_top.Controller.Interpreter.return_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state.
Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking processorci_top.Controller.Uart.state_read as FSM state register:
    Register has an initialization value.
Not marking processorci_top.Controller.Uart.state_write as FSM state register:
    Register has an initialization value.
Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state.
Not marking processorci_top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.

12.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$2780
  root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1393_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1406_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1419_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1405_Y
  found state code: 3'000
  found ctrl input: \Controller.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \Controller.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1419_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1410_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1406_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1405_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1393_Y
  ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done }
  ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1393_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1405_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1406_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1410_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1419_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'00-- ->      3'001 8'01010001
  transition:      3'000 4'01-- ->      3'000 8'01010000
  transition:      3'000 4'1--- ->      3'000 8'01010000
  transition:      3'010 4'0--0 ->      3'010 8'00100010
  transition:      3'010 4'0--1 ->      3'011 8'00100011
  transition:      3'010 4'1--- ->      3'000 8'00100000
  transition:      3'001 4'0-0- ->      3'001 8'00011001
  transition:      3'001 4'0-1- ->      3'010 8'00011010
  transition:      3'001 4'1--- ->      3'000 8'00011000
  transition:      3'011 4'0-0- ->      3'011 8'10010011
  transition:      3'011 4'0-1- ->      3'000 8'10010000
  transition:      3'011 4'1--- ->      3'000 8'10010000
Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.$procdff$2827
  root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.$procmux$2532_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2527_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2534_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2521_CMP
  found state code: 2'00
  found state code: 2'11
  found state code: 2'10
  found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1279_Y
  found state code: 2'01
  found ctrl output: $flatten\Controller.\Uart.$procmux$2521_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2527_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2532_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2534_CMP
  ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1279_Y }
  ctrl outputs: { $flatten\Controller.\Uart.$procmux$2534_CMP $flatten\Controller.\Uart.$procmux$2532_CMP $flatten\Controller.\Uart.$procmux$2527_CMP $flatten\Controller.\Uart.$procmux$2521_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] }
  transition:       2'00 2'00 ->       2'00 6'000100
  transition:       2'00 2'01 ->       2'01 6'000101
  transition:       2'00 2'1- ->       2'00 6'000100
  transition:       2'10 2'0- ->       2'11 6'001011
  transition:       2'10 2'1- ->       2'00 6'001000
  transition:       2'01 2'0- ->       2'10 6'100010
  transition:       2'01 2'1- ->       2'00 6'100000
  transition:       2'11 2'0- ->       2'00 6'010000
  transition:       2'11 2'1- ->       2'00 6'010000

12.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$2957' from module `\processorci_top'.
  Merging pattern 2'0- and 2'1- from group (3 0 6'010000).
  Merging pattern 2'1- and 2'0- from group (3 0 6'010000).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2950' from module `\processorci_top'.

12.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 15 unused cells and 15 unused wires.
<suppressed ~16 debug messages>

12.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2950' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$2957' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2532_CMP.
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2534_CMP.

12.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2950' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---
Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$2957' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> ---1
  10 -> --1-
  01 -> -1--
  11 -> 1---

12.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2950' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$2950 (\Controller.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \Controller.Uart.i_uart_rx.payload_done
    1: \Controller.Uart.i_uart_rx.next_bit
    2: \Controller.Uart.i_uart_rx.rxd_reg
    3: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1419_Y
    1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1410_Y
    2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1406_Y
    3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1405_Y
    4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1393_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'01--   ->     0 5'01010
      1:     0 4'1---   ->     0 5'01010
      2:     0 4'00--   ->     2 5'01010
      3:     1 4'1---   ->     0 5'00100
      4:     1 4'0--0   ->     1 5'00100
      5:     1 4'0--1   ->     3 5'00100
      6:     2 4'1---   ->     0 5'00011
      7:     2 4'0-1-   ->     1 5'00011
      8:     2 4'0-0-   ->     2 5'00011
      9:     3 4'0-1-   ->     0 5'10010
     10:     3 4'1---   ->     0 5'10010
     11:     3 4'0-0-   ->     3 5'10010

-------------------------------------

FSM `$fsm$\Controller.Uart.tx_fifo_read_state$2957' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$2957 (\Controller.Uart.tx_fifo_read_state):

  Number of input signals:    2
  Number of output signals:   2
  Number of state bits:       4

  Input signals:
    0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1279_Y
    1: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.$procmux$2521_CMP
    1: $flatten\Controller.\Uart.$procmux$2527_CMP

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'00   ->     0 2'01
      1:     0 2'1-   ->     0 2'01
      2:     0 2'01   ->     2 2'01
      3:     1 2'1-   ->     0 2'10
      4:     1 2'0-   ->     3 2'10
      5:     2 2'1-   ->     0 2'00
      6:     2 2'0-   ->     1 2'00
      7:     3 2'--   ->     0 2'00

-------------------------------------

12.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2950' from module `\processorci_top'.
Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$2957' from module `\processorci_top'.

12.13. Executing OPT pass (performing simple optimizations).

12.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~9 debug messages>

12.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

12.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~126 debug messages>

12.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

12.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2874 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2872 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\Core.$procdff$2869 ($dff) from module processorci_top (D = \Core.IDATAX [31:21], Q = \Core.XUIMM [31:21], rval = 11'00000000000).
Adding SRST signal on $flatten\Core.$procdff$2869 ($dff) from module processorci_top (D = $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:161$805_Y [12], Q = \Core.XUIMM [12], rval = 1'0).
Adding SRST signal on $flatten\Core.$procdff$2869 ($dff) from module processorci_top (D = $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:162$804_Y [20:13], Q = \Core.XUIMM [20:13], rval = 8'00000000).
Adding SRST signal on $flatten\Core.$procdff$2850 ($dff) from module processorci_top (D = $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y, Q = \Core.NXPC2, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$2849 ($dff) from module processorci_top (D = $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:440$952_Y [1:0], Q = \Core.FLUSH, rval = 2'10).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2792 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1743_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1737_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1728_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1719_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1710_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1701_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1683_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1692_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3057 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$3057 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1737_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1728_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1719_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1710_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1701_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1683_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1692_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2790 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1659_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3062 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1659_Y, Q = \Controller.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2789 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1648_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3068 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1373_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2788 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2787 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1637_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$3073 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1637_Y, Q = \Controller.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2786 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1626_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3079 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2784 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1603_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1594_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1585_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1576_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1567_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1558_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1540_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1549_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3081 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2783 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1522_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3085 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1413_Y, Q = \Controller.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2782 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1517_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3089 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2781 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1509_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3091 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1424_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2779 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2778 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$2777 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1486_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3097 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1233_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$2776 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1230_DATA, Q = \Controller.Uart.TX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$2772 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1481_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3104 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1249_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$2777 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1486_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3106 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1233_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$2776 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1230_DATA, Q = \Controller.Uart.RX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$2772 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1481_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3113 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1249_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2840 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2657_Y, Q = \Controller.Uart.state_read, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3115 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2657_Y, Q = \Controller.Uart.state_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2839 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2682_Y, Q = \Controller.Uart.counter_read, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$3119 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2682_Y, Q = \Controller.Uart.counter_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2838 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2646_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2837 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2697_Y, Q = \Controller.Uart.read_data, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3136 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2695_Y, Q = \Controller.Uart.read_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2836 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2635_Y, Q = \Controller.Uart.read_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2835 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2579_Y, Q = \Controller.Uart.state_write, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3143 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2579_Y, Q = \Controller.Uart.state_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2834 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2601_Y, Q = \Controller.Uart.counter_write, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$3147 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2601_Y, Q = \Controller.Uart.counter_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2833 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2615_Y, Q = \Controller.Uart.write_data_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3157 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2615_Y, Q = \Controller.Uart.write_data_buffer).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2832 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2629_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3167 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2831 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2561_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2830 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2571_Y, Q = \Controller.Uart.write_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2829 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2552_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3181 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2828 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2547_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2826 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2542_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3184 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2825 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2518_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2824 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2526_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2823 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2065_Y, Q = \Controller.Interpreter.temp_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2822 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2108_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3201 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2108_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]).
Adding EN signal on $auto$ff.cc:266:slice$3201 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2108_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2821 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2118_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3216 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2118_Y, Q = \Controller.Interpreter.timeout_counter).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2820 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2819 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2159_Y, Q = \Controller.Interpreter.read_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2818 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2187_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3232 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2817 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2212_Y, Q = \Controller.Interpreter.num_of_positions).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2816 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2234_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3243 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2815 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2240_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3245 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2240_Y, Q = \Controller.Interpreter.return_state).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2814 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2264_Y, Q = \Controller.Interpreter.memory_page_number).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2813 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2272_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3260 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2272_Y, Q = \Controller.Interpreter.memory_mux_selector).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2812 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2312_Y, Q = \Controller.Interpreter.end_position, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3264 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2312_Y, Q = \Controller.Interpreter.end_position).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2810 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2354_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3268 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2354_Y, Q = \Controller.Interpreter.bus_mode).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2809 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1893_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2808 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2365_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2807 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1998_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2806 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2375_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3281 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2375_Y, Q = \Controller.Interpreter.core_clk_enable).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2805 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2804 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2017_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2803 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2040_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2802 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1950_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2801 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2451_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3297 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2451_Y, Q = \Controller.Interpreter.counter).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2800 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1793_Y, Q = \Controller.Interpreter.state, rval = 8'00000000).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2799 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2475_Y, Q = \Controller.Interpreter.write_data).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2798 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2501_Y, Q = \Controller.Interpreter.address).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2797 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1917_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2796 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1939_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$2793 ($dff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1767_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3320 ($sdff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1767_Y, Q = \Controller.ClkDivider.pulse_counter).
Adding SRST signal on $flatten\Controller.$procdff$2847 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2718_Y, Q = \Controller.finish_execution, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3328 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2718_Y, Q = \Controller.finish_execution).
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$3220 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$3220 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$3220 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$3220 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$3220 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$3220 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$3220 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$3220 ($dffe) from module processorci_top.

12.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 128 unused cells and 134 unused wires.
<suppressed ~129 debug messages>

12.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~28 debug messages>

12.13.9. Rerunning OPT passes. (Maybe there is more to do..)

12.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~102 debug messages>

12.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$3087: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 1 changes.

12.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~60 debug messages>
Removed a total of 20 cells.

12.13.13. Executing OPT_DFF pass (perform DFF optimizations).

12.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 21 unused wires.
<suppressed ~2 debug messages>

12.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.13.16. Rerunning OPT passes. (Maybe there is more to do..)

12.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~102 debug messages>

12.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

12.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.13.20. Executing OPT_DFF pass (perform DFF optimizations).

12.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

12.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.13.23. Finished OPT passes. (There is nothing left to do.)

12.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$2876 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1040 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2876 (Controller.Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1040 (Controller.Memory.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2875 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1230 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2875 (Controller.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1230 (Controller.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$2997 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3022 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3035 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$2972 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1331 ($gt).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1288 ($eq).
Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1292 ($add).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1295 ($add).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1304 ($lt).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1309 ($eq).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1311 ($ge).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1794_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1795_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1797 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1799_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1800_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1801_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1802_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1803_CMP0 ($eq).
Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1805 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1807_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1808_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1810 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1812_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1813_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1817_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1818_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1819_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1821 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1823_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1824_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1825_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1827 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1829_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1831 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1833_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1834_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1835_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1836_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1837_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1838_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1839_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1841 ($mux).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1843_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1845 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1847_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1848_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1850 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1852_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1853_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1856_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1855 ($pmux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1857_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1858_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1859_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1860_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1861_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1862_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1863_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1864_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1865_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1866_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1867_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1868_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1869_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1870_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1871_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1872_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1873_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1874_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1875_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1876_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1877_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1878_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1879_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1881 ($mux).
Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1883_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1885 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1919_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1920_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1921_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1954_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2109_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2110_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2111_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2154_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2280_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2313_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2314_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3333 ($ne).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2387_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2388_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3323 ($ne).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$1262 ($lt).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1267 ($lt).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2566_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2572_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2573_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2585_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2587 ($mux).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2636_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2637_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2651_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2659_CMP0 ($eq).
Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2667 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1478 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1466 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1250 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1250 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1249 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1248 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1247 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1233 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1232 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1231 ($eq).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1478 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1466 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1250 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1250 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1249 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1248 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1247 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1233 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1232 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1231 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$2983 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1402 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1401 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1400 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1399 ($mux).
Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1394 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1392 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1368 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1360 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1358 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1355 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1354 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1350 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1345 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1344 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1343 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1342 ($mux).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1338 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1336 ($eq).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2709 ($mux).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2709 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$1017 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1001 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1000 ($mux).
Removed top 1 bits (of 32) from FF cell processorci_top.$flatten\Core.$procdff$2856 ($dff).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:613$968 ($add).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:441$950 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:451$948 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Core.$sub$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:441$947 ($sub).
Removed top 30 bits (of 32) from port Y of cell processorci_top.$flatten\Core.$sub$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:441$947 ($sub).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:390$902 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:388$895 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:387$893 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$850 ($eq).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:265$837 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:263$834 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:262$831 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:261$828 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:260$825 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:258$822 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:257$819 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:256$816 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:255$813 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:160$806 ($mux).
Removed top 19 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:161$805 ($mux).
Removed top 11 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:162$804 ($mux).
Removed top 11 bits (of 32) from mux cell processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:163$803 ($mux).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:143$776 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:141$774 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:140$772 ($eq).
Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:139$770 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:134$762 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:133$760 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2737_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$750 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$749 ($add).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$749 ($add).
Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$748 ($lt).
Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1000_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_ADDR[31:0]$1044.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1797_Y.
Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1805_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1810_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1821_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1827_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1831_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1841_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1845_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1850_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1855_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1881_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1885_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1038_ADDR[31:0]$1044.
Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2587_Y.
Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2667_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_ADDR[5:0]$1235.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_ADDR[5:0]$1244.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1232_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1248_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1249_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_ADDR[5:0]$1235.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1225_ADDR[5:0]$1244.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1232_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1248_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1233_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1249_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1399_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1400_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1401_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1402_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1342_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1343_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1344_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1345_Y.
Removed top 20 bits (of 32) from wire processorci_top.$flatten\Core.$0\XUIMM[31:0].
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:387$894_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:388$896_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Core.$sub$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:441$947_Y.
Removed top 1 bits (of 20) from wire processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:151$783_Y.
Removed top 4 bits (of 19) from wire processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:152$785_Y.
Removed top 4 bits (of 11) from wire processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:153$787_Y.
Removed top 19 bits (of 32) from wire processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:161$805_Y.
Removed top 11 bits (of 32) from wire processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:162$804_Y.
Removed top 11 bits (of 32) from wire processorci_top.$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:163$803_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$749_Y.

12.15. Executing PEEPOPT pass (run peephole optimizers).

12.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 56 unused wires.
<suppressed ~1 debug messages>

12.17. Executing SHARE pass (SAT-based resource sharing).
Found 6 cells in module processorci_top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\Core.$sshr$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:396$906 ($sshr):
    Found 1 activation_patterns using ctrl signal { \Core.XIDATA [30] \Core.LUI \Core.AUIPC $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:384$887_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:385$889_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:386$891_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:387$893_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:388$895_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:389$897_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:390$902_Y $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:427$939_Y $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$955_Y $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:568$958_Y \Controller.core_read_memory_data }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Core.$shr$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:392$905 ($shr):
    Found 1 activation_patterns using ctrl signal { \Core.XIDATA [30] \Core.LUI \Core.AUIPC $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:384$887_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:385$889_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:386$891_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:387$893_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:388$895_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:389$897_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:390$902_Y $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:427$939_Y $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$955_Y $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:568$958_Y \Controller.core_read_memory_data }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Core.$shl$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:390$903 ($shl):
    Found 1 activation_patterns using ctrl signal { \Core.LUI \Core.AUIPC $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:384$887_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:385$889_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:386$891_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:387$893_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:388$895_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:389$897_Y $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:390$902_Y $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:427$939_Y $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$955_Y $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:568$958_Y \Controller.core_read_memory_data }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Core.$memrd$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:576$959 ($memrd):
    Found 1 activation_patterns using ctrl signal { \Core.LUI \Core.AUIPC $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:427$939_Y $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$955_Y $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:568$958_Y \Controller.core_read_memory_data }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1040 ($memrd):
    Found 2 activation_patterns using ctrl signal { \Core.XRES \Controller.Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1837_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1040 ($memrd):
    Found 2 activation_patterns using ctrl signal { $flatten\Core.$logic_or$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$955_Y \Controller.core_read_memory_data \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1837_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.

12.18. Executing TECHMAP pass (map to technology primitives).

12.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/cmp2lut.v
Parsing Verilog input from `/usr/local/share/synlig/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

12.18.2. Continuing TECHMAP pass.
Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt.
No more expansions possible.
<suppressed ~249 debug messages>

12.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 6 unused wires.
<suppressed ~1 debug messages>

12.21. Executing TECHMAP pass (map to technology primitives).

12.21.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/mul2dsp.v
Parsing Verilog input from `/usr/local/share/synlig/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

12.21.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/dsp_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

12.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

12.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module processorci_top:
  creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1332 ($sub).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1287 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1291 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1292 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1295 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1302 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1306 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1294 ($sub).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1269 ($add).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1264 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1232 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1248 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1250 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1232 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1248 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1250 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1413 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1424 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1362 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1373 ($add).
  creating $macc model for $flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:389$900 ($add).
  creating $macc model for $flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:426$938 ($add).
  creating $macc model for $flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:613$968 ($add).
  creating $macc model for $flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:637$973 ($add).
  creating $macc model for $flatten\Core.$sub$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:389$899 ($sub).
  creating $macc model for $flatten\Core.$sub$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:441$947 ($sub).
  creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$749 ($add).
  creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$749.
  creating $alu model for $macc $flatten\Core.$sub$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:441$947.
  creating $alu model for $macc $flatten\Core.$sub$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:389$899.
  creating $alu model for $macc $flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:637$973.
  creating $alu model for $macc $flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:613$968.
  creating $alu model for $macc $flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:426$938.
  creating $alu model for $macc $flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:389$900.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1373.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1362.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1424.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1413.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1250.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1248.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1232.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1250.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1248.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1232.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1264.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1269.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1294.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1306.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1302.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1295.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1292.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1291.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1287.
  creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1332.
  creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1331 ($gt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1311 ($ge): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1304 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1311.
  creating $alu model for $flatten\Core.$ge$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:419$916 ($ge): new $alu
  creating $alu model for $flatten\Core.$ge$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:421$923 ($ge): new $alu
  creating $alu model for $flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:387$894 ($lt): new $alu
  creating $alu model for $flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:388$896 ($lt): new $alu
  creating $alu model for $flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:420$919 ($lt): merged with $flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:387$894.
  creating $alu model for $flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:422$927 ($lt): merged with $flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:388$896.
  creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$748 ($lt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1309 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1311.
  creating $alu model for $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:424$935 ($eq): merged with $flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:387$894.
  creating $alu model for $flatten\Core.$ne$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:423$931 ($ne): merged with $flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:387$894.
  creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$750 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$748.
  creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$748, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$750: $auto$alumacc.cc:485:replace_alu$3395
  creating $alu cell for $flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:387$894, $flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:420$919, $flatten\Core.$eq$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:424$935, $flatten\Core.$ne$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:423$931: $auto$alumacc.cc:485:replace_alu$3406
  creating $alu cell for $flatten\Core.$ge$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:421$923: $auto$alumacc.cc:485:replace_alu$3419
  creating $alu cell for $flatten\Core.$ge$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:419$916: $auto$alumacc.cc:485:replace_alu$3430
  creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1311, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1304, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1309: $auto$alumacc.cc:485:replace_alu$3439
  creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1331: $auto$alumacc.cc:485:replace_alu$3452
  creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1332: $auto$alumacc.cc:485:replace_alu$3457
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1287: $auto$alumacc.cc:485:replace_alu$3460
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1291: $auto$alumacc.cc:485:replace_alu$3463
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1292: $auto$alumacc.cc:485:replace_alu$3466
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1295: $auto$alumacc.cc:485:replace_alu$3469
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1302: $auto$alumacc.cc:485:replace_alu$3472
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1306: $auto$alumacc.cc:485:replace_alu$3475
  creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1294: $auto$alumacc.cc:485:replace_alu$3478
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1269: $auto$alumacc.cc:485:replace_alu$3481
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1264: $auto$alumacc.cc:485:replace_alu$3484
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1232: $auto$alumacc.cc:485:replace_alu$3487
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1248: $auto$alumacc.cc:485:replace_alu$3490
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1250: $auto$alumacc.cc:485:replace_alu$3493
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1232: $auto$alumacc.cc:485:replace_alu$3496
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1248: $auto$alumacc.cc:485:replace_alu$3499
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1250: $auto$alumacc.cc:485:replace_alu$3502
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1413: $auto$alumacc.cc:485:replace_alu$3505
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1424: $auto$alumacc.cc:485:replace_alu$3508
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1362: $auto$alumacc.cc:485:replace_alu$3511
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1373: $auto$alumacc.cc:485:replace_alu$3514
  creating $alu cell for $flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:388$896, $flatten\Core.$lt$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:422$927: $auto$alumacc.cc:485:replace_alu$3517
  creating $alu cell for $flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:389$900: $auto$alumacc.cc:485:replace_alu$3530
  creating $alu cell for $flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:426$938: $auto$alumacc.cc:485:replace_alu$3533
  creating $alu cell for $flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:613$968: $auto$alumacc.cc:485:replace_alu$3536
  creating $alu cell for $flatten\Core.$add$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:637$973: $auto$alumacc.cc:485:replace_alu$3539
  creating $alu cell for $flatten\Core.$sub$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:389$899: $auto$alumacc.cc:485:replace_alu$3542
  creating $alu cell for $flatten\Core.$sub$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:441$947: $auto$alumacc.cc:485:replace_alu$3545
  creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$749: $auto$alumacc.cc:485:replace_alu$3548
  created 34 $alu and 0 $macc cells.

12.23. Executing OPT pass (performing simple optimizations).

12.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~3 debug messages>

12.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~102 debug messages>

12.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

12.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

12.23.6. Executing OPT_DFF pass (perform DFF optimizations).

12.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 16 unused wires.
<suppressed ~1 debug messages>

12.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.23.9. Rerunning OPT passes. (Maybe there is more to do..)

12.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~102 debug messages>

12.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

12.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.23.13. Executing OPT_DFF pass (perform DFF optimizations).

12.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

12.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.23.16. Finished OPT passes. (There is nothing left to do.)

12.24. Executing MEMORY pass.

12.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

12.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

12.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing processorci_top.Controller.Data_Memory.memory write port 0.
  Analyzing processorci_top.Controller.Memory.memory write port 0.
  Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0.
  Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0.
  Analyzing processorci_top.Core.REGS write port 0.
Populating enable bits on write ports of memory processorci_top.Core.REGS with async read feedback:
    Port 0 bit 31: added enable logic for 1 different cases.
    Port 0 bit 30: added enable logic for 1 different cases.
    Port 0 bit 29: added enable logic for 1 different cases.
    Port 0 bit 28: added enable logic for 1 different cases.
    Port 0 bit 27: added enable logic for 1 different cases.
    Port 0 bit 26: added enable logic for 1 different cases.
    Port 0 bit 25: added enable logic for 1 different cases.
    Port 0 bit 24: added enable logic for 1 different cases.
    Port 0 bit 23: added enable logic for 1 different cases.
    Port 0 bit 22: added enable logic for 1 different cases.
    Port 0 bit 21: added enable logic for 1 different cases.
    Port 0 bit 20: added enable logic for 1 different cases.
    Port 0 bit 19: added enable logic for 1 different cases.
    Port 0 bit 18: added enable logic for 1 different cases.
    Port 0 bit 17: added enable logic for 1 different cases.
    Port 0 bit 16: added enable logic for 1 different cases.
    Port 0 bit 15: added enable logic for 1 different cases.
    Port 0 bit 14: added enable logic for 1 different cases.
    Port 0 bit 13: added enable logic for 1 different cases.
    Port 0 bit 12: added enable logic for 1 different cases.
    Port 0 bit 11: added enable logic for 1 different cases.
    Port 0 bit 10: added enable logic for 1 different cases.
    Port 0 bit 9: added enable logic for 1 different cases.
    Port 0 bit 8: added enable logic for 1 different cases.
    Port 0 bit 7: added enable logic for 1 different cases.
    Port 0 bit 6: added enable logic for 1 different cases.
    Port 0 bit 5: added enable logic for 1 different cases.
    Port 0 bit 4: added enable logic for 1 different cases.
    Port 0 bit 3: added enable logic for 1 different cases.
    Port 0 bit 2: added enable logic for 1 different cases.
    Port 0 bit 1: added enable logic for 1 different cases.
    Port 0 bit 0: added enable logic for 1 different cases.

12.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

12.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Core.REGS'[0] in module `\processorci_top': no output FF found.
Checking read port `\Core.REGS'[1] in module `\processorci_top': no output FF found.
Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Core.REGS'[0] in module `\processorci_top': merged address FF to cell.
Checking read port address `\Core.REGS'[1] in module `\processorci_top': merged address FF to cell.

12.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 2 unused cells and 19 unused wires.
<suppressed ~3 debug messages>

12.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory processorci_top.Core.REGS by address:

12.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

12.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

12.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

12.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

12.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Core.REGS via $__TRELLIS_DPR16X4_
Extracted addr FF from read port 0 of processorci_top.Core.REGS: $\Core.REGS$rdreg[0]
Extracted addr FF from read port 1 of processorci_top.Core.REGS: $\Core.REGS$rdreg[1]
<suppressed ~2482 debug messages>

12.27. Executing TECHMAP pass (map to technology primitives).

12.27.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/lutrams_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

12.27.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/brams_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

12.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1062 debug messages>

12.28. Executing OPT pass (performing simple optimizations).

12.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~104 debug messages>

12.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2873 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding SRST signal on $auto$ff.cc:266:slice$3253 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1306_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3192 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2065_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]).
Adding EN signal on $auto$ff.cc:266:slice$3055 ($sdff) from module processorci_top (D = $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y [1:0], Q = \Core.NXPC2 [1:0]).
Adding SRST signal on $auto$ff.cc:266:slice$3029 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2734_Y, Q = \ResetBootSystem.counter, rval = 6'000000).

12.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 2 unused cells and 7383 unused wires.
<suppressed ~3 debug messages>

12.28.5. Rerunning OPT passes. (Removed registers in this run.)

12.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

12.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$5949 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$3383 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

12.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 4 unused wires.
<suppressed ~2 debug messages>

12.28.10. Rerunning OPT passes. (Removed registers in this run.)

12.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.28.13. Executing OPT_DFF pass (perform DFF optimizations).

12.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

12.28.15. Finished fast OPT passes.

12.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

12.30. Executing OPT pass (performing simple optimizations).

12.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~72 debug messages>

12.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$5943: { $auto$opt_dff.cc:194:make_patterns_logic$5940 $auto$opt_dff.cc:194:make_patterns_logic$3193 $auto$opt_dff.cc:194:make_patterns_logic$3195 $auto$fsm_map.cc:74:implement_pattern_cache$3017 }
    Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1000:
      Old ports: A=\Core.NXPC2 [11:0], B={ \Controller.Interpreter.memory_page_number [5:0] \Core.NXPC2 [5:0] }, Y=$auto$wreduce.cc:461:run$3337 [11:0]
      New ports: A=\Core.NXPC2 [11:6], B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$3337 [11:6]
      New connections: $auto$wreduce.cc:461:run$3337 [5:0] = \Core.NXPC2 [5:0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1805:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$3340 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3340 [2] $auto$wreduce.cc:461:run$3340 [0] }
      New connections: $auto$wreduce.cc:461:run$3340 [1] = $auto$wreduce.cc:461:run$3340 [0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1810:
      Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$3341 [6:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$3341 [1:0]
      New connections: $auto$wreduce.cc:461:run$3341 [6:2] = { $auto$wreduce.cc:461:run$3341 [1] 3'010 $auto$wreduce.cc:461:run$3341 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1821:
      Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$3342 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3342 [2]
      New connections: { $auto$wreduce.cc:461:run$3342 [3] $auto$wreduce.cc:461:run$3342 [1:0] } = { $auto$wreduce.cc:461:run$3342 [2] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1831:
      Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$3344 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3344 [0]
      New connections: $auto$wreduce.cc:461:run$3344 [3:1] = { $auto$wreduce.cc:461:run$3344 [0] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1845:
      Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$3346 [6:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3346 [0]
      New connections: $auto$wreduce.cc:461:run$3346 [6:1] = { $auto$wreduce.cc:461:run$3346 [0] 1'0 $auto$wreduce.cc:461:run$3346 [0] 3'011 }
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2240:
      Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$2240_Y
      New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$2240_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2240_Y [7:5] = 3'000
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2365:
      Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2365_Y
      New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2365_Y [23:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2365_Y [31:24] = 8'00000000
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2375: $auto$opt_reduce.cc:137:opt_pmux$2915
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2579:
      Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$3352 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2579_Y
      New ports: A=3'000, B={ $auto$wreduce.cc:461:run$3352 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2579_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2579_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2587:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$3352 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3352 [2]
      New connections: $auto$wreduce.cc:461:run$3352 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2663:
      Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2663_Y
      New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2663_Y [2:1]
      New connections: { $flatten\Controller.\Uart.$procmux$2663_Y [3] $flatten\Controller.\Uart.$procmux$2663_Y [0] } = 2'00
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1621:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$3365 [0] 1'0 $auto$wreduce.cc:461:run$3366 [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$3368 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$3365 [0] $auto$wreduce.cc:461:run$3366 [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$3368 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1402:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3368 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3368 [0]
      New connections: $auto$wreduce.cc:461:run$3368 [1] = $auto$wreduce.cc:461:run$3368 [0]
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1758:
      Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$3370 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$3372 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$3370 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$3372 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1345:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3372 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3372 [0]
      New connections: $auto$wreduce.cc:461:run$3372 [1] = $auto$wreduce.cc:461:run$3372 [0]
    Consolidated identical input bits for $mux cell $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:151$783:
      Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$auto$wreduce.cc:461:run$3377
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3377 [0]
      New connections: $auto$wreduce.cc:461:run$3377 [19:1] = { $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] $auto$wreduce.cc:461:run$3377 [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:152$785:
      Old ports: A=19'0000000000000000000, B=19'1111111111111111111, Y=$auto$wreduce.cc:461:run$3378
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3378 [0]
      New connections: $auto$wreduce.cc:461:run$3378 [18:1] = { $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] $auto$wreduce.cc:461:run$3378 [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:153$787:
      Old ports: A=11'00000000000, B=11'11111111111, Y=$auto$wreduce.cc:461:run$3379
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3379 [0]
      New connections: $auto$wreduce.cc:461:run$3379 [10:1] = { $auto$wreduce.cc:461:run$3379 [0] $auto$wreduce.cc:461:run$3379 [0] $auto$wreduce.cc:461:run$3379 [0] $auto$wreduce.cc:461:run$3379 [0] $auto$wreduce.cc:461:run$3379 [0] $auto$wreduce.cc:461:run$3379 [0] $auto$wreduce.cc:461:run$3379 [0] $auto$wreduce.cc:461:run$3379 [0] $auto$wreduce.cc:461:run$3379 [0] $auto$wreduce.cc:461:run$3379 [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849:
      Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0]
      New connections: $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [23:1] = { $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853:
      Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0]
      New connections: $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [15:1] = { $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$854:
      Old ports: A=\Core.DATAI, B={ $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y \Core.DATAI [15:0] }, Y=$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$854_Y
      New ports: A=\Core.DATAI [31:16], B=$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$853_Y, Y=$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$854_Y [31:16]
      New connections: $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$854_Y [15:0] = \Core.DATAI [15:0]
    Consolidated identical input bits for $mux cell $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:451$948:
      Old ports: A=2'00, B=2'10, Y=$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:451$948_Y [1:0]
      New ports: A=1'0, B=1'1, Y=$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:451$948_Y [1]
      New connections: $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:451$948_Y [0] = 1'0
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2745: { $flatten\ResetBootSystem.$procmux$2738_CMP $flatten\ResetBootSystem.$procmux$2737_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2748:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2748_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2748_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2748_Y [0] = 1'0
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2657:
      Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2663_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2657_Y
      New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2663_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2657_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2657_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$855:
      Old ports: A=$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$854_Y, B={ $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y \Core.DATAI [7:0] }, Y=\Core.LDATA
      New ports: A={ $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:303$854_Y [31:16] \Core.DATAI [15:8] }, B={ $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] $flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:302$849_Y [0] }, Y=\Core.LDATA [31:8]
      New connections: \Core.LDATA [7:0] = \Core.DATAI [7:0]
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2754:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2748_Y, Y=$flatten\ResetBootSystem.$procmux$2754_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2748_Y [1], Y=$flatten\ResetBootSystem.$procmux$2754_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2754_Y [0] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 29 changes.

12.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

12.30.6. Executing OPT_DFF pass (perform DFF optimizations).

12.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 3 unused wires.
<suppressed ~1 debug messages>

12.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

12.30.9. Rerunning OPT passes. (Maybe there is more to do..)

12.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~72 debug messages>

12.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

12.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$3056 ($sdff) from module processorci_top (D = $auto$wreduce.cc:461:run$3376 [0], Q = \Core.FLUSH [0], rval = 1'0).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3072 ($sdff) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3116 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3144 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3246 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3246 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3246 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$3273 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$3273 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$3273 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$3273 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$3273 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$3273 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$3273 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$3273 ($dffe) from module processorci_top.

12.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

12.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

12.30.16. Rerunning OPT passes. (Maybe there is more to do..)

12.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~72 debug messages>

12.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1815:
      Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1815_Y
      New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1815_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1815_Y [7:5] = 3'000
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1793:
      Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$3350 [0] 6'000000 $auto$wreduce.cc:461:run$3343 [1:0] 1'0 $auto$wreduce.cc:461:run$3348 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$3347 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$3346 [6] 1'0 $auto$wreduce.cc:461:run$3346 [6] 3'011 $auto$wreduce.cc:461:run$3346 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$3342 [3] 2'00 $auto$wreduce.cc:461:run$3342 [3] 6'000010 $auto$wreduce.cc:461:run$3343 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$3342 [3] $auto$wreduce.cc:461:run$3342 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1815_Y 1'0 $auto$wreduce.cc:461:run$3341 [6] 3'010 $auto$wreduce.cc:461:run$3341 [2] $auto$wreduce.cc:461:run$3341 [6] $auto$wreduce.cc:461:run$3341 [2] 13'0001001100010 $auto$wreduce.cc:461:run$3340 [2:1] $auto$wreduce.cc:461:run$3340 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$3339 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1793_Y
      New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$3350 [0] 5'00000 $auto$wreduce.cc:461:run$3343 [1:0] $auto$wreduce.cc:461:run$3348 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$3347 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$3346 [6] 1'0 $auto$wreduce.cc:461:run$3346 [6] 3'011 $auto$wreduce.cc:461:run$3346 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$3342 [3] 2'00 $auto$wreduce.cc:461:run$3342 [3] 5'00010 $auto$wreduce.cc:461:run$3343 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$3342 [3] $auto$wreduce.cc:461:run$3342 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1815_Y [4:0] $auto$wreduce.cc:461:run$3341 [6] 3'010 $auto$wreduce.cc:461:run$3341 [2] $auto$wreduce.cc:461:run$3341 [6] $auto$wreduce.cc:461:run$3341 [2] 11'00100110010 $auto$wreduce.cc:461:run$3340 [2:1] $auto$wreduce.cc:461:run$3340 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$3339 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1793_Y [6:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1793_Y [7] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 2 changes.

12.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.30.20. Executing OPT_DFF pass (perform DFF optimizations).

12.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

12.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.30.23. Rerunning OPT passes. (Maybe there is more to do..)

12.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~72 debug messages>

12.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

12.30.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.30.27. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3301 ($sdff) from module processorci_top.

12.30.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

12.30.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

12.30.30. Rerunning OPT passes. (Maybe there is more to do..)

12.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~72 debug messages>

12.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

12.30.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.30.34. Executing OPT_DFF pass (perform DFF optimizations).

12.30.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

12.30.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.30.37. Finished OPT passes. (There is nothing left to do.)

12.31. Executing TECHMAP pass (map to technology primitives).

12.31.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v
Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

12.31.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/arith_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

12.31.3. Continuing TECHMAP pass.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $bmux.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $lut.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu.
Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu.
Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux.
Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux.
Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux.
Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux.
Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux.
Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_80_ecp5_alu for cells of type $alu.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ecp5_alu for cells of type $alu.
Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$e765c459d3029c22a22a27989e94858fd9ebfa9c\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$ba698a254f9a5947e85cbe7beae6b161eefc5386\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $pos.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~5383 debug messages>

12.32. Executing OPT pass (performing simple optimizations).

12.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~10221 debug messages>

12.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~4275 debug messages>
Removed a total of 1425 cells.

12.32.3. Executing OPT_DFF pass (perform DFF optimizations).

12.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1664 unused cells and 4525 unused wires.
<suppressed ~1670 debug messages>

12.32.5. Finished fast OPT passes.

12.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

12.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

12.35. Executing TECHMAP pass (map to technology primitives).

12.35.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

12.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFF_P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
No more expansions possible.
<suppressed ~970 debug messages>

12.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~116 debug messages>

12.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

12.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in processorci_top.

12.39. Executing ATTRMVCP pass (move or copy attributes).

12.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 4499 unused wires.
<suppressed ~1 debug messages>

12.41. Executing TECHMAP pass (map to technology primitives).

12.41.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/latches_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

12.41.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

12.42. Executing ABC9 pass.

12.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

12.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

12.42.3. Executing PROC pass (convert processes to netlists).

12.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$33391'.
Cleaned up 1 empty switch.

12.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$33392 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

12.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

12.42.3.4. Executing PROC_INIT pass (extract init attributes).

12.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

12.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

12.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$33392'.
     1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$33390_EN[3:0]$33396
     2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$33390_DATA[3:0]$33397
     3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$33390_ADDR[3:0]$33398
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$33391'.

12.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

12.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33388_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33387_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33382_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33381_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33376_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33386_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33375_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33385_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33384_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33380_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33379_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33378_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33374_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33389_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33383_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$33377_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$33390_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$33392'.
  created $dff cell `$procdff$33442' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$33390_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$33392'.
  created $dff cell `$procdff$33443' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$33390_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$33392'.
  created $dff cell `$procdff$33444' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$33391'.
  created direct connection (no actual register cell created).

12.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

12.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$33416'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$33392'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$33391'.
Cleaned up 1 empty switch.

12.42.3.12. Executing OPT_EXPR pass (perform const folding).

12.42.4. Executing SCC pass (detecting logic loops).
Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$31527 $auto$simplemap.cc:267:simplemap_mux$27392 $auto$simplemap.cc:126:simplemap_reduce$27377 $auto$simplemap.cc:126:simplemap_reduce$27374 $auto$opt_expr.cc:617:replace_const_cells$31511 $auto$ff.cc:266:slice$14818 $auto$simplemap.cc:126:simplemap_reduce$15105 $auto$simplemap.cc:126:simplemap_reduce$15120 $auto$ff.cc:266:slice$14817 $auto$ff.cc:266:slice$14816 $auto$simplemap.cc:267:simplemap_mux$15089 $auto$simplemap.cc:225:simplemap_logbin$15092 $auto$simplemap.cc:196:simplemap_lognot$15109 $auto$simplemap.cc:126:simplemap_reduce$15107 $auto$simplemap.cc:126:simplemap_reduce$15104 $auto$opt_expr.cc:617:replace_const_cells$31513 $auto$simplemap.cc:75:simplemap_bitop$27387 $auto$simplemap.cc:196:simplemap_lognot$15124 $auto$simplemap.cc:126:simplemap_reduce$15122 $auto$simplemap.cc:126:simplemap_reduce$15119 $auto$ff.cc:266:slice$14815 $auto$simplemap.cc:126:simplemap_reduce$8460 $auto$simplemap.cc:126:simplemap_reduce$8458 $auto$simplemap.cc:225:simplemap_logbin$15044 $auto$simplemap.cc:196:simplemap_lognot$15054 $auto$simplemap.cc:126:simplemap_reduce$15052 $auto$opt_expr.cc:617:replace_const_cells$31525 $auto$simplemap.cc:267:simplemap_mux$27391 $auto$simplemap.cc:126:simplemap_reduce$27382 $auto$simplemap.cc:126:simplemap_reduce$27379 $auto$simplemap.cc:75:simplemap_bitop$27390
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$8374 $auto$simplemap.cc:38:simplemap_not$8297 $auto$simplemap.cc:38:simplemap_not$19038 $auto$ff.cc:266:slice$18943 $auto$ff.cc:479:convert_ce_over_srst$32421 $auto$alumacc.cc:485:replace_alu$3395.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$8579 $auto$simplemap.cc:38:simplemap_not$19039 $auto$ff.cc:266:slice$18944 $auto$ff.cc:479:convert_ce_over_srst$32423 $auto$ff.cc:266:slice$18945 $auto$ff.cc:479:convert_ce_over_srst$32425 $auto$alumacc.cc:485:replace_alu$3395.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$8583 $auto$simplemap.cc:126:simplemap_reduce$8580 $auto$simplemap.cc:38:simplemap_not$19041 $auto$ff.cc:266:slice$18946 $auto$ff.cc:479:convert_ce_over_srst$32427 $auto$alumacc.cc:485:replace_alu$3395.slice[4].ccu2c_i $auto$ff.cc:266:slice$18947 $auto$ff.cc:479:convert_ce_over_srst$32429 $auto$simplemap.cc:126:simplemap_reduce$8407 $auto$simplemap.cc:126:simplemap_reduce$8376 $auto$simplemap.cc:126:simplemap_reduce$8373 $auto$simplemap.cc:126:simplemap_reduce$8585 $auto$simplemap.cc:126:simplemap_reduce$8581 $auto$simplemap.cc:38:simplemap_not$27957 $auto$ff.cc:266:slice$18948 $auto$ff.cc:479:convert_ce_over_srst$32431 $auto$simplemap.cc:126:simplemap_reduce$18956 $auto$simplemap.cc:75:simplemap_bitop$14023 $auto$simplemap.cc:38:simplemap_not$10750
Found an SCC: $auto$ff.cc:266:slice$14662 $auto$opt_expr.cc:617:replace_const_cells$31621 $auto$ff.cc:266:slice$14661 $auto$simplemap.cc:126:simplemap_reduce$14767 $auto$simplemap.cc:126:simplemap_reduce$14798 $auto$opt_expr.cc:617:replace_const_cells$31619 $auto$ff.cc:266:slice$14660 $auto$opt_expr.cc:617:replace_const_cells$31609 $auto$ff.cc:266:slice$14659 $auto$simplemap.cc:126:simplemap_reduce$14770 $auto$simplemap.cc:126:simplemap_reduce$14766 $auto$simplemap.cc:126:simplemap_reduce$14801 $auto$simplemap.cc:126:simplemap_reduce$14797 $auto$opt_expr.cc:617:replace_const_cells$31617 $auto$ff.cc:266:slice$14658 $auto$opt_expr.cc:617:replace_const_cells$31615 $auto$ff.cc:266:slice$14657 $auto$simplemap.cc:126:simplemap_reduce$14765 $auto$opt_expr.cc:617:replace_const_cells$31605 $auto$simplemap.cc:126:simplemap_reduce$14796 $auto$ff.cc:266:slice$14656 $auto$ff.cc:266:slice$14655 $auto$simplemap.cc:225:simplemap_logbin$14749 $auto$simplemap.cc:196:simplemap_lognot$14776 $auto$simplemap.cc:126:simplemap_reduce$14774 $auto$simplemap.cc:126:simplemap_reduce$14772 $auto$simplemap.cc:126:simplemap_reduce$14769 $auto$simplemap.cc:126:simplemap_reduce$14764 $auto$simplemap.cc:196:simplemap_lognot$14807 $auto$simplemap.cc:126:simplemap_reduce$14805 $auto$simplemap.cc:126:simplemap_reduce$14803 $auto$simplemap.cc:126:simplemap_reduce$14800 $auto$simplemap.cc:126:simplemap_reduce$14795 $auto$opt_expr.cc:617:replace_const_cells$31613 $auto$ff.cc:266:slice$14654 $auto$simplemap.cc:167:logic_reduce$8352 $auto$simplemap.cc:225:simplemap_logbin$14748
Found an SCC: $auto$ff.cc:266:slice$14827 $auto$opt_expr.cc:617:replace_const_cells$31523 $auto$ff.cc:266:slice$14826 $auto$simplemap.cc:126:simplemap_reduce$15142 $auto$opt_expr.cc:617:replace_const_cells$31521 $auto$ff.cc:266:slice$14825 $auto$ff.cc:266:slice$14824 $auto$simplemap.cc:126:simplemap_reduce$15145 $auto$simplemap.cc:126:simplemap_reduce$15141 $auto$opt_expr.cc:617:replace_const_cells$31519 $auto$ff.cc:266:slice$14823 $auto$opt_expr.cc:617:replace_const_cells$31517 $auto$ff.cc:266:slice$14822 $auto$simplemap.cc:126:simplemap_reduce$15140 $auto$ff.cc:266:slice$14821 $auto$ff.cc:266:slice$14820 $auto$simplemap.cc:126:simplemap_reduce$15149 $auto$simplemap.cc:126:simplemap_reduce$15147 $auto$simplemap.cc:126:simplemap_reduce$15144 $auto$simplemap.cc:126:simplemap_reduce$15139 $auto$opt_expr.cc:617:replace_const_cells$32205 $auto$ff.cc:266:slice$14819 $auto$simplemap.cc:126:simplemap_reduce$8464 $auto$simplemap.cc:196:simplemap_lognot$15151
Found 4 SCCs in module processorci_top.
Found 4 SCCs.

12.42.5. Executing ABC9_OPS pass (helper functions for ABC9).

12.42.6. Executing PROC pass (convert processes to netlists).

12.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

12.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

12.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

12.42.6.4. Executing PROC_INIT pass (extract init attributes).

12.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

12.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

12.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

12.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

12.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).

12.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

12.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

12.42.6.12. Executing OPT_EXPR pass (perform const folding).

12.42.7. Executing TECHMAP pass (map to technology primitives).

12.42.7.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v
Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

12.42.7.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~162 debug messages>

12.42.8. Executing OPT pass (performing simple optimizations).

12.42.8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.

12.42.8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

12.42.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

12.42.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Performed a total of 0 changes.

12.42.8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

12.42.8.6. Executing OPT_DFF pass (perform DFF optimizations).

12.42.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..

12.42.8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.

12.42.8.9. Finished OPT passes. (There is nothing left to do.)

12.42.9. Executing TECHMAP pass (map to technology primitives).

12.42.9.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_map.v
Parsing Verilog input from `/usr/local/share/synlig/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

12.42.9.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1047 debug messages>

12.42.10. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_model.v
Parsing Verilog input from `/usr/local/share/synlig/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

12.42.11. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

12.42.12. Executing ABC9_OPS pass (helper functions for ABC9).

12.42.13. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

12.42.14. Executing TECHMAP pass (map to technology primitives).

12.42.14.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v
Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

12.42.14.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $not.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~201 debug messages>

12.42.15. Executing OPT pass (performing simple optimizations).

12.42.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~18 debug messages>

12.42.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

12.42.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

12.42.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

12.42.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.42.15.6. Executing OPT_DFF pass (perform DFF optimizations).

12.42.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

12.42.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.42.15.9. Rerunning OPT passes. (Maybe there is more to do..)

12.42.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

12.42.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

12.42.15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

12.42.15.13. Executing OPT_DFF pass (perform DFF optimizations).

12.42.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

12.42.15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

12.42.15.16. Finished OPT passes. (There is nothing left to do.)

12.42.16. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

12.42.17. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 7198 cells with 47596 new cells, skipped 4273 cells.
  replaced 3 cell types:
     930 $_OR_
     267 $_XOR_
    6001 $_MUX_
  not replaced 8 cell types:
      12 $scopeinfo
     311 $_NOT_
     700 $_AND_
     844 TRELLIS_FF
    1044 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
    1044 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
     317 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $__ABC9_SCC_BREAKER

12.42.17.1. Executing ABC9_OPS pass (helper functions for ABC9).

12.42.17.2. Executing ABC9_OPS pass (helper functions for ABC9).

12.42.17.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 20434 AND gates and 59738 wires from module `processorci_top' to a netlist network with 5031 inputs and 1158 outputs.

12.42.17.4. Executing ABC9_EXE pass (technology mapping using ABC9).

12.42.17.5. Executing ABC9.
Running ABC command: "built in abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5031/   1158  and =   18656  lev =   35 (1.32)  mem = 0.56 MB  box = 1361  bb = 1044
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 2 carries.
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5031/   1158  and =   23512  lev =   63 (1.24)  mem = 0.61 MB  ch = 2036  box = 1345  bb = 1044
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 2 carries.
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   64. Obj =  148. Set =  672. CutMin = no
ABC: Node =   23512.  Ch =  1413.  Total mem =    7.17 MB. Peak cut mem =    0.26 MB.
ABC: P:  Del = 4920.00.  Ar =   17961.0.  Edge =    23152.  Cut =   280737.  T =     0.13 sec
ABC: P:  Del = 4920.00.  Ar =   18196.0.  Edge =    23443.  Cut =   279321.  T =     0.14 sec
ABC: P:  Del = 4920.00.  Ar =   12013.0.  Edge =    23689.  Cut =   718327.  T =     0.31 sec
ABC: F:  Del = 4920.00.  Ar =    7713.0.  Edge =    20321.  Cut =   385687.  T =     0.17 sec
ABC: A:  Del = 4920.00.  Ar =    7016.0.  Edge =    18674.  Cut =   365137.  T =     0.24 sec
ABC: A:  Del = 4920.00.  Ar =    6949.0.  Edge =    18618.  Cut =   369716.  T =     0.24 sec
ABC: Total time =     1.24 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   5031/   1158  and =   15420  lev =   28 (1.29)  mem = 0.52 MB  box = 1344  bb = 1044
ABC: Mapping (K=7)  :  lut =   4714  edge =   18515  lev =   10 (0.65)  Boxes are not in a topological order. Switching to level computation without boxes.
ABC: levB =   28  mem = 0.25 MB
ABC: LUT = 4714 : 2=542 11.5 %  3=738 15.7 %  4=2377 50.4 %  5=774 16.4 %  6=142 3.0 %  7=141 3.0 %  Ave = 3.93
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 2 carries.
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 13.09 seconds, total: 13.09 seconds

12.42.17.6. Executing AIGER frontend.
<suppressed ~12407 debug messages>
Removed 20935 unused cells and 47990 unused wires.

12.42.17.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     4724
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1044
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      300
ABC RESULTS:           input signals:     1119
ABC RESULTS:          output signals:      215
Removing temp directory.

12.42.18. Executing TECHMAP pass (map to technology primitives).

12.42.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_unmap.v
Parsing Verilog input from `/usr/local/share/synlig/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

12.42.18.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000110 for cells of type $__ABC9_SCC_BREAKER.
No more expansions possible.
<suppressed ~2408 debug messages>
Removed 291 unused cells and 75918 unused wires.

12.43. Executing TECHMAP pass (map to technology primitives).

12.43.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

12.43.2. Continuing TECHMAP pass.
Using template $paramod$576843ec5da9d065ef43831af18f1bac63825d80\$lut for cells of type $lut.
Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut.
Using template $paramod$db5822478ed6a418c4a199568dca9e7cb946a4d1\$lut for cells of type $lut.
Using template $paramod$879e1dd6a8ca34d36027ce28194d88f09bc10893\$lut for cells of type $lut.
Using template $paramod$176ebd2802f2d72a57e31cf1e4be5cf71b802412\$lut for cells of type $lut.
Using template $paramod$7ebd053006fefd5a4368bea803813a6c7860a94a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$461cadc1bd5a9a618782c453f75bb6c15ef2c050\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$b32b4adb3089ef9abf18f06625d6d0a3de008d93\$lut for cells of type $lut.
Using template $paramod$8ae5e24171bca0b8d12d43741a6723f274290f92\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$dd6a0556caf37ed7c9a40f6e9488ec973a729ee2\$lut for cells of type $lut.
Using template $paramod$2909c12c802825faea973fcade6ac36ccfd36e7f\$lut for cells of type $lut.
Using template $paramod$886de1b72ab1b0a51ce68f21a77c7a85e1a3262b\$lut for cells of type $lut.
Using template $paramod$857a42fadedfdd61ff917275c2a67673be62e038\$lut for cells of type $lut.
Using template $paramod$9ce19f1d75fc8c2890e9c51665a7d9e2e6953f54\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$26918802e6ed329b7afdcbcae3efbad76693779f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$95ce5b8dfb4a8891fc62c1ef4e32c8af460c9c7c\$lut for cells of type $lut.
Using template $paramod$c16f370ae7798b1bdf00bba0fa0d15e5edfce48d\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$0650d79817267033f7b6734f54159aee481fd78d\$lut for cells of type $lut.
Using template $paramod$ca357517489332a2cf261ee222c33ad12293e4d5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$20f82dd03802038bc013e5804609eaebb5d257db\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$ce15874c299a587dd16825ec2d2d2759b547554e\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$8c14e6d85060218e346675600ae1194fdf5a803e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut.
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$eced46750b43aa9efabd63e9db30cd976a863157\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$b9f1cc075fd5e1dc13f6aa9fc152bf79a0f71ef7\$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$1c7d8014a4d7918ee35a20538945662d20569ae6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$051b0f149cc6cdcadf3c24e3a7154fd78d1f7f19\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$14156b2616c16a10f2581287a57d3343ee88c698\$lut for cells of type $lut.
Using template $paramod$0c5a54c406cdb1ed108583f5d43071050a5e4d5c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$dd37cd23134cff028f2f6c89a8b24252334214d8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$e26686038120ac06db50efdb84758206882f9aaa\$lut for cells of type $lut.
Using template $paramod$a2241d5ec0a8f3e22a06d121139c830891d880d6\$lut for cells of type $lut.
Using template $paramod$e6cfc2a250ad5b0b3da266fa46a057a6eca6e3d9\$lut for cells of type $lut.
Using template $paramod$ec7a8a5417c175587f33c9e1164725c18f5a3cd4\$lut for cells of type $lut.
Using template $paramod$f27961905690c345277eaf00fab2c2234085d12b\$lut for cells of type $lut.
Using template $paramod$244955618a510e4a80414dbc0f64e83b0827188c\$lut for cells of type $lut.
Using template $paramod$f676d7dc356bd881625e7361b11bb80a06e9b7a7\$lut for cells of type $lut.
Using template $paramod$81cdc00d32c586d379feaa932cc25a9d9eb4f885\$lut for cells of type $lut.
Using template $paramod$a4ae881b85b2ce45956bc5db66140f164630be8f\$lut for cells of type $lut.
Using template $paramod$0bec256e287048b7c9f85c83203f801ac7caa352\$lut for cells of type $lut.
Using template $paramod$2a39ce4f9a8d7ee3f0d4cb27325ed920419df8e8\$lut for cells of type $lut.
Using template $paramod$bffbc92952163360ab46e89e211c634ca2e2cfb5\$lut for cells of type $lut.
Using template $paramod$1b7b25e4d4739c7c11d344801b334b6300580ea5\$lut for cells of type $lut.
Using template $paramod$512ad28d041d020b5b94d24dfd664f12580d7506\$lut for cells of type $lut.
Using template $paramod$db96c30226a807218dc12302236cc34e17a67f3c\$lut for cells of type $lut.
Using template $paramod$f0e629c931dd2cc394365a558ff648d99af72d97\$lut for cells of type $lut.
Using template $paramod$b3cf679aa6b7e21e6492496ff50aa71d9c1edef2\$lut for cells of type $lut.
Using template $paramod$06e298b931517c8a57cbd83651ac67398be1d2bf\$lut for cells of type $lut.
Using template $paramod$619cdf448d17b94203b8fc3e5f71468251e03e0a\$lut for cells of type $lut.
Using template $paramod$4870a513e3a9cd28f606753a4ab8250c000abe79\$lut for cells of type $lut.
Using template $paramod$4ec45f8bc6a62888d370a2cb3c4a334e0392e3d4\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$ceecf4ac8d47cbdc151f82fdf4032818e4fdaef5\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$7e3b74631bdfa3406ea1ab36245637ef43ba4560\$lut for cells of type $lut.
Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1\$lut for cells of type $lut.
Using template $paramod$6e64c13666511ae2ccc90ab6ddaf8be09bda5af2\$lut for cells of type $lut.
Using template $paramod$a62df8a802d9b82017aa298160c046cfb5568d60\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$659a283a1e6bcf695d44e2f641692d07efcbd3cd\$lut for cells of type $lut.
Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut.
Using template $paramod$5b17484c2590736ad70267419f134a32681b2631\$lut for cells of type $lut.
Using template $paramod$d80c9b99dacb354fa564a6fcc23ca30753bf6623\$lut for cells of type $lut.
Using template $paramod$cba7d4f63aea5e4b3faf052f9f9805e0c6d202cb\$lut for cells of type $lut.
Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$162444840ff3de9ca00172a33886d3c68fa9b88a\$lut for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$48391ae1473025a790c629d1c297bc6d36cccac5\$lut for cells of type $lut.
Using template $paramod$d4b8f08be5022193a69dfe31654c06b8c2e1ac1d\$lut for cells of type $lut.
Using template $paramod$1df184be438c7f1377f3400a91d761a3a7e89b05\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$c4eb6917e0e8b32f4d7e2137343203842aff51f1\$lut for cells of type $lut.
Using template $paramod$e66740ee896088d79400dc7ffaf9390d71786a3d\$lut for cells of type $lut.
Using template $paramod$5c6d01824df27a97c3776b3694e8814e23c197cd\$lut for cells of type $lut.
Using template $paramod$4ecd20e5c26b907d2510f6edbf0ddfc3b079ed41\$lut for cells of type $lut.
Using template $paramod$d0d573560673a9ceb97d93faba7d833a6340868e\$lut for cells of type $lut.
Using template $paramod$7947673503ebe0795857dbc35e6477d498481681\$lut for cells of type $lut.
Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut.
Using template $paramod$37eb25785b00801af8fc818b0d50dd3a20605e83\$lut for cells of type $lut.
Using template $paramod$5a6bad73d3629f06fe4104aa65830b516741b37c\$lut for cells of type $lut.
Using template $paramod$9eaabafe459be125f48a5e46558dd0084a2c0d60\$lut for cells of type $lut.
Using template $paramod$5f62cfc08101ac3abd993b56c04ac2877fceda5d\$lut for cells of type $lut.
Using template $paramod$aeb27cd9efe624def2282ecf09671da132bf31e8\$lut for cells of type $lut.
Using template $paramod$130af793a2ec6ecceb3e0ef509cf6b180e856b6f\$lut for cells of type $lut.
Using template $paramod$72999a7ffa547571d7240ef55378d6675343dc1c\$lut for cells of type $lut.
Using template $paramod$9ea34eb01f9b75f8b9132856d9e5332a707924f2\$lut for cells of type $lut.
Using template $paramod$92ae8cf9291da386060b54ece8d2ebc234f6e27d\$lut for cells of type $lut.
Using template $paramod$c6d059e080b09ab343ca6060ef12b8eed2642a75\$lut for cells of type $lut.
Using template $paramod$4214c9d54213db9d1ee0c07b47c899c2cd4c4f2e\$lut for cells of type $lut.
Using template $paramod$c6e1a97e3cbbb2733a8db100b892ff88030f0c9a\$lut for cells of type $lut.
Using template $paramod$33e78c0d17434939ae2fbe5531afa4bed6554b29\$lut for cells of type $lut.
Using template $paramod$debcc7cccc545f2581c51d99a6ac6aa109f04913\$lut for cells of type $lut.
Using template $paramod$e4857636d35dc9b5293045a985a317a436a4713f\$lut for cells of type $lut.
Using template $paramod$97b1cabfe93eb70f63d2f8ed944b3ac1002fad2b\$lut for cells of type $lut.
Using template $paramod$98dd5f38e0117c44d93d8e3812b44b0b0edd2ec0\$lut for cells of type $lut.
Using template $paramod$5292ee56af9b5b82806b8eda525aa33bb5ea38ac\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$a0f67318f1c24388c545d8c57553aed79a7a9a84\$lut for cells of type $lut.
Using template $paramod$058828a31692d50d5a6e790289a407a601e0e4aa\$lut for cells of type $lut.
Using template $paramod$f4459bc2ab9d0bffb290e426e5e53be7edbcebe9\$lut for cells of type $lut.
Using template $paramod$a6e85f8275fef179cc0a3f7b6826c981a91066fe\$lut for cells of type $lut.
Using template $paramod$22c9540e6b3191f825dc7dfff9da22920c3db73f\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$67fa53079304439ff536a5f09046a542bd29cfdc\$lut for cells of type $lut.
Using template $paramod$df7d3692924ad20986050a8a137f6781b5d77b70\$lut for cells of type $lut.
Using template $paramod$6afbf864e7730063e4884ed2d846c0a28956b580\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$c91ebb38937ac98aefe8c9a96539c3101997fe63\$lut for cells of type $lut.
Using template $paramod$cbb2dfe31d344d3326d567c2ed5a4b2a29f63219\$lut for cells of type $lut.
Using template $paramod$01ab972aab20d2f99be84146af88bbae3b2f5111\$lut for cells of type $lut.
Using template $paramod$dd351332a44263d6274369352ca1bd334f12f053\$lut for cells of type $lut.
Using template $paramod$8bfc0eeaaa84d2880b5de3926653cc1bb2fa4de7\$lut for cells of type $lut.
Using template $paramod$97aad10eeec1080a92bba752f9b085a6e1a07646\$lut for cells of type $lut.
Using template $paramod$d0ecd2cbaa0078163be6da2d181c42087b0d86c9\$lut for cells of type $lut.
Using template $paramod$57cf7fbf84518d9e7604ec42b59ba9511e1f3caf\$lut for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut.
Using template $paramod$25de935055baea42834794ed3ab25d96968bb13b\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$0fcb06ed76df01e8d45bc2b9e6c8a9b43fa42cb4\$lut for cells of type $lut.
Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad\$lut for cells of type $lut.
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut.
Using template $paramod$3b383aa74b05b60cb9cabc0ba0eca4dea92c2b33\$lut for cells of type $lut.
Using template $paramod$810e0f22d547104f8208898922f6ac2444aeece7\$lut for cells of type $lut.
Using template $paramod$f7e1711ce97b6b07e578616ec403db7268ddce97\$lut for cells of type $lut.
Using template $paramod$464d286cc302627c2e44b6c4a8450c9bebc28389\$lut for cells of type $lut.
Using template $paramod$5eade7c43026a770e3e647590c1378f4476f00e5\$lut for cells of type $lut.
Using template $paramod$25696d6b21c8ac3da9913114964545779e21cfa5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut.
Using template $paramod$7ff1fccad2e83dcddddfb88fb755c484352b8dd4\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$672e798a02b8bcc43378b3bcf167b71b5747401f\$lut for cells of type $lut.
Using template $paramod$44c0fe996e6f3f4ba8bae2e194245aa82c30fa47\$lut for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$983adbc56c7400f95b406f02e82bd0da8b98fd00\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$0defb1586b24785b85905f661056d6b3d902c0c8\$lut for cells of type $lut.
Using template $paramod$d5c7dda3e544463bf43ed73dadb51262f5dcf2fe\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$369624b024132c6d54ca5ca0dec0683515f4f203\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut.
Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut.
Using template $paramod$12d55b60f0f4993cdeef74f2f65f385722841c5f\$lut for cells of type $lut.
Using template $paramod$b3f8492b654d6f4d7d1d31e0c18d0c5631447158\$lut for cells of type $lut.
Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$af2b970363478c934f632261f05f42c59b0d7a99\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut.
Using template $paramod$38e1736814af31c180a1bbf9f565814e3ed34869\$lut for cells of type $lut.
Using template $paramod$17f1b90a5c6d7e6613368c5e7d3f44dd634e59e2\$lut for cells of type $lut.
Using template $paramod$dcba541ad53a9873d71bfba6c13dc2a8e2a60a79\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$b26fbfdb68e98cf016d61a8611b449e9f4a30f3c\$lut for cells of type $lut.
Using template $paramod$f626b575273537b3090dbe5d04b27b283ec9a192\$lut for cells of type $lut.
Using template $paramod$52953750219effadf43093a566baf492fdd6b6c8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$8cc44e7dc7e5476c7b083e476581e55f230c87db\$lut for cells of type $lut.
Using template $paramod$d901b7cb1a1da2b1c47f76b773158f002e0c7eb1\$lut for cells of type $lut.
Using template $paramod$2f5347e24f830bd8bfde3759a0646d71c474b35a\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$0c9da3c8d9db4ced37f391c3e84409664c4c8791\$lut for cells of type $lut.
Using template $paramod$d7478d457321afe61b208a896c257fafee460cdd\$lut for cells of type $lut.
Using template $paramod$9851cb11f88bbbf4a516c0595f3b0113b1f100c4\$lut for cells of type $lut.
Using template $paramod$2bec7593ac5b890d7d67f2d17be8418c1b52bad1\$lut for cells of type $lut.
Using template $paramod$b18baa3110bae773b5e5c44152e004d88297b421\$lut for cells of type $lut.
Using template $paramod$0e793476c76346bd792d37eb2a8620c559463304\$lut for cells of type $lut.
Using template $paramod$e5b29079c1a88f3fc663c746ec8e3359690ef674\$lut for cells of type $lut.
Using template $paramod$b089060a61c5d29ddce66d73edb5ee493ec9de27\$lut for cells of type $lut.
Using template $paramod$2a2d4c86167109f1e1c123aeaa7489a318c9881b\$lut for cells of type $lut.
Using template $paramod$20eff2533f7cb98a1ac35ca44db089a3ec2c6fc4\$lut for cells of type $lut.
Using template $paramod$da45f6470d9fb70af1012bd9e3b5d49af3903ab1\$lut for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$eb5824218569a85619c7eddcf7f115a0bbb9342c\$lut for cells of type $lut.
Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$949912d41b6703327b37a3cbe8a7a7bc923219b7\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010001 for cells of type $lut.
Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut.
Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut.
Using template $paramod$ac0fa5d7a90a8bbe2427a08d007dd31ff56eaf3f\$lut for cells of type $lut.
Using template $paramod$50ae037bea16070af222263fc6c06efd57346ae1\$lut for cells of type $lut.
Using template $paramod$ba05b8a1a425003df083aea0e69541f5cbdc68f2\$lut for cells of type $lut.
Using template $paramod$c6a1f9ea79b7bb1672d5d3c63312684d0f3defb6\$lut for cells of type $lut.
Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut.
Using template $paramod$765dca61dbfa835dacf2a260c8a4c5a36939a046\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45\$lut for cells of type $lut.
Using template $paramod$3c5eb16fa418cfbbe1710d24d17e7d0b5448c3c1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b\$lut for cells of type $lut.
Using template $paramod$98e99942f364173ee1da9b31f34c7829f11e4be1\$lut for cells of type $lut.
Using template $paramod$39a3022e55aa03d0b5478da3a6d9fcb662c62e56\$lut for cells of type $lut.
Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut.
Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$efc60783c939ae41b2f3555af407b17c007b27f8\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$0a4d85497e20c50068555dd5ad9ad3a7952cab73\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod$a5d5c745abad930299600272e8260a256cf53240\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$11c86b7a6cb6e98dcfb16c5f4d4cc1052b93d8a4\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$34d8179c3f4e5c9b014184678126740a73fec819\$lut for cells of type $lut.
Using template $paramod$31114d87be01f977936de4d238d2be8c5bca7194\$lut for cells of type $lut.
Using template $paramod$4f8edd664328039cee7936fba43b73a91069e069\$lut for cells of type $lut.
Using template $paramod$87cad75e5228984b6c2387055450005570b7eea8\$lut for cells of type $lut.
Using template $paramod$edb5e3f11a3d3283a20e1b8331e255940671d5c0\$lut for cells of type $lut.
Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut.
Using template $paramod$90e17302fa78c05fb2e941a1df9b1d9b4ad1170d\$lut for cells of type $lut.
Using template $paramod$b888b70a5f7e5362c3d8df906c5f324feaeffd36\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111001 for cells of type $lut.
Using template $paramod$4b815e6c998e04ad0d0242e44b0c58a7a9d0b3b6\$lut for cells of type $lut.
Using template $paramod$a9ce27937a83ad5f912b4564fe247b26679e1c7b\$lut for cells of type $lut.
Using template $paramod$4e7e1ecf88cc043c46be94d5c3ca9e430ef9814c\$lut for cells of type $lut.
Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut.
Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut.
Using template $paramod$12e9049d8709286a770fe60b59ec4d94c39ce3c9\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$813413d46ba2602dffdafe65045fe8b850de805f\$lut for cells of type $lut.
Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut.
Using template $paramod$3f8bddb26a8905ea147acf4247acf6d000ca20f7\$lut for cells of type $lut.
Using template $paramod$e718d2f5eb562e6029d6a1b1e060511bf1c65df1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut.
Using template $paramod$7d813eb49700f971f2635a434700eafdfa816bc3\$lut for cells of type $lut.
Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut.
Using template $paramod$9a6dd4ade5155328254b56c204046aa5d03d4faf\$lut for cells of type $lut.
Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut.
Using template $paramod$3569febfcd573671a7379d968b60becf1fda99f7\$lut for cells of type $lut.
Using template $paramod$0d98dc10c74f08927e02f9dbb8997446e190eab8\$lut for cells of type $lut.
Using template $paramod$80988c43f318602d7fbaedec0644aee2e766b204\$lut for cells of type $lut.
Using template $paramod$9998c61c50285bf1d3dc1a1ed624f8f310df58c4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$68ca57e964735ac63ed672a5c778148a2531293c\$lut for cells of type $lut.
Using template $paramod$ba5735bb1a246748109d851b6ab5abadef7d9b0d\$lut for cells of type $lut.
Using template $paramod$f120563e393cbebc71bcd685830ceda18dc8c013\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$648d5b3c4c08a2b5e6752f60f9134dd7da5b02b9\$lut for cells of type $lut.
Using template $paramod$13fa9273f1d4ad6050109d02dc87cffc90450a95\$lut for cells of type $lut.
Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut.
Using template $paramod$e2703f2296fab2fbf04a64f5bb5633bde82910c1\$lut for cells of type $lut.
Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut.
Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut.
Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636\$lut for cells of type $lut.
Using template $paramod$e277a522d8a930c8c8c8cdb56d33d42914aefec4\$lut for cells of type $lut.
Using template $paramod$62e34d236b5cf9e50e7481784c0097067a15fba4\$lut for cells of type $lut.
Using template $paramod$bacdb2105cbfbe75cfbcc2fb021fd3aba864526b\$lut for cells of type $lut.
Using template $paramod$4f09540800ac966d6e31a7ccf5f32a559a8ce57a\$lut for cells of type $lut.
Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut.
Using template $paramod$8417bd18654099a39056bad5f2790a28443b19e5\$lut for cells of type $lut.
Using template $paramod$d47075a53ff1dff553bbe454ba83286b2e9de7dd\$lut for cells of type $lut.
Using template $paramod$cffc6ae87e2643c54b07604cb7b8203d2d06760d\$lut for cells of type $lut.
Using template $paramod$07b1b12ce0305f55108770e958fd02caedfebdf8\$lut for cells of type $lut.
Using template $paramod$1ad9ca75a5e52e69f39f16c0b8ffb14773a0b7f2\$lut for cells of type $lut.
Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
Using template $paramod$12efc86bf2818a298303d831b00a54492f688afd\$lut for cells of type $lut.
Using template $paramod$83c164efc0cfaeade1b523d878ce92eca74d52fa\$lut for cells of type $lut.
Using template $paramod$65d6343bf57e6e1dc263ea36e76f30b39a5a1ef4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$c1f081fa9b9062fed4a693c382cabca36a3581a3\$lut for cells of type $lut.
Using template $paramod$e3528e0a03ffaa5957b993fa1d2fd84bc89a9b80\$lut for cells of type $lut.
Using template $paramod$3eb8805ccd6f91bad96dcbf190c2fb4f72f4634f\$lut for cells of type $lut.
Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut.
Using template $paramod$29c142aa8fa1002414251345df2e74414f35d86d\$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut.
Using template $paramod$6f3f060a82077d7722793a80a7f81ffcda8e7f4d\$lut for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$5a2475f0ff8adfa6c48e46c1977dad3962daa33d\$lut for cells of type $lut.
Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$faf4b69e2195a9ce52b7c3bce83fa5ea343bc378\$lut for cells of type $lut.
Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut.
Using template $paramod$18df3812bc12364e5ebcb6c3ed05c0294e4c26fc\$lut for cells of type $lut.
Using template $paramod$a23bde83d26849bc8c55e17143c36b6f506a1b34\$lut for cells of type $lut.
Using template $paramod$1e9faef0228fd0cfa5408ab5c5e15544877f4836\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$afb8959a93937986ded51b1cddcab9e31c6ea2ed\$lut for cells of type $lut.
Using template $paramod$061bf509610e3c6080c8b516973b11121df0b78c\$lut for cells of type $lut.
Using template $paramod$903905cca899aab473483ca27c3db12d7108e3a5\$lut for cells of type $lut.
Using template $paramod$200337237619ba4c0bed9a492562f1d1b57fb569\$lut for cells of type $lut.
Using template $paramod$947725aec98a9f18ff21139ab8c0f14697acf4b2\$lut for cells of type $lut.
Using template $paramod$8cac5452d526045503c5864c3a1dac0121c7053e\$lut for cells of type $lut.
Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$a9ebd93bc2fc1a9f7fc387533c3e17044ba51058\$lut for cells of type $lut.
Using template $paramod$689255407ca86ad992a9ce6973b8de567f5df196\$lut for cells of type $lut.
Using template $paramod$a73f8f46f0905730b1b0d0e93e1e4a8fa5695cec\$lut for cells of type $lut.
Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut.
Using template $paramod$fce992df4978ad69e56d150579aa6ba47bc13a78\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut.
Using template $paramod$d108746cf2a09e71d9dc612f174b3c5e7be80328\$lut for cells of type $lut.
Using template $paramod$c1f6e14bf850d506408a22233ac34c8f37217261\$lut for cells of type $lut.
Using template $paramod$0c4bf7f90dfa61960f1a574188c7812e994dad89\$lut for cells of type $lut.
Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut.
Using template $paramod$58b33073d6510d6145ff01c28a604d07765b1342\$lut for cells of type $lut.
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut.
Using template $paramod$18455d4fd1270af2266bf4bb1c44971b2eb6b37a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut.
Using template $paramod$19fe1ba23ba7fdb117bb75432cd43fbe2b988d53\$lut for cells of type $lut.
Using template $paramod$dd3f9015128047ac2d55add992936456be7aadfb\$lut for cells of type $lut.
Using template $paramod$1b292dfca1a62bf07c745cb22add5dcc3dce70dd\$lut for cells of type $lut.
Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut.
Using template $paramod$7c3833e617307006af30409ed68b65a011a1121e\$lut for cells of type $lut.
Using template $paramod$cdfb4ce36e9b97ab980954e4bd7262833a7086a8\$lut for cells of type $lut.
Using template $paramod$ab5f6cbda813df0763ad05c5e0cfe5a674acf259\$lut for cells of type $lut.
Using template $paramod$adfe923f18aeb12b253f7e2aab06ea1c2e048a45\$lut for cells of type $lut.
Using template $paramod$010d9e7260a28ffa3b7871e475819281e7f16f47\$lut for cells of type $lut.
Using template $paramod$bffe9d8c0c94254b4cbd9b3815d51a8270953936\$lut for cells of type $lut.
Using template $paramod$00b29f251060f06067cde261039b0cf684919ac9\$lut for cells of type $lut.
Using template $paramod$ad674a6677838b57bc50152bb2f06ef155538d5d\$lut for cells of type $lut.
Using template $paramod$fd5f9f6473eab1cf0b3278781b94ff30ae30905f\$lut for cells of type $lut.
Using template $paramod$eadbfb46c348c82b7975ec20f659a19c59a68112\$lut for cells of type $lut.
Using template $paramod$fa784f6f6cd8d340af9807fab73d1da519000865\$lut for cells of type $lut.
Using template $paramod$c6c5c0866bedba0b11c0c33a09adb57704fdc1eb\$lut for cells of type $lut.
Using template $paramod$5480e1bb8536b88b3418601d1fbc28d4ecc87a09\$lut for cells of type $lut.
Using template $paramod$20f3f4b8e32f8a8b038b0056872dc94926194798\$lut for cells of type $lut.
Using template $paramod$36e77cf68e95b3b8cccf1bb5b64409630f2c88d1\$lut for cells of type $lut.
Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut.
Using template $paramod$1875a64980687d84476cca9206287369bec7f34d\$lut for cells of type $lut.
Using template $paramod$341dfb87e06f69bf04389257026cab683799d65f\$lut for cells of type $lut.
Using template $paramod$952d1467c6f0b2e537a4df6d594c34569171e5d0\$lut for cells of type $lut.
Using template $paramod$8d3a93c8dd39d9a0e2fdc24e03d1bc418471679a\$lut for cells of type $lut.
Using template $paramod$250e9ed6c15020113b6b30a5ef7c8f11f208ca8e\$lut for cells of type $lut.
Using template $paramod$71c782b489750a75e5d94a68c129740de7407998\$lut for cells of type $lut.
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut.
Using template $paramod$745b81833ddf166b613847245d7849b70669b494\$lut for cells of type $lut.
Using template $paramod$2c2dc1e712eb09b3e837ea657c9126c7b73de4d7\$lut for cells of type $lut.
Using template $paramod$6d3ff2249b75859a5b3ab418eca6f7d98ed48047\$lut for cells of type $lut.
Using template $paramod$adef88b71e0eed8050f8ed4dc3aa81740ec1c3e7\$lut for cells of type $lut.
Using template $paramod$550b997c78458b09f9c5508bab5bcac9d0dec938\$lut for cells of type $lut.
Using template $paramod$7ab2d32d202d5aa87ba27d425289ab6e2fdfcd1a\$lut for cells of type $lut.
Using template $paramod$bc09e6bc278accee6d588282634b5352c92b43d5\$lut for cells of type $lut.
Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d\$lut for cells of type $lut.
Using template $paramod$1f679301e11279c4af2a899182d47882af80ad14\$lut for cells of type $lut.
Using template $paramod$d939a5a789eec56f7727056d897b7d53657d2106\$lut for cells of type $lut.
Using template $paramod$5afe21d6fdc7c33aeb338fdb508ea02813207bfd\$lut for cells of type $lut.
Using template $paramod$12ab4ac9a458997cfab0c618d6b4e5b6b68b140c\$lut for cells of type $lut.
Using template $paramod$b2d4da7bd51df285f0bc0956519ab8a2e6d9a000\$lut for cells of type $lut.
Using template $paramod$06457edff985ac2621f32f6418c0f1e49baaf820\$lut for cells of type $lut.
Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut.
Using template $paramod$911589a8ac6d190cf9f90bd95129fad539ab76d5\$lut for cells of type $lut.
Using template $paramod$c6cfd89d797af1a317c03e52360d69b458d1d5ec\$lut for cells of type $lut.
Using template $paramod$625b44527a6320960a991295842340eeca84d995\$lut for cells of type $lut.
Using template $paramod$f6bad0c59ab167149c1805436d46cf42ed9a1b1b\$lut for cells of type $lut.
Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$e35ae36554ad61a1ad94da3bae227a28cdbf1aa4\$lut for cells of type $lut.
Using template $paramod$52f98a97841a570af09358e5d1366323d88663f8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$0f781d9bcf08c1e5dbae258ad4233d25c7328f2f\$lut for cells of type $lut.
Using template $paramod$d5b95ef1c89d834e3e72966caf0c9ff97c5cfa95\$lut for cells of type $lut.
Using template $paramod$0517fb01044da31a3b22edd53ea8ef5543f8966c\$lut for cells of type $lut.
Using template $paramod$137f74d8861423744b1783ae0260df331440aa44\$lut for cells of type $lut.
Using template $paramod$528f2802a6c1401e8a9814b2996a5f454e5327b9\$lut for cells of type $lut.
Using template $paramod$f66dddce965f1ebf0108d596b6a2f4031cd1781c\$lut for cells of type $lut.
Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$d8905128edf1384eccfd1b9f150a88db7c8175f1\$lut for cells of type $lut.
Using template $paramod$f0315d6003d354beedba111255ca7369b0f0d4ca\$lut for cells of type $lut.
Using template $paramod$68488f63d77cba57cc19937af3918f03e1260379\$lut for cells of type $lut.
Using template $paramod$1578333f1a5078051b84dbcbad362e8087bf5284\$lut for cells of type $lut.
Using template $paramod$69ca0f7c1494825b16aa3127759c16ac2790296a\$lut for cells of type $lut.
Using template $paramod$74c0f3179b5cebe485563ea55e9b637e7ee5c0c3\$lut for cells of type $lut.
Using template $paramod$b615004ebff9228145b881021ca021846a7f9002\$lut for cells of type $lut.
Using template $paramod$1f313f85ef575d13bac75382f04905a8c8be8f57\$lut for cells of type $lut.
Using template $paramod$6150d2f6e6ca7abf300267e422469f3af026940a\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$dd0a2d9fbf92ccc060bbb4525fc7ed88dc1ec1df\$lut for cells of type $lut.
Using template $paramod$0b6609cc8f4550cae49590e9f1045bfee789ad8d\$lut for cells of type $lut.
Using template $paramod$1632c1c0242796acfc963a05742c4acd2f475c4e\$lut for cells of type $lut.
Using template $paramod$6fb487e03b9eb2189ab4deaeea6214b936634463\$lut for cells of type $lut.
Using template $paramod$f405ee362848dd1a47c58160f854302f6ecf95ff\$lut for cells of type $lut.
Using template $paramod$52b0a90461cc6ec479cb8754d30da4ff7afb30e3\$lut for cells of type $lut.
Using template $paramod$28483cb637ee8fe4dd523d681451f035cd66b79b\$lut for cells of type $lut.
Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a\$lut for cells of type $lut.
Using template $paramod$55608858ecc0aa82350d501a1fbad74f74c9a072\$lut for cells of type $lut.
Using template $paramod$e6d1024eaee9364f18ed4ab4a476b8018bc3d9ca\$lut for cells of type $lut.
Using template $paramod$5ddea2745600cfd65315d9047bf1d3dedc34607f\$lut for cells of type $lut.
Using template $paramod$5e2c4e05bbdd2eaa20212f01bb8e88597c0f6680\$lut for cells of type $lut.
Using template $paramod$fcb30a1ef590387064e2bb0c918db1df4b073e24\$lut for cells of type $lut.
Using template $paramod$7a7f6ada1a295c605b484d0266088d2a6d14a87f\$lut for cells of type $lut.
Using template $paramod$ed9cf238d83340907346ef59d900269a70ac0648\$lut for cells of type $lut.
Using template $paramod$c214b4f4a9031361a7ff4859158ca8c9d48de37d\$lut for cells of type $lut.
Using template $paramod$2b67ef9118af19b656129dcc5fb7da42141255f5\$lut for cells of type $lut.
Using template $paramod$fda6887b37f599177ed9cb69271d882b63df7e66\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut.
Using template $paramod$d02990ad6060e1ccca018f046e62f43cde91b751\$lut for cells of type $lut.
Using template $paramod$fa45f28daf300aaa781ee4b9baa5ce968b1d8c66\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$fb4ed309581bcd972f41afa8566ae8b9812c7f6c\$lut for cells of type $lut.
Using template $paramod$187b265af118a45b7880d2dcc0524ee2abd6b591\$lut for cells of type $lut.
Using template $paramod$7fe48044d99531d56b2fc07984c92bfc01591fcf\$lut for cells of type $lut.
Using template $paramod$078a725d7245a429d31c2ec95904a26c239ee717\$lut for cells of type $lut.
Using template $paramod$1078665aa144cf7ff525a892db61e5cee078ce7c\$lut for cells of type $lut.
Using template $paramod$222a475794122d8f9a0548ccb740c0a3fabce248\$lut for cells of type $lut.
Using template $paramod$6e3a03c79073e44642e8ed2dab4ee82dfd40dfba\$lut for cells of type $lut.
Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705\$lut for cells of type $lut.
Using template $paramod$a8372e175876cbb66e220516f0b094622c6ad591\$lut for cells of type $lut.
Using template $paramod$7a0b348a7069d0c8f44afe945e212fcf3f3fd64c\$lut for cells of type $lut.
Using template $paramod$faa355e3a546873de087917018b61722824a2ee2\$lut for cells of type $lut.
Using template $paramod$409a0e544a97f4bccfaeb4cf629a05c58c57ce37\$lut for cells of type $lut.
Using template $paramod$38f9bf4dd2329347b8471f0a98443dd323386889\$lut for cells of type $lut.
Using template $paramod$891d17c049ef97ffbed57a5d4edf3f9e83d4f776\$lut for cells of type $lut.
Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut.
Using template $paramod$1388687c3c65d91c3d10b8cdb4cd5aa73f2d35ce\$lut for cells of type $lut.
Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut.
Using template $paramod$65c2e5789ae727746431093b75e8a544527553e0\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$9506ecf18c91672f3dae4008b6ad1f2863e8019f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$8be603794459732f9a374f76041b510fc63b115b\$lut for cells of type $lut.
Using template $paramod$1e9d7896e1dd3d2af9633eefc9c29afb478cef41\$lut for cells of type $lut.
Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut.
Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut.
Using template $paramod$6c543b558919ff57a92ac09985ad349c5934cfed\$lut for cells of type $lut.
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut.
Using template $paramod$b4f807a191cea4e6becb3c470f725682d5df1b0d\$lut for cells of type $lut.
Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut.
Using template $paramod$fddfaafad20e385d20971828336f8fb14f3d4f32\$lut for cells of type $lut.
Using template $paramod$ff4dd96a8adc011bb838ebb9d645764e57a15653\$lut for cells of type $lut.
Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut.
Using template $paramod$8c13ad014d500c3a349fa680995aa7f6f9eaaf87\$lut for cells of type $lut.
Using template $paramod$b637cf4714c2e93484bb499728e176a6ab69c910\$lut for cells of type $lut.
Using template $paramod$121f66828c71d3c18a58c99e9f44b94525cfca81\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut.
Using template $paramod$ca4d41379eb122514d1cb539e5736325e45c4a88\$lut for cells of type $lut.
Using template $paramod$833582361e14b3ee2e66ad676022ab35d7aa7e28\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut.
Using template $paramod$b18f60dfd13c21d3e472b89652353f3f5342b450\$lut for cells of type $lut.
Using template $paramod$937eaeeb63a1b85d8002bf1a4a34f80f9eeb9d76\$lut for cells of type $lut.
Using template $paramod$555682f6d7afbc6b26a8a5287a23dd436b742293\$lut for cells of type $lut.
Using template $paramod$96353c8e4d0a77a8c56bd6844da7d672aa918337\$lut for cells of type $lut.
Using template $paramod$9a91b51cf781dace9cdae572fb7cec9542aea0d8\$lut for cells of type $lut.
Using template $paramod$d4fae2c0d9ad2966369cd4e39b81c71bcd1327c9\$lut for cells of type $lut.
Using template $paramod$5b3e9401eaefa436f6fae7c2d31693e998d2c7b1\$lut for cells of type $lut.
Using template $paramod$3c2eecef1d5f85c82f4e1b2831501a2d442e93ee\$lut for cells of type $lut.
Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut.
Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut.
Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut.
Using template $paramod$17d4fb2077cb7df6fab11c907c67b6f08f6e17ae\$lut for cells of type $lut.
Using template $paramod$8e01d13e078e8177912f721c32dbabb20f78322d\$lut for cells of type $lut.
Using template $paramod$c089e8f8c94e66a4e6c7d8e92731760f73418cbf\$lut for cells of type $lut.
Using template $paramod$ff7b4776e95c73ef189816542c3a84d65b50b8d8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Using template $paramod$6e4a86e6f1a5dc8f826898a131e83cdba4a4fc9e\$lut for cells of type $lut.
Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut.
Using template $paramod$f94cf08026d21db794b98b1a8efaec5f34ff8975\$lut for cells of type $lut.
Using template $paramod$b254004e52e31d6991f04f6113897c64fa1650ce\$lut for cells of type $lut.
Using template $paramod$6790eb142d4504679f3b3597b4967f2cd5bb2451\$lut for cells of type $lut.
Using template $paramod$8c88b559aaf396c2bf544d61c1ccd2157a480a90\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut.
Using template $paramod$c24d0e2a94559837d969df5b5aaf84188feaf3d8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$e4c3984b0f292ec38c153e6818d5f5a1c58e4f5f\$lut for cells of type $lut.
Using template $paramod$17c2f243a1da896c622c9087a9b7432bee6819fa\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut.
Using template $paramod$fca82610c4582bae0c561edc640eb928b48fbdcf\$lut for cells of type $lut.
Using template $paramod$aae9ca9917d459d5338463ab9843dad4578b88dd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut.
No more expansions possible.
<suppressed ~11998 debug messages>

12.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in processorci_top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130411.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$25457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$25457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$25388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$25289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$25199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$25146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$25141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$25042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$23907.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$23765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$23675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$23468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$23407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$23261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$23189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$23011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22665.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$flatten\Core.$0\XSIMM[31:0][7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$flatten\Core.$0\XSIMM[31:0][7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21941.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21735.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21497.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$20970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$20545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$20322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$20273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$20147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$20147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$20147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$20147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19656.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19651.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19617.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3373[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3373[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut\Core.IDATAX[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut\Core.IDATAX[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$18998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$18998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$18998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$18998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$18998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$18998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$18810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$18810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$18688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$18109.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$17888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$17888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$17297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$17198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$16243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$16243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$15102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$12977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$12977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$12977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$12977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$12810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$12810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut\Core.IDATAX[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$12220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$12088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$0\XJAL[0:0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11397.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11229.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11229.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11229.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11229.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11229.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11161.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11161.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11161.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11161.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11161.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11161.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11161.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10553.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10829.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11623.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10539.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10377.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10437.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10449.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10703.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$10982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11161.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11229.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11229.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11440.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$10497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11713.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$11733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$11759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$0\XJAL[0:0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11855.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$11902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$12247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut\Core.IDATAX[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$12386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$12810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$12977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$13012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$13078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$13103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$13141.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$13227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13461.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$13660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$13857.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13890.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$13949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$13983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14107.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$14577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$14595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$14698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14791.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14989.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$15079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$15096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$15152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15285.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$15327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$15343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$15378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15696.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$15755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15771.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$15980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$16249.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$16308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$16364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16927.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$16968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$16984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$17162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$17178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$17198.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$17208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$17292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$17297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$17558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17799.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$17912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$17976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$18034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$18154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$18158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$18335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$18605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18787.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$18810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19031.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19081.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$19952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$19975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$20147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$20181.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20247.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$20302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$20322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20371.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20497.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20599.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20665.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20885.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$20970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$20977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21305.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21345.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21659.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$21924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$21936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$21977.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$22680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22697.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22825.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$22910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$22981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$23090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$23184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$23189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$23261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$23308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$23402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$23407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$23576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$23670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$23675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$23808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$23902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$23907.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23907.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24351.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24793.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24915.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$24952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$24961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$25042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$25052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$25136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$25141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$25146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$130144$lut$aiger130143$25199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$25289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$25383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$25388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$25409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$10844.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$24485.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$auto$opt_dff.cc:219:make_patterns_logic$3127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$auto$opt_dff.cc:219:make_patterns_logic$3316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$opt_dff.cc:253:combine_resets$3052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$rtlil.cc:2724:Not$3170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$auto$opt_dff.cc:219:make_patterns_logic$3036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3373[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$0\XSIMM[31:0][3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Controller.\Interpreter.$procmux$1793.Y[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$19143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$14995.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$18471.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3373[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22397.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$fsm_map.cc:170:map_fsm$2963[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$14432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$20204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$21029.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$22734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$23975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$24468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$25457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$11780.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$0\XJAL[0:0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$0\XSIMM[31:0][3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$0\XSIMM[31:0][7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut$aiger130143$10417.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$flatten\Core.$0$memwr$\REGS$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:558$753_DATA[31:0]$945[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$130144$lut$flatten\Core.$0\XSIMM[31:0][7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$flatten\Core.$ternary$/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:596$970_Y[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$23912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$aiger130143$19301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut$auto$wreduce.cc:461:run$3381[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$130144$lut\Core.IDATAX[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut\Core.IDATAX[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut\Core.IDATAX[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut\Core.IDATAX[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut\Core.IDATAX[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut\Core.IDATAX[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut\Core.IDATAX[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$130144$lut\Core.IDATAX[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130343.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130179.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130259.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130263.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130321.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130309.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130327.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130333.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130333.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130363.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130379.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$130144$lut$aiger130143$13706.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130408.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$130419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Removed 0 unused cells and 14333 unused wires.

12.45. Executing AUTONAME pass.
Renamed 594638 objects in module processorci_top (312 iterations).
<suppressed ~18798 debug messages>

12.46. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `processorci_top'. Setting top module to processorci_top.

12.46.1. Analyzing design hierarchy..
Top module:  \processorci_top

12.46.2. Analyzing design hierarchy..
Top module:  \processorci_top
Removed 0 unused modules.

12.47. Printing statistics.

=== processorci_top ===

   Number of wires:               8768
   Number of wire bits:          22697
   Number of public wires:        8768
   Number of public wire bits:   22697
   Number of ports:                 10
   Number of port bits:             10
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              11298
     $scopeinfo                     12
     CCU2C                         300
     L6MUX21                       565
     LUT4                         6911
     PFUMX                        1622
     TRELLIS_DPR16X4              1044
     TRELLIS_FF                    844

12.48. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Found and reported 0 problems.

12.49. Executing JSON backend.

Warnings: 3 unique messages, 3 total
End of script. Logfile hash: b2c620821c, CPU: user 42.48s system 0.29s, MEM: 296.57 MB peak
Time spent: 30% 1x abc9_exe (13 sec), 16% 1x autoname (6 sec), ...
/eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \
	--lpf /eda/processor_ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \
	--speed 6 --lpf-allow-unconstrained  --ignore-loops
/eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config  --bit colorlight_i9.bit

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] dir
Running in /var/jenkins_home/workspace/darkriscv/darkriscv
[Pipeline] {
[Pipeline] echo
Flashing FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p darkriscv -b colorlight_i9 -l
Final configuration file generated at /var/jenkins_home/workspace/darkriscv/darkriscv/build_colorlight_i9.tcl
Makefile executed successfully.
Makefile output:
/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 (null)
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE

Loading: [====                                              ] 7.52%
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Loading: [============                                      ] 23.14%
Loading: [===============                                   ] 29.80%
Loading: [===================                               ] 37.32%
Loading: [=======================                           ] 45.13%
Loading: [===========================                       ] 52.65%
Loading: [===============================                   ] 60.18%
Loading: [==================================                ] 67.70%
Loading: [======================================            ] 75.51%
Loading: [==========================================        ] 83.03%
Loading: [==============================================    ] 90.55%
Loading: [==================================================] 98.36%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
[Pipeline] echo
Testing FPGA colorlight_i9.
[Pipeline] dir
Running in /var/jenkins_home/workspace/darkriscv/darkriscv
[Pipeline] {
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyACM0
Test for FPGA in /dev/ttyACM0
[Pipeline] sh
+ python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0
Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'}
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Final configuration file generated at /var/jenkins_home/workspace/darkriscv/darkriscv/build_digilent_arty_a7_100t.tcl
Makefile executed successfully.
Makefile output:
Building the Design...
/eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/darkriscv/darkriscv/build_digilent_arty_a7_100t.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096"

****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source /var/jenkins_home/workspace/darkriscv/darkriscv/build_digilent_arty_a7_100t.tcl
# read_verilog /var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v
read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1277.145 ; gain = 24.836 ; free physical = 2918 ; free virtual = 24591
# read_verilog /eda/processor_ci/rtl/darkriscv.v
# read_verilog /eda/processor-ci-controller/modules/uart.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
# read_verilog /eda/processor-ci-controller/src/fifo.v
# read_verilog /eda/processor-ci-controller/src/reset.v
# read_verilog /eda/processor-ci-controller/src/clk_divider.v
# read_verilog /eda/processor-ci-controller/src/memory.v
# read_verilog /eda/processor-ci-controller/src/interpreter.v
# read_verilog /eda/processor-ci-controller/src/controller.v
# set ID [lindex $argv 0]
# set CLOCK_FREQ [lindex $argv 1]
# set MEMORY_SIZE [lindex $argv 2]
# set HIGH_CLK 1
# read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
# set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
# synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE \
#     -verilog_define $HIGH_CLK
Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096 -verilog_define 1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 3712833
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2031.805 ; gain = 402.715 ; free physical = 1690 ; free virtual = 23373
---------------------------------------------------------------------------------
INFO: [Synth 8-11241] undeclared symbol 'reset_o', assumed default net type 'wire' [/eda/processor_ci/rtl/darkriscv.v:55]
WARNING: [Synth 8-8895] 'reset_o' is already implicitly declared on line 55 [/eda/processor_ci/rtl/darkriscv.v:154]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16]
WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15]
WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16]
WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17]
WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84]
WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85]
INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/darkriscv.v:1]
INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
	Parameter BUFFER_SIZE bound to: 8 - type: integer 
	Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer 
	Parameter BUS_WIDTH bound to: 32 - type: integer 
	Parameter WORD_SIZE_BY bound to: 4 - type: integer 
	Parameter ID bound to: 0 - type: integer 
	Parameter RESET_CLK_CYCLES bound to: 20 - type: integer 
	Parameter MEMORY_FILE bound to: (null) - type: string 
	Parameter MEMORY_SIZE bound to: 4096 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1]
	Parameter COUNTER_BITS bound to: 32 - type: integer 
	Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1]
INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer 
	Parameter BUS_WIDTH bound to: 32 - type: integer 
	Parameter ID bound to: 0 - type: integer 
	Parameter RESET_CLK_CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
	Parameter BUFFER_SIZE bound to: 8 - type: integer 
	Parameter WORD_SIZE_BY bound to: 4 - type: integer 
INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213]
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1]
	Parameter DEPTH bound to: 8 - type: integer 
	Parameter WIDTH bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 50000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 50000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1]
	Parameter MEMORY_FILE bound to: (null) - type: string 
	Parameter MEMORY_SIZE bound to: 4096 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1]
WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1]
INFO: [Synth 8-6157] synthesizing module 'darkriscv' [/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:57]
	Parameter CPTR bound to: 0 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'darkriscv' (0#1) [/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:57]
WARNING: [Synth 8-7071] port 'DEBUG' of module 'darkriscv' is unconnected for instance 'Core' [/eda/processor_ci/rtl/darkriscv.v:95]
WARNING: [Synth 8-7023] instance 'Core' of module 'darkriscv' has 15 connections declared, but only 14 given [/eda/processor_ci/rtl/darkriscv.v:95]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1]
	Parameter CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/darkriscv.v:158]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/darkriscv.v:158]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/darkriscv.v:158]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/darkriscv.v:1]
WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25]
WARNING: [Synth 8-6014] Unused sequential element XCUS_reg was removed.  [/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:144]
WARNING: [Synth 8-6014] Unused sequential element XSYS_reg was removed.  [/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:146]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/darkriscv.v:21]
WARNING: [Synth 8-7129] Port BERR in module darkriscv is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2120.773 ; gain = 491.684 ; free physical = 1575 ; free virtual = 23260
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2138.586 ; gain = 509.496 ; free physical = 1571 ; free virtual = 23256
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2138.586 ; gain = 509.496 ; free physical = 1571 ; free virtual = 23256
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2138.586 ; gain = 0.000 ; free physical = 1579 ; free virtual = 23264
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2294.336 ; gain = 0.000 ; free physical = 1559 ; free virtual = 23244
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2294.371 ; gain = 0.000 ; free physical = 1556 ; free virtual = 23241
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1550 ; free virtual = 23235
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1550 ; free virtual = 23235
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1550 ; free virtual = 23235
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_RECV |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_SEND |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              000 |                             0000
                    READ |                              001 |                             0001
        COPY_READ_BUFFER |                              010 |                             0100
                      WB |                              011 |                             0010
                  FINISH |                              100 |                             0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              000 |                             0000
       COPY_WRITE_BUFFER |                              001 |                             0100
                   WRITE |                              010 |                             0001
                      WB |                              011 |                             0010
                  FINISH |                              100 |                             0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  iSTATE |                             0001 |                               00
                 iSTATE0 |                             0010 |                               01
                 iSTATE1 |                             0100 |                               10
                 iSTATE2 |                             1000 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
           RESET_COUNTER |                               00 |                               01
                    IDLE |                               01 |                               10
                    INIT |                               10 |                               00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1548 ; free virtual = 23234
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input   64 Bit       Adders := 2     
	   2 Input   32 Bit       Adders := 9     
	   3 Input   32 Bit       Adders := 1     
	   2 Input   24 Bit       Adders := 2     
	   2 Input   10 Bit       Adders := 2     
	   2 Input    8 Bit       Adders := 1     
	   2 Input    6 Bit       Adders := 4     
	   2 Input    5 Bit       Adders := 1     
	   2 Input    4 Bit       Adders := 2     
	   2 Input    3 Bit       Adders := 2     
	   2 Input    2 Bit       Adders := 1     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
	   2 Input      1 Bit         XORs := 1     
+---Registers : 
	               64 Bit    Registers := 2     
	               32 Bit    Registers := 20    
	               24 Bit    Registers := 5     
	               10 Bit    Registers := 2     
	                8 Bit    Registers := 11    
	                6 Bit    Registers := 1     
	                4 Bit    Registers := 4     
	                3 Bit    Registers := 2     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 39    
+---RAMs : 
	              32K Bit	(1024 X 32 bit)          RAMs := 2     
	              512 Bit	(16 X 32 bit)          RAMs := 1     
	               64 Bit	(8 X 8 bit)          RAMs := 2     
+---Muxes : 
	   4 Input   64 Bit        Muxes := 1     
	   2 Input   64 Bit        Muxes := 1     
	  48 Input   64 Bit        Muxes := 2     
	   2 Input   32 Bit        Muxes := 23    
	   5 Input   32 Bit        Muxes := 1     
	   4 Input   32 Bit        Muxes := 2     
	  48 Input   24 Bit        Muxes := 1     
	  48 Input    8 Bit        Muxes := 2     
	   2 Input    8 Bit        Muxes := 4     
	  24 Input    7 Bit        Muxes := 1     
	   2 Input    7 Bit        Muxes := 2     
	   2 Input    6 Bit        Muxes := 4     
	   3 Input    6 Bit        Muxes := 1     
	   2 Input    5 Bit        Muxes := 2     
	   2 Input    4 Bit        Muxes := 4     
	   5 Input    3 Bit        Muxes := 4     
	   2 Input    3 Bit        Muxes := 3     
	   2 Input    2 Bit        Muxes := 19    
	  48 Input    2 Bit        Muxes := 1     
	   4 Input    2 Bit        Muxes := 6     
	   3 Input    2 Bit        Muxes := 2     
	   2 Input    1 Bit        Muxes := 52    
	  48 Input    1 Bit        Muxes := 22    
	   3 Input    1 Bit        Muxes := 5     
	   4 Input    1 Bit        Muxes := 3     
	   5 Input    1 Bit        Muxes := 11    
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-3936] Found unconnected internal register 'XIDATA_reg' and it is trimmed from '32' to '31' bits. [/var/jenkins_home/workspace/darkriscv/darkriscv/rtl/darkriscv.v:131]
WARNING: [Synth 8-7129] Port BERR in module darkriscv is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module Memory is either unconnected or has no load
WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load
WARNING: [Synth 8-7129] Port intr in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port sck in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port cs in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port mosi in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port miso in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port rw in module Controller is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module processorci_top is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:07 ; elapsed = 00:01:08 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1375 ; free virtual = 23068
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object          | Depth x Width | Implemented As | 
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1         | LUT            | 
|Interpreter | memory_mux_selector | 256x1         | LUT            | 
+------------+---------------------+---------------+----------------+


Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object              | Inference | Size (Depth x Width) | Primitives       | 
+------------+-------------------------+-----------+----------------------+------------------+
|Controller  | Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|Controller  | Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|Controller  | Memory/memory_reg       | Implied   | 1 K x 32             | RAM256X1S x 128  | 
|Controller  | Data_Memory/memory_reg  | Implied   | 1 K x 32             | RAM256X1S x 128  | 
|Core        | REGS_reg                | Implied   | 16 x 32              | RAM32M x 16      | 
+------------+-------------------------+-----------+----------------------+------------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1382 ; free virtual = 23074
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:44 ; elapsed = 00:01:46 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1374 ; free virtual = 23066
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping Report
+------------+-------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object              | Inference | Size (Depth x Width) | Primitives       | 
+------------+-------------------------+-----------+----------------------+------------------+
|Controller  | Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|Controller  | Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|Controller  | Memory/memory_reg       | Implied   | 1 K x 32             | RAM256X1S x 128  | 
|Controller  | Data_Memory/memory_reg  | Implied   | 1 K x 32             | RAM256X1S x 128  | 
|Core        | REGS_reg                | Implied   | 16 x 32              | RAM32M x 16      | 
+------------+-------------------------+-----------+----------------------+------------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:49 ; elapsed = 00:01:50 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1375 ; free virtual = 23068
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:59 ; elapsed = 00:02:01 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1374 ; free virtual = 23067
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:59 ; elapsed = 00:02:01 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1374 ; free virtual = 23067
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:00 ; elapsed = 00:02:02 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1371 ; free virtual = 23064
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:02:00 ; elapsed = 00:02:02 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1369 ; free virtual = 23062
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:02:01 ; elapsed = 00:02:02 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1370 ; free virtual = 23062
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:02:01 ; elapsed = 00:02:03 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1368 ; free virtual = 23061
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+----------+------+
|      |Cell      |Count |
+------+----------+------+
|1     |BUFG      |     2|
|2     |CARRY4    |   127|
|3     |LUT1      |    35|
|4     |LUT2      |   317|
|5     |LUT3      |   410|
|6     |LUT4      |   232|
|7     |LUT5      |   288|
|8     |LUT6      |   820|
|9     |MUXF7     |     5|
|10    |RAM256X1S |   256|
|11    |RAM32M    |    18|
|12    |RAM32X1D  |     4|
|13    |FDRE      |   823|
|14    |FDSE      |    24|
|15    |IBUF      |     2|
|16    |OBUF      |     1|
|17    |OBUFT     |     2|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:02:01 ; elapsed = 00:02:03 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1367 ; free virtual = 23060
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 35 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:56 ; elapsed = 00:01:58 . Memory (MB): peak = 2294.371 ; gain = 509.496 ; free physical = 1371 ; free virtual = 23063
Synthesis Optimization Complete : Time (s): cpu = 00:02:01 ; elapsed = 00:02:03 . Memory (MB): peak = 2294.371 ; gain = 665.281 ; free physical = 1370 ; free virtual = 23063
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2294.371 ; gain = 0.000 ; free physical = 1618 ; free virtual = 23310
INFO: [Netlist 29-17] Analyzing 410 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2358.367 ; gain = 0.000 ; free physical = 1629 ; free virtual = 23322
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 278 instances were transformed.
  RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 18 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances

Synth Design complete | Checksum: 275ff437
INFO: [Common 17-83] Releasing license: Synthesis
51 Infos, 91 Warnings, 2 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:02:20 ; elapsed = 00:02:16 . Memory (MB): peak = 2358.402 ; gain = 1081.258 ; free physical = 1634 ; free virtual = 23327
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2051.389; main = 1781.178; forked = 411.095
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3217.941; main = 2358.371; forked = 955.617
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2422.398 ; gain = 63.996 ; free physical = 1631 ; free virtual = 23324

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 13ee6e85e

Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2526.211 ; gain = 103.812 ; free physical = 1592 ; free virtual = 23285

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 13ee6e85e

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2770.148 ; gain = 0.000 ; free physical = 1340 ; free virtual = 23033

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 13ee6e85e

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2770.148 ; gain = 0.000 ; free physical = 1340 ; free virtual = 23033
Phase 1 Initialization | Checksum: 13ee6e85e

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2770.148 ; gain = 0.000 ; free physical = 1340 ; free virtual = 23033

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 13ee6e85e

Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2770.148 ; gain = 0.000 ; free physical = 1339 ; free virtual = 23032

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 13ee6e85e

Time (s): cpu = 00:00:00.96 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2770.148 ; gain = 0.000 ; free physical = 1338 ; free virtual = 23030
Phase 2 Timer Update And Timing Data Collection | Checksum: 13ee6e85e

Time (s): cpu = 00:00:00.96 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2770.148 ; gain = 0.000 ; free physical = 1337 ; free virtual = 23030

Phase 3 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 13ee6e85e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.75 . Memory (MB): peak = 2770.148 ; gain = 0.000 ; free physical = 1337 ; free virtual = 23029
Retarget | Checksum: 13ee6e85e
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 1be2d89eb

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.87 . Memory (MB): peak = 2770.148 ; gain = 0.000 ; free physical = 1340 ; free virtual = 23032
Constant propagation | Checksum: 1be2d89eb
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
Phase 5 Sweep | Checksum: 212ff8b5d

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2770.148 ; gain = 0.000 ; free physical = 1341 ; free virtual = 23033
Sweep | Checksum: 212ff8b5d
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 212ff8b5d

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2802.164 ; gain = 32.016 ; free physical = 1337 ; free virtual = 23029
BUFG optimization | Checksum: 212ff8b5d
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 212ff8b5d

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2802.164 ; gain = 32.016 ; free physical = 1336 ; free virtual = 23028
Shift Register Optimization | Checksum: 212ff8b5d
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 212ff8b5d

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2802.164 ; gain = 32.016 ; free physical = 1333 ; free virtual = 23026
Post Processing Netlist | Checksum: 212ff8b5d
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 157e814ae

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2802.164 ; gain = 32.016 ; free physical = 1332 ; free virtual = 23025

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2802.164 ; gain = 0.000 ; free physical = 1340 ; free virtual = 23032
Phase 9.2 Verifying Netlist Connectivity | Checksum: 157e814ae

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2802.164 ; gain = 32.016 ; free physical = 1340 ; free virtual = 23032
Phase 9 Finalization | Checksum: 157e814ae

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2802.164 ; gain = 32.016 ; free physical = 1340 ; free virtual = 23032
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               0  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 157e814ae

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2802.164 ; gain = 32.016 ; free physical = 1340 ; free virtual = 23032
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.164 ; gain = 0.000 ; free physical = 1339 ; free virtual = 23031

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 157e814ae

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2802.164 ; gain = 0.000 ; free physical = 1331 ; free virtual = 23023

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 157e814ae

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.164 ; gain = 0.000 ; free physical = 1330 ; free virtual = 23023

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.164 ; gain = 0.000 ; free physical = 1330 ; free virtual = 23023
Ending Netlist Obfuscation Task | Checksum: 157e814ae

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.164 ; gain = 0.000 ; free physical = 1330 ; free virtual = 23022
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 2802.164 ; gain = 443.762 ; free physical = 1330 ; free virtual = 23022
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2834.180 ; gain = 0.000 ; free physical = 1341 ; free virtual = 23034
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14393337e

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2834.180 ; gain = 0.000 ; free physical = 1341 ; free virtual = 23034
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.180 ; gain = 0.000 ; free physical = 1341 ; free virtual = 23034

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 927cb20f

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2834.180 ; gain = 0.000 ; free physical = 1339 ; free virtual = 23032

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 13c025578

Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.207 ; gain = 7.027 ; free physical = 1330 ; free virtual = 23023

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 13c025578

Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.207 ; gain = 7.027 ; free physical = 1328 ; free virtual = 23021
Phase 1 Placer Initialization | Checksum: 13c025578

Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.207 ; gain = 7.027 ; free physical = 1326 ; free virtual = 23019

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 18ea1bfa6

Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.207 ; gain = 7.027 ; free physical = 1338 ; free virtual = 23030

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 155dd8d82

Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 2841.207 ; gain = 7.027 ; free physical = 1333 ; free virtual = 23026

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 155dd8d82

Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 2841.207 ; gain = 7.027 ; free physical = 1317 ; free virtual = 23009

Phase 2.4 Global Placement Core

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 10e6eb9e7

Time (s): cpu = 00:00:36 ; elapsed = 00:00:22 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1308 ; free virtual = 23000

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 1 LUTNM shape to break, 121 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 1, total 1, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 57 nets or LUTs. Breaked 1 LUT, combined 56 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2857.215 ; gain = 0.000 ; free physical = 1309 ; free virtual = 23002

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            1  |             56  |                    57  |           0  |           1  |  00:00:01  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            1  |             56  |                    57  |           0  |           9  |  00:00:01  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 12c3c03b0

Time (s): cpu = 00:00:40 ; elapsed = 00:00:25 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1307 ; free virtual = 22999
Phase 2.4 Global Placement Core | Checksum: 1cd370949

Time (s): cpu = 00:01:11 ; elapsed = 00:00:41 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1305 ; free virtual = 22997
Phase 2 Global Placement | Checksum: 1cd370949

Time (s): cpu = 00:01:11 ; elapsed = 00:00:41 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1305 ; free virtual = 22997

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 12b2bcefd

Time (s): cpu = 00:01:14 ; elapsed = 00:00:43 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1305 ; free virtual = 22998

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 160d8554e

Time (s): cpu = 00:01:19 ; elapsed = 00:00:46 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1303 ; free virtual = 22996

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 200039411

Time (s): cpu = 00:01:19 ; elapsed = 00:00:47 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1303 ; free virtual = 22996

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 15ea902b0

Time (s): cpu = 00:01:19 ; elapsed = 00:00:47 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1303 ; free virtual = 22996

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 1676245cc

Time (s): cpu = 00:01:34 ; elapsed = 00:00:59 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1285 ; free virtual = 22978

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 230e98975

Time (s): cpu = 00:01:36 ; elapsed = 00:01:01 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1304 ; free virtual = 22996

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 194188f2c

Time (s): cpu = 00:01:37 ; elapsed = 00:01:02 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1304 ; free virtual = 22996

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 12a6ce499

Time (s): cpu = 00:01:37 ; elapsed = 00:01:02 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1304 ; free virtual = 22996

Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 1a887dcb3

Time (s): cpu = 00:01:59 ; elapsed = 00:01:21 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1303 ; free virtual = 22996
Phase 3 Detail Placement | Checksum: 1a887dcb3

Time (s): cpu = 00:01:59 ; elapsed = 00:01:21 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1303 ; free virtual = 22996

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1cd6b125b

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.156 | TNS=-16.051 |
Phase 1 Physical Synthesis Initialization | Checksum: 139aa07ac

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2857.215 ; gain = 0.000 ; free physical = 1292 ; free virtual = 22984
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 139aa07ac

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2857.215 ; gain = 0.000 ; free physical = 1302 ; free virtual = 22995
Phase 4.1.1.1 BUFG Insertion | Checksum: 1cd6b125b

Time (s): cpu = 00:02:07 ; elapsed = 00:01:26 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1297 ; free virtual = 22990

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.789. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1700cfe05

Time (s): cpu = 00:03:13 ; elapsed = 00:02:28 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1255 ; free virtual = 22997

Time (s): cpu = 00:03:13 ; elapsed = 00:02:28 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1254 ; free virtual = 22997
Phase 4.1 Post Commit Optimization | Checksum: 1700cfe05

Time (s): cpu = 00:03:13 ; elapsed = 00:02:28 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1250 ; free virtual = 22992

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1700cfe05

Time (s): cpu = 00:03:13 ; elapsed = 00:02:28 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1245 ; free virtual = 22987

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                2x2|
|___________|___________________|___________________|
|      South|                1x1|                2x2|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 1700cfe05

Time (s): cpu = 00:03:14 ; elapsed = 00:02:28 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1240 ; free virtual = 22982
Phase 4.3 Placer Reporting | Checksum: 1700cfe05

Time (s): cpu = 00:03:14 ; elapsed = 00:02:29 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1256 ; free virtual = 22998

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2857.215 ; gain = 0.000 ; free physical = 1256 ; free virtual = 22998

Time (s): cpu = 00:03:14 ; elapsed = 00:02:29 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1256 ; free virtual = 22998
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15ae22301

Time (s): cpu = 00:03:14 ; elapsed = 00:02:29 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1256 ; free virtual = 22998
Ending Placer Task | Checksum: b476537b

Time (s): cpu = 00:03:14 ; elapsed = 00:02:29 . Memory (MB): peak = 2857.215 ; gain = 23.035 ; free physical = 1256 ; free virtual = 22998
37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:03:16 ; elapsed = 00:02:30 . Memory (MB): peak = 2857.215 ; gain = 55.051 ; free physical = 1256 ; free virtual = 22998
# report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
# report_utilization -file digilent_arty_a7_utilization_place.rpt
# report_io -file digilent_arty_a7_io.rpt
report_io: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2857.215 ; gain = 0.000 ; free physical = 1256 ; free virtual = 22998
# report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2857.215 ; gain = 0.000 ; free physical = 1256 ; free virtual = 22998
# report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: 626ff93 ConstDB: 0 ShapeSum: ae4f53e8 RouteDB: 0
Post Restoration Checksum: NetGraph: 7ed647ad | NumContArr: efbf21f6 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2f3e75edd

Time (s): cpu = 00:01:26 ; elapsed = 00:01:15 . Memory (MB): peak = 2857.215 ; gain = 0.000 ; free physical = 1640 ; free virtual = 23434

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2f3e75edd

Time (s): cpu = 00:01:26 ; elapsed = 00:01:15 . Memory (MB): peak = 2857.215 ; gain = 0.000 ; free physical = 1650 ; free virtual = 23444

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2f3e75edd

Time (s): cpu = 00:01:26 ; elapsed = 00:01:15 . Memory (MB): peak = 2857.215 ; gain = 0.000 ; free physical = 1650 ; free virtual = 23444
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2c1562e08

Time (s): cpu = 00:01:37 ; elapsed = 00:01:20 . Memory (MB): peak = 2857.215 ; gain = 0.000 ; free physical = 1611 ; free virtual = 23405
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.060  | TNS=0.000  | WHS=-0.917 | THS=-79.961|


Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0130565 %
  Global Horizontal Routing Utilization  = 0.00518613 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 2759
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 2723
  Number of Partially Routed Nets     = 36
  Number of Node Overlaps             = 30

Phase 2 Router Initialization | Checksum: 358c028e3

Time (s): cpu = 00:01:41 ; elapsed = 00:01:22 . Memory (MB): peak = 2857.215 ; gain = 0.000 ; free physical = 1611 ; free virtual = 23405

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 358c028e3

Time (s): cpu = 00:01:41 ; elapsed = 00:01:22 . Memory (MB): peak = 2857.215 ; gain = 0.000 ; free physical = 1610 ; free virtual = 23404

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 1d97ae062

Time (s): cpu = 00:02:24 ; elapsed = 00:01:38 . Memory (MB): peak = 2957.191 ; gain = 99.977 ; free physical = 1459 ; free virtual = 23253
Phase 3 Initial Routing | Checksum: 1d97ae062

Time (s): cpu = 00:02:24 ; elapsed = 00:01:38 . Memory (MB): peak = 2957.191 ; gain = 99.977 ; free physical = 1459 ; free virtual = 23253
INFO: [Route 35-580] Design has 115 pins with tight setup and hold constraints.

The top 5 pins with tight setup and hold constraints:

+====================+===================+======================+
| Launch Setup Clock | Launch Hold Clock | Pin                  |
+====================+===================+======================+
| sys_clk_pin        | sys_clk_pin       | Core/XSCC_reg/D      |
| sys_clk_pin        | sys_clk_pin       | Core/XUIMM_reg[29]/D |
| sys_clk_pin        | sys_clk_pin       | Core/XSIMM_reg[20]/D |
| sys_clk_pin        | sys_clk_pin       | Core/XSIMM_reg[11]/D |
| sys_clk_pin        | sys_clk_pin       | Core/XSIMM_reg[29]/D |
+--------------------+-------------------+----------------------+

File with complete list of pins: tight_setup_hold_pins.txt


Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 820
 Number of Nodes with overlaps = 151
 Number of Nodes with overlaps = 30
 Number of Nodes with overlaps = 13
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.719 | TNS=-164.767| WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 3036cdba4

Time (s): cpu = 00:03:30 ; elapsed = 00:02:19 . Memory (MB): peak = 2957.191 ; gain = 99.977 ; free physical = 1475 ; free virtual = 23270

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 192
 Number of Nodes with overlaps = 12
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.989 | TNS=-68.814| WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 28f54ee29

Time (s): cpu = 00:04:35 ; elapsed = 00:03:17 . Memory (MB): peak = 2957.191 ; gain = 99.977 ; free physical = 1462 ; free virtual = 23257

Phase 4.3 Global Iteration 2
 Number of Nodes with overlaps = 179
 Number of Nodes with overlaps = 83
 Number of Nodes with overlaps = 17
 Number of Nodes with overlaps = 12
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.850 | TNS=-59.812| WHS=N/A    | THS=N/A    |

Phase 4.3 Global Iteration 2 | Checksum: 1f90bc6f5

Time (s): cpu = 00:06:04 ; elapsed = 00:04:23 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1432 ; free virtual = 23227

Phase 4.4 Global Iteration 3
 Number of Nodes with overlaps = 226
 Number of Nodes with overlaps = 28
 Number of Nodes with overlaps = 16
 Number of Nodes with overlaps = 14
 Number of Nodes with overlaps = 9
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.850 | TNS=-52.540| WHS=N/A    | THS=N/A    |

Phase 4.4 Global Iteration 3 | Checksum: 256b76734

Time (s): cpu = 00:06:25 ; elapsed = 00:04:41 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1433 ; free virtual = 23228
Phase 4 Rip-up And Reroute | Checksum: 256b76734

Time (s): cpu = 00:06:25 ; elapsed = 00:04:41 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1433 ; free virtual = 23228

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 20c4221e4

Time (s): cpu = 00:06:27 ; elapsed = 00:04:42 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1432 ; free virtual = 23227
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.770 | TNS=-44.003| WHS=N/A    | THS=N/A    |

 Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 1e685075f

Time (s): cpu = 00:06:29 ; elapsed = 00:04:43 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1417 ; free virtual = 23212

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1e685075f

Time (s): cpu = 00:06:29 ; elapsed = 00:04:43 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1416 ; free virtual = 23211
Phase 5 Delay and Skew Optimization | Checksum: 1e685075f

Time (s): cpu = 00:06:29 ; elapsed = 00:04:43 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1416 ; free virtual = 23211

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1ecf7cdaa

Time (s): cpu = 00:06:32 ; elapsed = 00:04:45 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1425 ; free virtual = 23220
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.683 | TNS=-42.362| WHS=0.059  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 1ecf7cdaa

Time (s): cpu = 00:06:32 ; elapsed = 00:04:45 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1425 ; free virtual = 23220
Phase 6 Post Hold Fix | Checksum: 1ecf7cdaa

Time (s): cpu = 00:06:32 ; elapsed = 00:04:45 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1425 ; free virtual = 23220

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 1.2583 %
  Global Horizontal Routing Utilization  = 1.28865 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0


--GLOBAL Congestion:
Utilization threshold used for congestion level computation: 0.85
Congestion Report
North Dir 1x1 Area, Max Cong = 64.8649%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 65.7658%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 73.5294%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 76.4706%, No Congested Regions.

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0

Phase 7 Route finalize | Checksum: 1ecf7cdaa

Time (s): cpu = 00:06:32 ; elapsed = 00:04:45 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1425 ; free virtual = 23220

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1ecf7cdaa

Time (s): cpu = 00:06:32 ; elapsed = 00:04:45 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1425 ; free virtual = 23220

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1d3cd3aa3

Time (s): cpu = 00:06:33 ; elapsed = 00:04:46 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1426 ; free virtual = 23221

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.683 | TNS=-42.362| WHS=0.059  | THS=0.000  |

WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 1d3cd3aa3

Time (s): cpu = 00:06:35 ; elapsed = 00:04:47 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1420 ; free virtual = 23215
INFO: [Route 35-16] Router Completed Successfully

Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 1895203db

Time (s): cpu = 00:06:36 ; elapsed = 00:04:47 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1420 ; free virtual = 23215
Ending Routing Task | Checksum: 1895203db

Time (s): cpu = 00:06:36 ; elapsed = 00:04:47 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1418 ; free virtual = 23213

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
16 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:06:39 ; elapsed = 00:04:50 . Memory (MB): peak = 3019.191 ; gain = 161.977 ; free physical = 1419 ; free virtual = 23214
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (1)
------------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (1)
-------------------------------
 There is 1 port with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
     -0.690      -42.098                    148                12968        0.060        0.000                      0                12968        3.750        0.000                       0                  2025  


Timing constraints are not met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock        Waveform(ns)         Period(ns)      Frequency(MHz)
-----        ------------         ----------      --------------
sck          {0.000 50.000}       100.000         10.000          
sys_clk_pin  {0.000 5.000}        10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
sys_clk_pin        -0.690      -42.098                    148                12968        0.060        0.000                      0                12968        3.750        0.000                       0                  2025  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


# report_route_status -file digilent_arty_a7_route_status.rpt
# report_drc -file digilent_arty_a7_drc.rpt
Command: report_drc -file digilent_arty_a7_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/darkriscv/darkriscv/digilent_arty_a7_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_arty_a7_power.rpt
Command: report_power -file digilent_arty_a7_power.rpt
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "digilent_arty_a7_100t.bit"
Command: write_bitstream -force digilent_arty_a7_100t.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_arty_a7_100t.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 3160.230 ; gain = 93.016 ; free physical = 1295 ; free virtual = 23094
# exit
INFO: [Common 17-206] Exiting Vivado at Sun Apr  6 00:17:13 2025...

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
[Pipeline] dir
Running in /var/jenkins_home/workspace/darkriscv/darkriscv
[Pipeline] {
[Pipeline] echo
Flashing FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p darkriscv -b digilent_arty_a7_100t -l
Final configuration file generated at /var/jenkins_home/workspace/darkriscv/darkriscv/build_digilent_arty_a7_100t.tcl
Makefile executed successfully.
Makefile output:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit
empty
Jtag frequency : requested 10.00MHz   -> real 10.00MHz  
Open file DONE
Parse file DONE
load program

Load SRAM: [===============                                   ] 30.00%
Load SRAM: [===============================                   ] 62.00%
Load SRAM: [===============================================   ] 94.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
[Pipeline] echo
Testing FPGA digilent_arty_a7_100t.
[Pipeline] dir
Running in /var/jenkins_home/workspace/darkriscv/darkriscv
[Pipeline] {
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyUSB1
Test for FPGA in /dev/ttyUSB1
[Pipeline] sh
+ python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1
Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'}
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: e4a3996b-fae1-4a34-961d-f8f4c3c81e90
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: No test report files were found. Configuration error?
Finished: FAILURE