Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Tue May  6 00:07:21 2025
| Host         : 89852011558b running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : processorci_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |    59 |
|    Minimum number of control sets                        |    59 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |    89 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |    59 |
| >= 0 to < 4        |     2 |
| >= 4 to < 6        |     6 |
| >= 6 to < 8        |     4 |
| >= 8 to < 10       |     8 |
| >= 10 to < 12      |     6 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     0 |
| >= 16              |    30 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              87 |           40 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |             150 |           75 |
| Yes          | No                    | No                     |             163 |           60 |
| Yes          | No                    | Yes                    |              32 |            8 |
| Yes          | Yes                   | No                     |             407 |           95 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+----------------+----------------------------------------------------------------+---------------------------------------------------------+------------------+----------------+--------------+
|  Clock Signal  |                          Enable Signal                         |                     Set/Reset Signal                    | Slice Load Count | Bel Load Count | Bels / Slice |
+----------------+----------------------------------------------------------------+---------------------------------------------------------+------------------+----------------+--------------+
|  clk_IBUF_BUFG |                                                                |                                                         |                1 |              1 |         1.00 |
|  clk_o_BUFG    | u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  clk_o_BUFG    | u_Controller/Uart/i_uart_tx/E[0]                               |                                                         |                1 |              4 |         4.00 |
|  clk_o_BUFG    | u_Controller/Uart/i_uart_rx/next_bit                           | u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1__0_n_0   |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ResetBootSystem/counter                                        |                                                         |                1 |              4 |         4.00 |
|  clk_o_BUFG    | u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0          | u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/return_state                          | ResetBootSystem/rst_o_reg_0                             |                2 |              5 |         2.50 |
|  clk_core_BUFG |                                                                | u_Controller/Core_Memory/XRES_reg_8                     |                3 |              5 |         1.67 |
|  clk_o_BUFG    |                                                                |                                                         |                4 |              6 |         1.50 |
|  clk_core_BUFG |                                                                | u_Controller/Core_Memory/XRES_reg_7                     |                3 |              6 |         2.00 |
|  clk_core_BUFG |                                                                | u_Controller/Core_Memory/XRES_reg_0                     |                3 |              7 |         2.33 |
|  clk_o_BUFG    | u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                             |                2 |              7 |         3.50 |
|  clk_core_BUFG |                                                                | u_Controller/Core_Memory/XRES_reg_19                    |                5 |              8 |         1.60 |
|  clk_o_BUFG    | u_Controller/Uart/uart_tx_en                                   | ResetBootSystem/rst_o_reg_0                             |                2 |              8 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/accumulator[7]_i_1_n_0                | ResetBootSystem/rst_o_reg_0                             |                1 |              8 |         8.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/counter                               | ResetBootSystem/rst_o_reg_0                             |                4 |              8 |         2.00 |
|  clk_o_BUFG    | u_Controller/Uart/i_uart_rx/E[0]                               | ResetBootSystem/rst_o_reg_0                             |                2 |              8 |         4.00 |
|  clk_o_BUFG    | u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                             |                2 |              8 |         4.00 |
|  clk_o_BUFG    | u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0] | ResetBootSystem/rst_o_reg_0                             |                1 |              8 |         8.00 |
|  clk_o_BUFG    | u_Controller/Uart/i_uart_rx/recieved_data0                     | u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                1 |              8 |         8.00 |
|  clk_o_BUFG    | u_Controller/Uart/i_uart_rx/cycle_counter0                     | u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0 |                3 |             10 |         3.33 |
|  clk_o_BUFG    | u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ResetBootSystem/SR[0]                                   |                3 |             10 |         3.33 |
|  clk_core_BUFG |                                                                | u_Controller/Core_Memory/XRES_reg_18                    |                5 |             11 |         2.20 |
|  clk_o_BUFG    | u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                  | ResetBootSystem/rst_o_reg_0                             |                3 |             11 |         3.67 |
|  clk_core_BUFG |                                                                | u_Controller/Core_Memory/XRES_reg                       |                6 |             11 |         1.83 |
|  clk_o_BUFG    | u_Controller/Uart/rx_fifo/read_ptr0                            | ResetBootSystem/rst_o_reg_0                             |                3 |             11 |         3.67 |
|  clk_o_BUFG    | u_Controller/Interpreter/address[31]_i_1_n_0                   |                                                         |                6 |             12 |         2.00 |
|  clk_o_BUFG    | u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0        |                                                         |                2 |             12 |         6.00 |
|  clk_o_BUFG    | u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0           |                                                         |                2 |             12 |         6.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0    |                                                         |               10 |             24 |         2.40 |
|  clk_o_BUFG    | u_Controller/Interpreter/memory_page_number[23]_i_2_n_0        | u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                7 |             24 |         3.43 |
|  clk_o_BUFG    | u_Controller/Interpreter/timeout                               | ResetBootSystem/rst_o_reg_0                             |                7 |             24 |         3.43 |
|  clk_o_BUFG    | u_Controller/Interpreter/accumulator0                          | ResetBootSystem/rst_o_reg_0                             |                4 |             24 |         6.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/num_of_pages                          | ResetBootSystem/rst_o_reg_0                             |                5 |             24 |         4.80 |
|  clk_o_BUFG    | u_Controller/Interpreter/end_position[31]_i_1_n_0              | ResetBootSystem/rst_o_reg_0                             |                7 |             32 |         4.57 |
|  clk_o_BUFG    | u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0               | ResetBootSystem/rst_o_reg_0                             |                8 |             32 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/timeout_counter                       | ResetBootSystem/rst_o_reg_0                             |                5 |             32 |         6.40 |
|  clk_o_BUFG    | u_Controller/Interpreter/communication_buffer[31]_i_1_n_0      | ResetBootSystem/rst_o_reg_0                             |                8 |             32 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/read_buffer                           | ResetBootSystem/rst_o_reg_0                             |               11 |             32 |         2.91 |
|  clk_o_BUFG    | u_Controller/Uart/tx_fifo/E[0]                                 | ResetBootSystem/rst_o_reg_0                             |                5 |             32 |         6.40 |
|  clk_o_BUFG    | u_Controller/Uart/rx_fifo/E[0]                                 | ResetBootSystem/rst_o_reg_0                             |                4 |             32 |         8.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/write_data[31]_i_1_n_0                |                                                         |               14 |             32 |         2.29 |
|  clk_o_BUFG    | u_Controller/Interpreter/communication_write_data[31]_i_1_n_0  |                                                         |               13 |             32 |         2.46 |
|  clk_core_BUFG |                                                                | Core/XRES_reg_0                                         |               25 |             49 |         1.96 |
|  clk_o_BUFG    |                                                                | ResetBootSystem/rst_o_reg_0                             |               25 |             53 |         2.12 |
|  clk_o_BUFG    | u_Controller/Interpreter/num_of_positions[23]_i_1_n_0          |                                                         |               15 |             55 |         3.67 |
|  clk_o_BUFG    | u_Controller/Interpreter/memory_mux_selector_reg_3             |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/NXPC2_reg[12]_2                       |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/NXPC2_reg[12]_3                       |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/address_reg[10]_0                     |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/address_reg[11]_0                     |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/NXPC2_reg[12]_4                       |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/NXPC2_reg[12]_6                       |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/NXPC2_reg[12]_5                       |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/NXPC2_reg[12]_1                       |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/NXPC2_reg[12]_0                       |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/NXPC2_reg[12]                         |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG    | u_Controller/Interpreter/memory_mux_selector_reg_4             |                                                         |               32 |            128 |         4.00 |
|  clk_core_BUFG |                                                                |                                                         |               51 |            208 |         4.08 |
+----------------+----------------------------------------------------------------+---------------------------------------------------------+------------------+----------------+--------------+


