Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
<span class="pipeline-node-3">Running on Jenkins in /var/lib/jenkins/workspace/cv32e40p
</span>[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
<span class="pipeline-node-7">+ rm -rf cv32e40p
</span>[Pipeline] sh
<span class="pipeline-node-8">+ git clone --recursive <a href='https://github.com/openhwgroup/cv32e40p'>https://github.com/openhwgroup/cv32e40p</a> cv32e40p
Cloning into 'cv32e40p'...
</span>[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
<span class="pipeline-node-13">Running in /var/lib/jenkins/workspace/cv32e40p/cv32e40p
</span>[Pipeline] {
[Pipeline] sh
<span class="pipeline-node-15">+ iverilog -o simulation.out -g2005-sv -s -I rtl/include/ rtl/cv32e40p_aligner.sv rtl/cv32e40p_alu.sv rtl/cv32e40p_alu_div.sv rtl/cv32e40p_apu_disp.sv rtl/cv32e40p_compressed_decoder.sv rtl/cv32e40p_controller.sv rtl/cv32e40p_core.sv rtl/cv32e40p_cs_registers.sv rtl/cv32e40p_decoder.sv rtl/cv32e40p_ex_stage.sv rtl/cv32e40p_ff_one.sv rtl/cv32e40p_fifo.sv rtl/cv32e40p_fp_wrapper.sv rtl/cv32e40p_hwloop_regs.sv rtl/cv32e40p_id_stage.sv rtl/cv32e40p_if_stage.sv rtl/cv32e40p_int_controller.sv rtl/cv32e40p_load_store_unit.sv rtl/cv32e40p_mult.sv rtl/cv32e40p_obi_interface.sv rtl/cv32e40p_popcnt.sv rtl/cv32e40p_prefetch_buffer.sv rtl/cv32e40p_prefetch_controller.sv rtl/cv32e40p_register_file_ff.sv rtl/cv32e40p_register_file_latch.sv rtl/cv32e40p_sleep_unit.sv rtl/cv32e40p_top.sv
rtl/cv32e40p_alu.sv:29: syntax error
I give up.
</span>[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
<span class="pipeline-node-67">Failed in branch colorlight_i9
</span>[Pipeline] }
<span class="pipeline-node-68">Failed in branch digilent_nexys4_ddr
</span>[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
<span class="pipeline-node-74">Running in /var/lib/jenkins/workspace/cv32e40p/cv32e40p
</span>[Pipeline] {
[Pipeline] sh
<span class="pipeline-node-76">+ rm -rf Bender.yml CITATION.cff CONTRIBUTING.md LICENSE README.md bhv ci constraints cv32e40p_fpu_manifest.flist cv32e40p_manifest.flist docs example_tb python-requirements.txt rtl scripts src_files.yml sva util
</span>[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 2
Finished: FAILURE