Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/Toooba
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf *.xml
[Pipeline] sh
+ rm -rf Toooba
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/bluespec/Toooba Toooba
Cloning into 'Toooba'...
Submodule 'src_Core/BSV_Additional_Libs/BlueStuff' (https://github.com/CTSRD-CHERI/BlueStuff.git) registered for path 'src_Core/BSV_Additional_Libs/BlueStuff'
Cloning into '/var/jenkins_home/workspace/Toooba/Toooba/src_Core/BSV_Additional_Libs/BlueStuff'...
Submodule path 'src_Core/BSV_Additional_Libs/BlueStuff': checked out '7e3686c5dc361a7125e859cf60c609596a1a9b83'
Submodule 'BlueBasics' (https://github.com/CTSRD-CHERI/BlueBasics.git) registered for path 'src_Core/BSV_Additional_Libs/BlueStuff/BlueBasics'
Submodule 'SocketPacketUtils' (https://github.com/CTSRD-CHERI/SocketPacketUtils.git) registered for path 'src_Core/BSV_Additional_Libs/BlueStuff/SocketPacketUtils'
Cloning into '/var/jenkins_home/workspace/Toooba/Toooba/src_Core/BSV_Additional_Libs/BlueStuff/BlueBasics'...
Cloning into '/var/jenkins_home/workspace/Toooba/Toooba/src_Core/BSV_Additional_Libs/BlueStuff/SocketPacketUtils'...
Submodule path 'src_Core/BSV_Additional_Libs/BlueStuff/BlueBasics': checked out '9be88c5c0a7cd9c24a04ea85dda54c58b471ac3c'
Submodule path 'src_Core/BSV_Additional_Libs/BlueStuff/SocketPacketUtils': checked out 'e7df4dd0f3ef6cbb0275e880e7c8ec88c91a8fde'
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Toooba/Toooba
[Pipeline] {
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAXI4_Deburster_A.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAluDispToRegFifo.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAluExeToFinFifo.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAluRegToExeFifo.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkBht.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkBoot_ROM.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDCRqMshrWrapper.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDPRqMshrWrapper.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDPipeline.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDTlbSynth.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDirPredictor.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDivExecQ.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDoubleDiv.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDoubleFMA.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDoubleSqrt.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDummyStoreBuffer.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkEpochManager.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_AXI4.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFmaExecQ.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivDispToRegFifo.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivRegToExeFifo.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkGSelectGHistReg.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkGSelectPred.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkGShareGHistReg.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkGSharePred.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkIBankWrapper.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkICRqMshrWrapper.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkICoCache.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkIPRqMshrWrapper.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkIPipeline.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkITlb.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkL2Tlb.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkLLCache.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkLLPipeline.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkLSQIssueLdQ.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkLastLvCRqMshr.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMMIOInst.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMemDispToRegFifo.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMemRegToExeFifo.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMem_Controller.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMem_Model.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMinimumExecQ.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMulExecQ.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkNullTransCache.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkPLIC_16_2_7.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkRFileSynth.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkRas.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkRegRenamingTable.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkReorderBufferSynth.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationAlu.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationFpuMulDiv.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationMem.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkRobRowSynth.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkScoreboardAggr.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkScoreboardCons.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSimpleRespQ.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Map.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSpecTagManager.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSplitLSQ.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSplitTransCache.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkStoreBufferEhr.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSyncBramFifo_w36_d512.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSyncFifo_w32_d16.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTourGHistReg.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTourPred.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTourPredSecure.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkUART.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpDiv.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpDivIP.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpDivSim.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpFma.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpFmaIP.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpFmaSim.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpSqrt.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpSqrtIP.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpSqrtSim.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_alu.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_aluBr.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_amoExec.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_basicExec.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_brAddrCalc.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_checkForException.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_decode.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_decodeBrPred.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_execFpuSimple.v builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_getControlFlow.v builds/Resources/Verilator_resources/import_DPI_C_decls.v src_Core/BSV_Additional_Libs/BlueStuff/BlueUtils/MemBRAM_Altera.v src_Core/BSV_Additional_Libs/BlueStuff/BlueUtils/MemSim.v src_Core/RISCY_OOO/fpgautils/xilinx/fpu/fp_div_sim.v src_Core/RISCY_OOO/fpgautils/xilinx/fpu/fp_fma_sim.v src_Core/RISCY_OOO/fpgautils/xilinx/fpu/fp_sqrt_sim.v src_Core/RISCY_OOO/fpgautils/xilinx/reset_regs/reset_guard.v src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v src_SSITH_P3/Verilog_RTL/mkBht.v src_SSITH_P3/Verilog_RTL/mkCore.v src_SSITH_P3/Verilog_RTL/mkCoreW.v src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v src_SSITH_P3/Verilog_RTL/mkDM_CSR_Tap.v src_SSITH_P3/Verilog_RTL/mkDM_GPR_Tap.v src_SSITH_P3/Verilog_RTL/mkDM_Mem_Tap.v src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v src_SSITH_P3/Verilog_RTL/mkDPipeline.v src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v src_SSITH_P3/Verilog_RTL/mkDebug_Module.v src_SSITH_P3/Verilog_RTL/mkDirPredictor.v src_SSITH_P3/Verilog_RTL/mkDivExecQ.v src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v src_SSITH_P3/Verilog_RTL/mkEpochManager.v src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v src_SSITH_P3/Verilog_RTL/mkFetchStage.v src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v src_SSITH_P3/Verilog_RTL/mkGSelectPred.v src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v src_SSITH_P3/Verilog_RTL/mkGSharePred.v src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v src_SSITH_P3/Verilog_RTL/mkICoCache.v src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v src_SSITH_P3/Verilog_RTL/mkIPipeline.v src_SSITH_P3/Verilog_RTL/mkITlb.v src_SSITH_P3/Verilog_RTL/mkJtagTap.v src_SSITH_P3/Verilog_RTL/mkL2Tlb.v src_SSITH_P3/Verilog_RTL/mkLLCache.v src_SSITH_P3/Verilog_RTL/mkLLPipeline.v src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v src_SSITH_P3/Verilog_RTL/mkMMIOInst.v src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v src_SSITH_P3/Verilog_RTL/mkMemLoader.v src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v src_SSITH_P3/Verilog_RTL/mkMulExecQ.v src_SSITH_P3/Verilog_RTL/mkNullTransCache.v src_SSITH_P3/Verilog_RTL/mkP3_Core.v src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v src_SSITH_P3/Verilog_RTL/mkProc.v src_SSITH_P3/Verilog_RTL/mkRFileSynth.v src_SSITH_P3/Verilog_RTL/mkRas.v src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v src_SSITH_P3/Verilog_RTL/mkSoC_Map.v src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v src_SSITH_P3/Verilog_RTL/mkTV_Encode.v src_SSITH_P3/Verilog_RTL/mkTV_Xactor.v src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v src_SSITH_P3/Verilog_RTL/mkTourPred.v src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v src_SSITH_P3/Verilog_RTL/mkTrace_Data2_to_Trace_Data.v src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v src_SSITH_P3/Verilog_RTL/module_alu.v src_SSITH_P3/Verilog_RTL/module_aluBr.v src_SSITH_P3/Verilog_RTL/module_amoExec.v src_SSITH_P3/Verilog_RTL/module_basicExec.v src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v src_SSITH_P3/Verilog_RTL/module_checkForException.v src_SSITH_P3/Verilog_RTL/module_decode.v src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v src_SSITH_P3/Verilog_RTL/module_getControlFlow.v src_SSITH_P3/xilinx_ip/hdl/ASSIGN1.v src_SSITH_P3/xilinx_ip/hdl/BRAM2.v src_SSITH_P3/xilinx_ip/hdl/Counter.v src_SSITH_P3/xilinx_ip/hdl/FIFO1.v src_SSITH_P3/xilinx_ip/hdl/FIFO10.v src_SSITH_P3/xilinx_ip/hdl/FIFO2.v src_SSITH_P3/xilinx_ip/hdl/FIFO20.v src_SSITH_P3/xilinx_ip/hdl/FIFOL1.v src_SSITH_P3/xilinx_ip/hdl/MakeClock.v src_SSITH_P3/xilinx_ip/hdl/MakeReset0.v src_SSITH_P3/xilinx_ip/hdl/MakeResetA.v src_SSITH_P3/xilinx_ip/hdl/RegFile.v src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v src_SSITH_P3/xilinx_ip/hdl/ResetEither.v src_SSITH_P3/xilinx_ip/hdl/RevertReg.v src_SSITH_P3/xilinx_ip/hdl/SizedFIFO.v src_SSITH_P3/xilinx_ip/hdl/SizedFIFO0.v src_SSITH_P3/xilinx_ip/hdl/SyncFIFOLevel.v src_SSITH_P3/xilinx_ip/hdl/SyncHandshake.v src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v src_SSITH_P3/xilinx_ip/hdl/SyncResetA.v src_SSITH_P3/xilinx_ip/hdl/SyncWire.v src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v src_SSITH_P3/xilinx_ip/hdl/mkBht.v src_SSITH_P3/xilinx_ip/hdl/mkCore.v src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v src_SSITH_P3/xilinx_ip/hdl/mkDM_CSR_Tap.v src_SSITH_P3/xilinx_ip/hdl/mkDM_GPR_Tap.v src_SSITH_P3/xilinx_ip/hdl/mkDM_Mem_Tap.v src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v src_SSITH_P3/xilinx_ip/hdl/mkITlb.v src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v src_SSITH_P3/xilinx_ip/hdl/mkProc.v src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v src_SSITH_P3/xilinx_ip/hdl/mkRas.v src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v src_SSITH_P3/xilinx_ip/hdl/mkTV_Encode.v src_SSITH_P3/xilinx_ip/hdl/mkTV_Xactor.v src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v src_SSITH_P3/xilinx_ip/hdl/mkTrace_Data2_to_Trace_Data.v src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v src_SSITH_P3/xilinx_ip/hdl/module_alu.v src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v src_SSITH_P3/xilinx_ip/hdl/module_decode.v src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v src_SSITH_P3/xilinx_ip/hdl/module_getControlFlow.v src_SSITH_P3/xilinx_ip/hdl/reset_guard.v src_bsc_lib_RTL/BRAM2.v src_bsc_lib_RTL/FIFO1.v src_bsc_lib_RTL/FIFO10.v src_bsc_lib_RTL/FIFO2.v src_bsc_lib_RTL/FIFO20.v src_bsc_lib_RTL/FIFOL1.v src_bsc_lib_RTL/MakeClock.v src_bsc_lib_RTL/MakeResetA.v src_bsc_lib_RTL/RegFile.v src_bsc_lib_RTL/RegFileLoad.v src_bsc_lib_RTL/ResetEither.v src_bsc_lib_RTL/RevertReg.v src_bsc_lib_RTL/SizedFIFO.v src_bsc_lib_RTL/SizedFIFO0.v src_bsc_lib_RTL/SyncFIFOLevel.v src_bsc_lib_RTL/SyncHandshake.v src_bsc_lib_RTL/SyncResetA.v src_bsc_lib_RTL/main.v src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v src_SSITH_P3/Verilog_RTL_sim/SyncWire.v src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v src_SSITH_P3/Verilog_RTL_sim/mkBht.v src_SSITH_P3/Verilog_RTL_sim/mkCore.v src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v src_SSITH_P3/Verilog_RTL_sim/mkDM_CSR_Tap.v src_SSITH_P3/Verilog_RTL_sim/mkDM_GPR_Tap.v src_SSITH_P3/Verilog_RTL_sim/mkDM_Mem_Tap.v src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v src_SSITH_P3/Verilog_RTL_sim/mkFabric_2x3.v src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v src_SSITH_P3/Verilog_RTL_sim/mkITlb.v src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v src_SSITH_P3/Verilog_RTL_sim/mkProc.v src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v src_SSITH_P3/Verilog_RTL_sim/mkRas.v src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v src_SSITH_P3/Verilog_RTL_sim/mkSyncBramFifo_w36_d512.v src_SSITH_P3/Verilog_RTL_sim/mkSyncFifo_w32_d16.v src_SSITH_P3/Verilog_RTL_sim/mkTV_Encode.v src_SSITH_P3/Verilog_RTL_sim/mkTV_Xactor.v src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v src_SSITH_P3/Verilog_RTL_sim/mkTrace_Data2_to_Trace_Data.v src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDiv.v src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivIP.v src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivSim.v src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFma.v src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaIP.v src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaSim.v src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrt.v src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtIP.v src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtSim.v src_SSITH_P3/Verilog_RTL_sim/module_alu.v src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v src_SSITH_P3/Verilog_RTL_sim/module_decode.v src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v src_SSITH_P3/Verilog_RTL_sim/module_getControlFlow.v
builds/Resources/Verilator_resources/import_DPI_C_decls.v:13: syntax error
I give up.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
Stage "Utilities" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
Stage "digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
Stage "digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 2
Finished: FAILURE