Started by timer [Pipeline] Start of Pipeline [Pipeline] node Still waiting to schedule task Waiting for next available executor Running on Jenkins in /var/jenkins_home/workspace/T13x [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf *.xml [Pipeline] sh + rm -rf T13x [Pipeline] sh + git clone --recursive --depth=1 https://github.com/klessydra/T13x T13x Cloning into 'T13x'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/T13x/T13x [Pipeline] { [Pipeline] sh + /eda/oss-cad-suite/bin/ghdl -a --std=08 klessydra-t1-3th/PKG_RiscV_Klessydra.vhd klessydra-t1-3th/RTL-Accumulator.vhd klessydra-t1-3th/RTL-Debug_Unit.vhd klessydra-t1-3th/RTL-CSR_Unit.vhd klessydra-t1-3th/RTL-DSP_Unit.vhd klessydra-t1-3th/RTL-ID_STAGE.vhd klessydra-t1-3th/RTL-IE_STAGE.vhd klessydra-t1-3th/RTL-IF_STAGE.vhd klessydra-t1-3th/RTL-Load_Store_Unit.vhd klessydra-t1-3th/RTL-Processing_Pipeline.vhd klessydra-t1-3th/RTL-Program_Counter_unit.vhd klessydra-t1-3th/RTL-Registerfile.vhd klessydra-t1-3th/STR-Klessydra_top.vhd klessydra-t1-3th/RTL-Scratchpad_Memory.vhd klessydra-t1-3th/RTL-Scratchpad_Memory_Interface.vhd klessydra-t1-3th/RTL-Program_Counter_unit.vhd:109:12:warning: declaration of "MTVEC" hides port "MTVEC" [-Whide] signal MTVEC : in std_logic_vector(31 downto 0); ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:110:12:warning: declaration of "instr_gnt_i" hides port "instr_gnt_i" [-Whide] signal instr_gnt_i, taken_branch : in std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:110:25:warning: declaration of "taken_branch" hides port "taken_branch" [-Whide] signal instr_gnt_i, taken_branch : in std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:111:12:warning: declaration of "set_wfi_condition" hides port "set_wfi_condition" [-Whide] signal set_wfi_condition : in std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:112:12:warning: declaration of "taken_branch_pending" hides port "taken_branch_pending" [-Whide] signal taken_branch_pending : inout std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:113:12:warning: declaration of "irq_pending" hides port "irq_pending" [-Whide] signal irq_pending : in std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:114:12:warning: declaration of "ie_except_condition" hides port "ie_except_condition" [-Whide] signal ie_except_condition : in std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:115:12:warning: declaration of "ls_except_condition" hides port "ls_except_condition" [-Whide] signal ls_except_condition : in std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:116:12:warning: declaration of "dsp_except_condition" hides port "dsp_except_condition" [-Whide] signal dsp_except_condition : in std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:117:12:warning: declaration of "set_except_condition" hides port "set_except_condition" [-Whide] signal set_except_condition : in std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:118:12:warning: declaration of "set_mret_condition" hides port "set_mret_condition" [-Whide] signal set_mret_condition : in std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:119:12:warning: declaration of "pc" hides signal "pc" [-Whide] signal pc : inout std_logic_vector(31 downto 0); ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:120:12:warning: declaration of "taken_branch_pc_lat" hides port "taken_branch_pc_lat" [-Whide] signal taken_branch_pc_lat : in std_logic_vector(31 downto 0); ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:122:12:warning: declaration of "incremented_pc" hides port "incremented_pc" [-Whide] signal incremented_pc : in std_logic_vector(31 downto 0); ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:123:12:warning: declaration of "boot_pc" hides signal "boot_pc" [-Whide] signal boot_pc : in std_logic_vector(31 downto 0); ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:124:12:warning: declaration of "pc_update_enable" hides signal "pc_update_enable" [-Whide] signal pc_update_enable : in std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:125:12:warning: declaration of "served_ie_except_condition" hides port "served_ie_except_condition" [-Whide] signal served_ie_except_condition : out std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:126:12:warning: declaration of "served_ls_except_condition" hides port "served_ls_except_condition" [-Whide] signal served_ls_except_condition : out std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:127:12:warning: declaration of "served_dsp_except_condition" hides port "served_dsp_except_condition" [-Whide] signal served_dsp_except_condition : out std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:128:12:warning: declaration of "served_except_condition" hides port "served_except_condition" [-Whide] signal served_except_condition : out std_logic; ^ klessydra-t1-3th/RTL-Program_Counter_unit.vhd:129:12:warning: declaration of "served_mret_condition" hides port "served_mret_condition" [-Whide] signal served_mret_condition : out std_logic) is ^ klessydra-t1-3th/RTL-Registerfile.vhd:85:26:error: no "RS1_Data_IE" for attribute specification attribute ram_style of RS1_Data_IE : signal is "reg"; ^ klessydra-t1-3th/RTL-Registerfile.vhd:86:26:error: no "RS2_Data_IE" for attribute specification attribute ram_style of RS2_Data_IE : signal is "reg"; ^ klessydra-t1-3th/RTL-Registerfile.vhd:87:26:error: no "RD_Data_IE" for attribute specification attribute ram_style of RD_Data_IE : signal is "reg"; ^ klessydra-t1-3th/RTL-Registerfile.vhd:265:3:warning: declaration of "RF_FF" hides if generate statement [-Whide] RF_FF : if LUTRAM_RF = 0 generate ^ klessydra-t1-3th/RTL-Registerfile.vhd:288:3:warning: declaration of "RF_LUTRAM" hides if generate statement [-Whide] RF_LUTRAM : if LUTRAM_RF = 1 generate ^ /eda/oss-cad-suite/libexec/ghdl:error: compilation error [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) Stage "Utilities" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) Stage "FPGA Build Pipeline" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] parallel [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) Stage "digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] stage [Pipeline] { (Synthesis and PnR) Stage "digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) Stage "digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) Stage "digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch digilent_arty_a7_100t [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 389e2d03-556d-4098-84b3-356ddfcddc70 hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE