Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/T13x
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf T13x
[Pipeline] sh
+ git clone --recursive https://github.com/klessydra/T13x T13x
Cloning into 'T13x'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/T13x/T13x
[Pipeline] {
[Pipeline] sh
+ ghdl -a --std=08 klessydra-t1-3th/PKG_RiscV_Klessydra.vhd klessydra-t1-3th/RTL-Accumulator.vhd klessydra-t1-3th/RTL-Debug_Unit.vhd klessydra-t1-3th/RTL-CSR_Unit.vhd klessydra-t1-3th/RTL-DSP_Unit.vhd klessydra-t1-3th/RTL-ID_STAGE.vhd klessydra-t1-3th/RTL-IE_STAGE.vhd klessydra-t1-3th/RTL-IF_STAGE.vhd klessydra-t1-3th/RTL-Load_Store_Unit.vhd klessydra-t1-3th/RTL-Processing_Pipeline.vhd klessydra-t1-3th/RTL-Program_Counter_unit.vhd klessydra-t1-3th/RTL-Registerfile.vhd klessydra-t1-3th/STR-Klessydra_top.vhd klessydra-t1-3th/RTL-Scratchpad_Memory.vhd klessydra-t1-3th/RTL-Scratchpad_Memory_Interface.vhd
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:109:12:warning: declaration of "mtvec" hides port "mtvec" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:110:12:warning: declaration of "instr_gnt_i" hides port "instr_gnt_i" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:110:25:warning: declaration of "taken_branch" hides port "taken_branch" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:111:12:warning: declaration of "set_wfi_condition" hides port "set_wfi_condition" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:112:12:warning: declaration of "taken_branch_pending" hides port "taken_branch_pending" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:113:12:warning: declaration of "irq_pending" hides port "irq_pending" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:114:12:warning: declaration of "ie_except_condition" hides port "ie_except_condition" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:115:12:warning: declaration of "ls_except_condition" hides port "ls_except_condition" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:116:12:warning: declaration of "dsp_except_condition" hides port "dsp_except_condition" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:117:12:warning: declaration of "set_except_condition" hides port "set_except_condition" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:118:12:warning: declaration of "set_mret_condition" hides port "set_mret_condition" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:119:12:warning: declaration of "pc" hides signal "pc" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:120:12:warning: declaration of "taken_branch_pc_lat" hides port "taken_branch_pc_lat" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:122:12:warning: declaration of "incremented_pc" hides port "incremented_pc" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:123:12:warning: declaration of "boot_pc" hides signal "boot_pc" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:124:12:warning: declaration of "pc_update_enable" hides signal "pc_update_enable" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:125:12:warning: declaration of "served_ie_except_condition" hides port "served_ie_except_condition" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:126:12:warning: declaration of "served_ls_except_condition" hides port "served_ls_except_condition" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:127:12:warning: declaration of "served_dsp_except_condition" hides port "served_dsp_except_condition" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:128:12:warning: declaration of "served_except_condition" hides port "served_except_condition" [-Whide]
klessydra-t1-3th/RTL-Program_Counter_unit.vhd:129:12:warning: declaration of "served_mret_condition" hides port "served_mret_condition" [-Whide]
klessydra-t1-3th/RTL-Registerfile.vhd:85:26: no "rs1_data_ie" for attribute specification
klessydra-t1-3th/RTL-Registerfile.vhd:86:26: no "rs2_data_ie" for attribute specification
klessydra-t1-3th/RTL-Registerfile.vhd:87:26: no "rd_data_ie" for attribute specification
klessydra-t1-3th/RTL-Registerfile.vhd:265:3:warning: declaration of "rf_ff" hides if generate statement [-Whide]
klessydra-t1-3th/RTL-Registerfile.vhd:288:3:warning: declaration of "rf_lutram" hides if generate statement [-Whide]
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/T13x/T13x
[Pipeline] {
[Pipeline] sh
+ rm -rf README.md klessydra-t1-3th pics src_files.yml
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE