Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Tue May 13 22:44:12 2025
| Host         : 89852011558b running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : processorci_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |   179 |
|    Minimum number of control sets                        |   179 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   161 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |   179 |
| >= 0 to < 4        |     4 |
| >= 4 to < 6        |    10 |
| >= 6 to < 8        |     6 |
| >= 8 to < 10       |     7 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     0 |
| >= 16              |   145 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |             409 |          154 |
| No           | No                    | Yes                    |              52 |           31 |
| No           | Yes                   | No                     |             120 |           66 |
| Yes          | No                    | No                     |             454 |          199 |
| Yes          | No                    | Yes                    |            3291 |         1913 |
| Yes          | Yes                   | No                     |             433 |          130 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+-----------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------+----------------+--------------+
|                                    Clock Signal                                   |                                       Enable Signal                                      |                               Set/Reset Signal                              | Slice Load Count | Bel Load Count | Bels / Slice |
+-----------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------+----------------+--------------+
|  clk_IBUF_BUFG                                                                    |                                                                                          |                                                                             |                1 |              1 |         1.00 |
|  u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].trap_hndlr_reg0                |                                                                                          | u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].trap_hndlr_reg[0]_i_2_n_0 |                1 |              1 |         1.00 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                              | u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0                                 |                1 |              1 |         1.00 |
|  u_klessydra_t0_2th_core/CSR/CSR_updating_logic[1].trap_hndlr_reg0                |                                                                                          | u_klessydra_t0_2th_core/CSR/trap_hndlr                                      |                1 |              1 |         1.00 |
|  clk_core_BUFG                                                                    |                                                                                          |                                                                             |                3 |              4 |         1.33 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/i_uart_tx/E[0]                                                         |                                                                             |                1 |              4 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0                                    | u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1_n_0                          |                1 |              4 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/i_uart_rx/next_bit                                                     | u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1__0_n_0                       |                1 |              4 |         4.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/served_except_condition6_out                                | u_Controller/Interpreter/rst_core                                           |                2 |              4 |         2.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE0                                     | u_klessydra_t0_2th_core/Pipe/i___10_n_0                                     |                3 |              4 |         1.33 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE0                                     | u_klessydra_t0_2th_core/Pipe/i___9_n_0                                      |                2 |              4 |         2.00 |
|  clk_o_BUFG                                                                       | ResetBootSystem/counter                                                                  |                                                                             |                2 |              4 |         2.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE0                                     | u_klessydra_t0_2th_core/Pipe/i___8_n_0                                      |                3 |              5 |         1.67 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/return_state                                                    | ResetBootSystem/rst_o_reg_0                                                 |                3 |              5 |         1.67 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/CSR/i___17_n_0                                                   | u_Controller/Interpreter/rst_core                                           |                2 |              6 |         3.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/CSR/i___27_n_0                                                   | u_Controller/Interpreter/rst_core                                           |                3 |              6 |         2.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE0                                     | u_klessydra_t0_2th_core/Pipe/i___7_n_0                                      |                4 |              6 |         1.50 |
|  clk_o_BUFG                                                                       |                                                                                          |                                                                             |                3 |              6 |         2.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE0                                     | u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE[8]_i_1_n_0              |                4 |              7 |         1.75 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0                                      | ResetBootSystem/rst_o_reg_0                                                 |                3 |              7 |         2.33 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/uart_tx_en                                                             | ResetBootSystem/rst_o_reg_0                                                 |                1 |              8 |         8.00 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/i_uart_rx/recieved_data0                                               | u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0                        |                1 |              8 |         8.00 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0                                      | ResetBootSystem/rst_o_reg_0                                                 |                1 |              8 |         8.00 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/i_uart_rx/E[0]                                                         | ResetBootSystem/rst_o_reg_0                                                 |                1 |              8 |         8.00 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0]                           | ResetBootSystem/rst_o_reg_0                                                 |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/counter                                                         | ResetBootSystem/rst_o_reg_0                                                 |                3 |              8 |         2.67 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/accumulator[7]_i_1_n_0                                          | ResetBootSystem/rst_o_reg_0                                                 |                3 |              8 |         2.67 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/i_uart_rx/cycle_counter0                                               | u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0                     |                3 |             10 |         3.33 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                              | ResetBootSystem/SR[0]                                                       |                3 |             10 |         3.33 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                                            | ResetBootSystem/rst_o_reg_0                                                 |                4 |             11 |         2.75 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/rx_fifo/read_ptr0                                                      | ResetBootSystem/rst_o_reg_0                                                 |                4 |             11 |         2.75 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/address[31]_i_1_n_0                                             |                                                                             |                8 |             12 |         1.50 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0                                     |                                                                             |                2 |             12 |         6.00 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0                                  |                                                                             |                2 |             12 |         6.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/memory_page_number[23]_i_2_n_0                                  | u_Controller/Interpreter/memory_page_number[23]_i_1_n_0                     |                7 |             24 |         3.43 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0                              |                                                                             |                8 |             24 |         3.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/accumulator0                                                    | ResetBootSystem/rst_o_reg_0                                                 |                6 |             24 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/num_of_pages                                                    | ResetBootSystem/rst_o_reg_0                                                 |                6 |             24 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/timeout                                                         | ResetBootSystem/rst_o_reg_0                                                 |                8 |             24 |         3.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Prg_Ctr/pc_update_logic[0].served_mret_condition_reg[0]_0        | u_Controller/Interpreter/rst_core                                           |               16 |             26 |         1.62 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]_5    | u_Controller/Interpreter/rst_core                                           |               16 |             26 |         1.62 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/CSR/CSR_updating_logic[0].MCAUSE_internal[0][30]_i_1_n_0         | u_Controller/Interpreter/rst_core                                           |               12 |             28 |         2.33 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/E[0]                                                        | u_Controller/Interpreter/rst_core                                           |               13 |             28 |         2.15 |
|  u_klessydra_t0_2th_core/Pipe/fsm_IE_comb.PC_offset_wires_reg[0][31]_i_1_n_0_BUFG |                                                                                          |                                                                             |               13 |             31 |         2.38 |
|  u_klessydra_t0_2th_core/Pipe/fsm_IE_comb.PC_offset_wires_reg[1][31]_i_2_n_0_BUFG |                                                                                          |                                                                             |               13 |             31 |         2.38 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/csr_addr_i[11]_i_1_n_0                                      | u_Controller/Interpreter/rst_core                                           |               11 |             31 |         2.82 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/flush_cycle_count[0][30]_i_1_n_0                            | u_Controller/Interpreter/rst_core                                           |                8 |             31 |         3.88 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/flush_cycle_count[1][30]_i_1_n_0                            | u_Controller/Interpreter/rst_core                                           |                9 |             31 |         3.44 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][9]_73                                       | u_Controller/Interpreter/rst_core                                           |               28 |             32 |         1.14 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][8]_48                                       | u_Controller/Interpreter/rst_core                                           |               23 |             32 |         1.39 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][0]_45                                       | u_Controller/Interpreter/rst_core                                           |               23 |             32 |         1.39 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]_1[0] | u_Controller/Interpreter/rst_core                                           |               12 |             32 |         2.67 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][24]_53                                      | u_Controller/Interpreter/rst_core                                           |               19 |             32 |         1.68 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][20]_47                                      | u_Controller/Interpreter/rst_core                                           |               24 |             32 |         1.33 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][4]_50                                       | u_Controller/Interpreter/rst_core                                           |               18 |             32 |         1.78 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]_4[0] | u_Controller/Interpreter/rst_core                                           |               13 |             32 |         2.46 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][21]_62                                      | u_Controller/Interpreter/rst_core                                           |               27 |             32 |         1.19 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][27]_57                                      | u_Controller/Interpreter/rst_core                                           |               28 |             32 |         1.14 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][25]_59                                      | u_Controller/Interpreter/rst_core                                           |               23 |             32 |         1.39 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][31][31]_i_1_n_0                             | u_Controller/Interpreter/rst_core                                           |               29 |             32 |         1.10 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][24]_46                                      | u_Controller/Interpreter/rst_core                                           |               25 |             32 |         1.28 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][4]_49                                       | u_Controller/Interpreter/rst_core                                           |               17 |             32 |         1.88 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][29]_55                                      | u_Controller/Interpreter/rst_core                                           |               28 |             32 |         1.14 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][23]_60                                      | u_Controller/Interpreter/rst_core                                           |               29 |             32 |         1.10 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/pc_update_logic[1].served_except_condition_reg[1][0]        | u_Controller/Interpreter/rst_core                                           |               19 |             32 |         1.68 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][20]_52                                      | u_Controller/Interpreter/rst_core                                           |               13 |             32 |         2.46 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[1].PCER_reg[1][8][0]                     | u_Controller/Interpreter/rst_core                                           |               11 |             32 |         2.91 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][26]_101                                     | u_Controller/Interpreter/rst_core                                           |               20 |             32 |         1.60 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/write_data[31]_i_1_n_0                                          |                                                                             |               17 |             32 |         1.88 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/communication_write_data[31]_i_1_n_0                            |                                                                             |               14 |             32 |         2.29 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/timeout_counter                                                 | ResetBootSystem/rst_o_reg_0                                                 |                7 |             32 |         4.57 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/read_buffer                                                     | ResetBootSystem/rst_o_reg_0                                                 |               18 |             32 |         1.78 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/communication_buffer[31]_i_1_n_0                                | ResetBootSystem/rst_o_reg_0                                                 |                9 |             32 |         3.56 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/end_position[31]_i_1_n_0                                        | ResetBootSystem/rst_o_reg_0                                                 |                9 |             32 |         3.56 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/tx_fifo/E[0]                                                           | ResetBootSystem/rst_o_reg_0                                                 |                4 |             32 |         8.00 |
|  clk_o_BUFG                                                                       | u_Controller/Uart/rx_fifo/E[0]                                                           | ResetBootSystem/rst_o_reg_0                                                 |                5 |             32 |         6.40 |
|  clk_o_BUFG                                                                       | u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0                                         | ResetBootSystem/rst_o_reg_0                                                 |                8 |             32 |         4.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][25]_100                                     | u_Controller/Interpreter/rst_core                                           |               21 |             32 |         1.52 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][23]_99                                      | u_Controller/Interpreter/rst_core                                           |               26 |             32 |         1.23 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][28]_56                                      | u_Controller/Interpreter/rst_core                                           |               27 |             32 |         1.19 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][28]_103                                     | u_Controller/Interpreter/rst_core                                           |               21 |             32 |         1.52 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][22]_98                                      | u_Controller/Interpreter/rst_core                                           |               23 |             32 |         1.39 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][29]_104                                     | u_Controller/Interpreter/rst_core                                           |               25 |             32 |         1.28 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][27]_102                                     | u_Controller/Interpreter/rst_core                                           |               20 |             32 |         1.60 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/csr_wdata_i[31]_i_1_n_0                                     | u_Controller/Interpreter/rst_core                                           |               22 |             32 |         1.45 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][0]_44                                       | u_Controller/Interpreter/rst_core                                           |               20 |             32 |         1.60 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][8]_51                                       | u_Controller/Interpreter/rst_core                                           |               22 |             32 |         1.45 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][26]_58                                      | u_Controller/Interpreter/rst_core                                           |               22 |             32 |         1.45 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][22]_61                                      | u_Controller/Interpreter/rst_core                                           |               30 |             32 |         1.07 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][30]_54                                      | u_Controller/Interpreter/rst_core                                           |               26 |             32 |         1.23 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][3]_77                                       | u_Controller/Interpreter/rst_core                                           |               20 |             32 |         1.60 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][5]_76                                       | u_Controller/Interpreter/rst_core                                           |               23 |             32 |         1.39 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][12]_89                                      | u_Controller/Interpreter/rst_core                                           |               19 |             32 |         1.68 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][16]_93                                      | u_Controller/Interpreter/rst_core                                           |               19 |             32 |         1.68 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][2]_81                                       | u_Controller/Interpreter/rst_core                                           |               19 |             32 |         1.68 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][14]_68                                      | u_Controller/Interpreter/rst_core                                           |               20 |             32 |         1.60 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][11]_88                                      | u_Controller/Interpreter/rst_core                                           |               22 |             32 |         1.45 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][13]_90                                      | u_Controller/Interpreter/rst_core                                           |               23 |             32 |         1.39 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[1].PCER_reg[1][2][0]                     | u_Controller/Interpreter/rst_core                                           |               13 |             32 |         2.46 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][18]_64                                      | u_Controller/Interpreter/rst_core                                           |               21 |             32 |         1.52 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][19]_63                                      | u_Controller/Interpreter/rst_core                                           |               22 |             32 |         1.45 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][13]_69                                      | u_Controller/Interpreter/rst_core                                           |               18 |             32 |         1.78 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][6]_75                                       | u_Controller/Interpreter/rst_core                                           |               25 |             32 |         1.28 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][1]_80                                       | u_Controller/Interpreter/rst_core                                           |               15 |             32 |         2.13 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][3]_82                                       | u_Controller/Interpreter/rst_core                                           |               18 |             32 |         1.78 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][17]_65                                      | u_Controller/Interpreter/rst_core                                           |               21 |             32 |         1.52 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][2]_78                                       | u_Controller/Interpreter/rst_core                                           |               27 |             32 |         1.19 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][7]_85                                       | u_Controller/Interpreter/rst_core                                           |               20 |             32 |         1.60 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/csr_addr_i_reg[1]_0[0]                                      | u_Controller/Interpreter/rst_core                                           |               15 |             32 |         2.13 |
|  Prg_Ctr/taken_branch_pc_lat_internal[0]_1                                        |                                                                                          |                                                                             |                9 |             32 |         3.56 |
|  Prg_Ctr/taken_branch_pc_lat_internal[1]_0                                        |                                                                                          |                                                                             |                9 |             32 |         3.56 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/CSR/i___18_n_0                                                   | u_Controller/Interpreter/rst_core                                           |                9 |             32 |         3.56 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/CSR/i___20_n_0                                                   | u_Controller/Interpreter/rst_core                                           |               15 |             32 |         2.13 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[0].PCER_reg[0][7][0]                     | u_Controller/Interpreter/rst_core                                           |               16 |             32 |         2.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/csr_addr_i_reg[4]_0[0]                                      | u_Controller/Interpreter/rst_core                                           |               14 |             32 |         2.29 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/csr_addr_i_reg[11]_3[0]                                     | u_Controller/Interpreter/rst_core                                           |               14 |             32 |         2.29 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/csr_addr_i_reg[11]_1[0]                                     | u_Controller/Interpreter/rst_core                                           |               14 |             32 |         2.29 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][15]_92                                      | u_Controller/Interpreter/rst_core                                           |               19 |             32 |         1.68 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/csr_addr_i_reg[11]_2[0]                                     | u_Controller/Interpreter/rst_core                                           |               12 |             32 |         2.67 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/csr_instr_req_reg_2[0]                                      | u_Controller/Interpreter/rst_core                                           |               15 |             32 |         2.13 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[0].PCER_reg[0][2][0]                     | u_Controller/Interpreter/rst_core                                           |               13 |             32 |         2.46 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/csr_addr_i_reg[2]_0[0]                                      | u_Controller/Interpreter/rst_core                                           |               11 |             32 |         2.91 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/instr_grant_reg[0]                                          | u_Controller/Interpreter/rst_core                                           |               11 |             32 |         2.91 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][10]_87                                      | u_Controller/Interpreter/rst_core                                           |               22 |             32 |         1.45 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][31][31]_i_1_n_0                             | u_Controller/Interpreter/rst_core                                           |               25 |             32 |         1.28 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/core_reset_reg_3[0]                                         |                                                                             |               13 |             32 |         2.46 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][18]_95                                      | u_Controller/Interpreter/rst_core                                           |               18 |             32 |         1.78 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][21]_97                                      | u_Controller/Interpreter/rst_core                                           |               20 |             32 |         1.60 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][17]_94                                      | u_Controller/Interpreter/rst_core                                           |               15 |             32 |         2.13 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][19]_96                                      | u_Controller/Interpreter/rst_core                                           |               23 |             32 |         1.39 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Prg_Ctr/pc_update_logic[1].pc[1][31]_i_1_n_0                     | u_Controller/Interpreter/rst_core                                           |               13 |             32 |         2.46 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Prg_Ctr/pc_update_logic[0].pc[0][31]_i_1_n_0                     | u_Controller/Interpreter/rst_core                                           |               11 |             32 |         2.91 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[1].PCER_reg[1][9][0]                     | u_Controller/Interpreter/rst_core                                           |               11 |             32 |         2.91 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[1].PCER_reg[1][7][0]                     | u_Controller/Interpreter/rst_core                                           |               14 |             32 |         2.29 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/pc_update_logic[0].served_except_condition_reg[0][0]        | u_Controller/Interpreter/rst_core                                           |               20 |             32 |         1.60 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/core_reset_reg_2[0]                                         |                                                                             |               12 |             32 |         2.67 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]_2[0] | u_Controller/Interpreter/rst_core                                           |               11 |             32 |         2.91 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[0].PCER_reg[0][8][0]                     | u_Controller/Interpreter/rst_core                                           |               12 |             32 |         2.67 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/csr_instr_req_reg_3[0]                                      | u_Controller/Interpreter/rst_core                                           |               12 |             32 |         2.67 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/instr_grant_reg_1[0]                                        | u_Controller/Interpreter/rst_core                                           |               13 |             32 |         2.46 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]_3[0] | u_Controller/Interpreter/rst_core                                           |               12 |             32 |         2.67 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/CSR_updating_logic[0].PCER_reg[0][9][0]                     | u_Controller/Interpreter/rst_core                                           |                9 |             32 |         3.56 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/pc_except_value_reg[0]0                                     |                                                                             |               11 |             32 |         2.91 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][5]_83                                       | u_Controller/Interpreter/rst_core                                           |               21 |             32 |         1.52 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][1]_79                                       | u_Controller/Interpreter/rst_core                                           |               28 |             32 |         1.14 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][9]_86                                       | u_Controller/Interpreter/rst_core                                           |               22 |             32 |         1.45 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][14]_91                                      | u_Controller/Interpreter/rst_core                                           |               16 |             32 |         2.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][6]_84                                       | u_Controller/Interpreter/rst_core                                           |               16 |             32 |         2.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][7]_74                                       | u_Controller/Interpreter/rst_core                                           |               29 |             32 |         1.10 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][16]_66                                      | u_Controller/Interpreter/rst_core                                           |               16 |             32 |         2.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][10]_72                                      | u_Controller/Interpreter/rst_core                                           |               23 |             32 |         1.39 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[0][30]_105                                     | u_Controller/Interpreter/rst_core                                           |               17 |             32 |         1.88 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/pc_except_value_reg[1]0                                     |                                                                             |                9 |             32 |         3.56 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][12]_70                                      | u_Controller/Interpreter/rst_core                                           |               20 |             32 |         1.60 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][11]_71                                      | u_Controller/Interpreter/rst_core                                           |               22 |             32 |         1.45 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/regfile_wire[1][15]_67                                      | u_Controller/Interpreter/rst_core                                           |               24 |             32 |         1.33 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/harc_IE_wire                                                | u_Controller/Interpreter/rst_core                                           |               11 |             33 |         3.00 |
|  clk_core_BUFG                                                                    | instr_grant_BUFG                                                                         | u_Controller/Interpreter/rst_core                                           |               10 |             33 |         3.30 |
|  instr_grant_BUFG                                                                 |                                                                                          |                                                                             |               22 |             36 |         1.64 |
|  harc_ID_lat_reg[0]_i_2_n_0                                                       |                                                                                          |                                                                             |               17 |             46 |         2.71 |
|  clk_core_BUFG                                                                    |                                                                                          | u_Controller/Interpreter/rst_core                                           |               31 |             52 |         1.68 |
|  clk_o_BUFG                                                                       |                                                                                          | ResetBootSystem/rst_o_reg_0                                                 |               22 |             54 |         2.45 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/num_of_positions[23]_i_1_n_0                                    |                                                                             |               17 |             55 |         3.24 |
|  clk_core_BUFG                                                                    |                                                                                          | u_Controller/Interpreter/memory_mux_selector_reg_rep_0                      |               42 |             64 |         1.52 |
|  harc_IE                                                                          |                                                                                          |                                                                             |               30 |             95 |         3.17 |
| ~harc_IE                                                                          |                                                                                          |                                                                             |               34 |             95 |         2.79 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/memory_mux_selector_reg_rep_9                                   |                                                                             |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/memory_mux_selector_reg_rep_10                                  |                                                                             |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/memory_mux_selector_reg_rep_11                                  |                                                                             |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/memory_mux_selector_reg_rep_12                                  |                                                                             |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/memory_mux_selector_reg_3                                       |                                                                             |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/address_reg[11]_0                                               |                                                                             |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/address_reg[10]_0                                               |                                                                             |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/memory_mux_selector_reg_4                                       |                                                                             |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/memory_mux_selector_reg_rep_8                                   |                                                                             |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/memory_mux_selector_reg_rep_7                                   |                                                                             |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/memory_mux_selector_reg_rep_6                                   |                                                                             |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                       | u_Controller/Interpreter/memory_mux_selector_reg_5                                       |                                                                             |               32 |            128 |         4.00 |
|  clk_core_BUFG                                                                    | u_klessydra_t0_2th_core/Pipe/decoded_instruction_IE0                                     |                                                                             |               87 |            163 |         1.87 |
+-----------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------+----------------+--------------+


