| .git |
| .github |
| .Xil |
| docs |
| fpga |
| software |
| src |
| tests |
| .gitattributes | May 12, 2025, 5:08:08 AM | 29 B | |
| .gitignore | May 12, 2025, 5:08:08 AM | 21 B | |
| build_digilent_arty_a7_100t.tcl | May 12, 2025, 5:08:15 AM | 2.99 KiB | |
| clockInfo.txt | May 12, 2025, 5:10:25 AM | 375 B | |
| digilent_arty_a7_100t.bit | May 12, 2025, 5:12:30 AM | 3.65 MiB | |
| digilent_arty_a7_clock_utilization.rpt | May 12, 2025, 5:10:38 AM | 16.56 KiB | |
| digilent_arty_a7_control_sets.rpt | May 12, 2025, 5:10:37 AM | 12.48 KiB | |
| digilent_arty_a7_drc.rpt | May 12, 2025, 5:12:02 AM | 2.36 KiB | |
| digilent_arty_a7_io.rpt | May 12, 2025, 5:10:37 AM | 96.82 KiB | |
| digilent_arty_a7_power.rpt | May 12, 2025, 5:12:03 AM | 8.55 KiB | |
| digilent_arty_a7_route_status.rpt | May 12, 2025, 5:11:59 AM | 651 B | |
| digilent_arty_a7_timing.rpt | May 12, 2025, 5:12:02 AM | 18.47 KiB | |
| digilent_arty_a7_utilization_hierarchical_place.rpt | May 12, 2025, 5:10:37 AM | 3.09 KiB | |
| digilent_arty_a7_utilization_place.rpt | May 12, 2025, 5:10:37 AM | 10.57 KiB | |
| LICENSE | May 12, 2025, 5:08:08 AM | 1.05 KiB | |
| processor_ci_defines.vh | May 12, 2025, 5:08:15 AM | 300 B | |
| README.md | May 12, 2025, 5:08:08 AM | 2.08 KiB | |
| simulation.out | May 12, 2025, 5:08:09 AM | 56.82 KiB | |
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