Started by user Julio Nunes Avelar [Pipeline] Start of Pipeline [Pipeline] node Still waiting to schedule task Waiting for next available executor Running on Jenkins in /var/lib/jenkins/workspace/Pequeno Risco ECP5 Yosys [Pipeline] { [Pipeline] stage [Pipeline] { (git_clone) [Pipeline] sh + rm -Rf Pequeno-Risco-5/ build/ [Pipeline] sh + git clone https://github.com/JN513/Pequeno-Risco-5.git Cloning into 'Pequeno-Risco-5'... [Pipeline] sh + cd Pequeno-Risco-5 [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (IVerilog) [Pipeline] sh + mkdir -p build [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o build/core_test.o -s core_tb Pequeno-Risco-5/src/alu.v Pequeno-Risco-5/src/alu_control.v Pequeno-Risco-5/src/control_unit.v Pequeno-Risco-5/src/core.v Pequeno-Risco-5/src/data_memory.v Pequeno-Risco-5/src/immediate_generator.v Pequeno-Risco-5/src/instruction_memory.v Pequeno-Risco-5/src/mux.v Pequeno-Risco-5/src/pc.v Pequeno-Risco-5/src/registers.v Pequeno-Risco-5/tests/core_test.v [Pipeline] sh + /eda/oss-cad-suite/bin/vvp build/core_test.o ERROR: Pequeno-Risco-5/src/instruction_memory.v:20: $readmemh: Unable to open software/memory/bne.hex for reading. VCD info: dumpfile build/core.vcd opened for output. Pequeno-Risco-5/tests/core_test.v:23: $finish called at 120 (1s) [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Yosys) [Pipeline] sh + /eda/oss-cad-suite/bin/yosys -p read_verilog Pequeno-Risco-5/fpga/ecp5/main.v; read_verilog Pequeno-Risco-5/src/*.v; synth_ecp5 -json ./build/out.json -abc9 /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf <claire@yosyshq.com> | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) -- Running command ` read_verilog Pequeno-Risco-5/fpga/ecp5/main.v; read_verilog Pequeno-Risco-5/src/*.v; synth_ecp5 -json ./build/out.json -abc9 ' -- 1. Executing Verilog-2005 frontend: Pequeno-Risco-5/fpga/ecp5/main.v Parsing Verilog input from `Pequeno-Risco-5/fpga/ecp5/main.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: Pequeno-Risco-5/src/alu.v Parsing Verilog input from `Pequeno-Risco-5/src/alu.v' to AST representation. Generating RTLIL representation for module `\ALU'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: Pequeno-Risco-5/src/alu_control.v Parsing Verilog input from `Pequeno-Risco-5/src/alu_control.v' to AST representation. Generating RTLIL representation for module `\ALU_Control'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: Pequeno-Risco-5/src/control_unit.v Parsing Verilog input from `Pequeno-Risco-5/src/control_unit.v' to AST representation. Generating RTLIL representation for module `\Control_Unit'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: Pequeno-Risco-5/src/core.v Parsing Verilog input from `Pequeno-Risco-5/src/core.v' to AST representation. Generating RTLIL representation for module `\Core'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: Pequeno-Risco-5/src/data_memory.v Parsing Verilog input from `Pequeno-Risco-5/src/data_memory.v' to AST representation. Generating RTLIL representation for module `\Data_Memory'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: Pequeno-Risco-5/src/immediate_generator.v Parsing Verilog input from `Pequeno-Risco-5/src/immediate_generator.v' to AST representation. Generating RTLIL representation for module `\Immediate_Generator'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: Pequeno-Risco-5/src/instruction_memory.v Parsing Verilog input from `Pequeno-Risco-5/src/instruction_memory.v' to AST representation. Generating RTLIL representation for module `\Instruction_Memory'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: Pequeno-Risco-5/src/mux.v Parsing Verilog input from `Pequeno-Risco-5/src/mux.v' to AST representation. Generating RTLIL representation for module `\MUX'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: Pequeno-Risco-5/src/pc.v Parsing Verilog input from `Pequeno-Risco-5/src/pc.v' to AST representation. Generating RTLIL representation for module `\PC'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: Pequeno-Risco-5/src/registers.v Parsing Verilog input from `Pequeno-Risco-5/src/registers.v' to AST representation. Generating RTLIL representation for module `\Registers'. Successfully finished Verilog frontend. 12. Executing SYNTH_ECP5 pass. 12.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 12.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 12.3. Executing HIERARCHY pass (managing design hierarchy). 12.3.1. Finding top of design hierarchy.. root of 0 design levels: Registers root of 0 design levels: PC root of 0 design levels: MUX root of 0 design levels: Instruction_Memory root of 0 design levels: Immediate_Generator root of 0 design levels: Data_Memory root of 1 design levels: Core root of 0 design levels: Control_Unit root of 0 design levels: ALU_Control root of 0 design levels: ALU root of 2 design levels: top Automatically selected top as design top module. 12.3.2. Analyzing design hierarchy.. Top module: \top Used module: \Core Used module: \Registers Used module: \Immediate_Generator Used module: \Data_Memory Used module: \Instruction_Memory Used module: \Control_Unit Used module: \ALU_Control Used module: \ALU Used module: \PC Used module: \MUX Parameter \MEMORY_FILE = 256'0010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101100110011100000110011101100001010111110111010001100101011100110111010000101110011010000110010101111000 12.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'. Parameter \MEMORY_FILE = 256'0010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101100110011100000110011101100001010111110111010001100101011100110111010000101110011010000110010101111000 Generating RTLIL representation for module `$paramod$8187afbf33560b800064823d5dcb03d397aac8aa\Core'. Parameter \MEMORY_SIZE = 1024 Parameter \MEMORY_FILE = { } 12.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Instruction_Memory'. Parameter \MEMORY_SIZE = 1024 Parameter \MEMORY_FILE = { } Generating RTLIL representation for module `$paramod$c489be178aab881f114c89e947475f7d1b9ca072\Instruction_Memory'. 12.3.5. Analyzing design hierarchy.. Top module: \top Used module: $paramod$8187afbf33560b800064823d5dcb03d397aac8aa\Core Used module: \Registers Used module: \Immediate_Generator Used module: \Data_Memory Used module: \Instruction_Memory Used module: \Control_Unit Used module: \ALU_Control Used module: \ALU Used module: \PC Used module: \MUX Parameter \MEMORY_SIZE = 1024 Parameter \MEMORY_FILE = 256'0010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101100110011100000110011101100001010111110111010001100101011100110111010000101110011010000110010101111000 12.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\Instruction_Memory'. Parameter \MEMORY_SIZE = 1024 Parameter \MEMORY_FILE = 256'0010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101100110011100000110011101100001010111110111010001100101011100110111010000101110011010000110010101111000 Generating RTLIL representation for module `$paramod$ea5ab62c4b9e74a8fc4617fff9c3041a495e653f\Instruction_Memory'. 12.3.7. Analyzing design hierarchy.. Top module: \top Used module: $paramod$8187afbf33560b800064823d5dcb03d397aac8aa\Core Used module: \Registers Used module: \Immediate_Generator Used module: \Data_Memory Used module: $paramod$ea5ab62c4b9e74a8fc4617fff9c3041a495e653f\Instruction_Memory Used module: \Control_Unit Used module: \ALU_Control Used module: \ALU Used module: \PC Used module: \MUX 12.3.8. Analyzing design hierarchy.. Top module: \top Used module: $paramod$8187afbf33560b800064823d5dcb03d397aac8aa\Core Used module: \Registers Used module: \Immediate_Generator Used module: \Data_Memory Used module: $paramod$ea5ab62c4b9e74a8fc4617fff9c3041a495e653f\Instruction_Memory Used module: \Control_Unit Used module: \ALU_Control Used module: \ALU Used module: \PC Used module: \MUX Removing unused module `$paramod$c489be178aab881f114c89e947475f7d1b9ca072\Instruction_Memory'. Removing unused module `\Instruction_Memory'. Removing unused module `\Core'. Removed 3 unused modules. 12.4. Executing PROC pass (convert processes to netlists). 12.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$6320'. Found and cleaned up 1 empty switch in `$paramod$ea5ab62c4b9e74a8fc4617fff9c3041a495e653f\Instruction_Memory.$proc$Pequeno-Risco-5/src/instruction_memory.v:0$6439'. Removing empty process `$paramod$ea5ab62c4b9e74a8fc4617fff9c3041a495e653f\Instruction_Memory.$proc$Pequeno-Risco-5/src/instruction_memory.v:0$6439'. Removing empty process `top.$proc$Pequeno-Risco-5/fpga/ecp5/main.v:17$1'. Cleaned up 2 empty switches. 12.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$6427 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$6379 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$6321 in module TRELLIS_DPR16X4. Removed 1 dead cases from process $proc$Pequeno-Risco-5/src/registers.v:158$6199 in module Registers. Marked 2 switch rules as full_case in process $proc$Pequeno-Risco-5/src/registers.v:158$6199 in module Registers. Removed 2 dead cases from process $proc$Pequeno-Risco-5/src/registers.v:82$6198 in module Registers. Marked 2 switch rules as full_case in process $proc$Pequeno-Risco-5/src/registers.v:82$6198 in module Registers. Marked 2 switch rules as full_case in process $proc$Pequeno-Risco-5/src/pc.v:18$6192 in module PC. Removed 2 dead cases from process $proc$Pequeno-Risco-5/src/immediate_generator.v:10$6187 in module Immediate_Generator. Marked 1 switch rules as full_case in process $proc$Pequeno-Risco-5/src/immediate_generator.v:10$6187 in module Immediate_Generator. Marked 2 switch rules as full_case in process $proc$Pequeno-Risco-5/src/data_memory.v:26$2082 in module Data_Memory. Marked 1 switch rules as full_case in process $proc$Pequeno-Risco-5/src/control_unit.v:12$23 in module Control_Unit. Removed 1 dead cases from process $proc$Pequeno-Risco-5/src/alu_control.v:13$19 in module ALU_Control. Marked 6 switch rules as full_case in process $proc$Pequeno-Risco-5/src/alu_control.v:13$19 in module ALU_Control. Marked 1 switch rules as full_case in process $proc$Pequeno-Risco-5/src/alu.v:14$4 in module ALU. Removed a total of 6 dead cases. 12.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 2138 assignments to connections. 12.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6428'. Set init value: \Q = 1'0 Found init rule in `\Registers.$proc$Pequeno-Risco-5/src/registers.v:0$6203'. Set init value: \register0 = 0 Set init value: \register1 = 0 Set init value: \register2 = 0 Set init value: \register3 = 0 Set init value: \register4 = 0 Set init value: \register5 = 0 Set init value: \register6 = 0 Set init value: \register7 = 0 Set init value: \register8 = 0 Set init value: \register9 = 0 Set init value: \register10 = 0 Set init value: \register11 = 0 Set init value: \register12 = 0 Set init value: \register13 = 0 Set init value: \register14 = 0 Set init value: \register15 = 0 Set init value: \register16 = 0 Set init value: \register17 = 0 Set init value: \register18 = 0 Set init value: \register19 = 0 Set init value: \register20 = 0 Set init value: \register21 = 0 Set init value: \register22 = 0 Set init value: \register23 = 0 Set init value: \register24 = 0 Set init value: \register25 = 0 Set init value: \register26 = 0 Set init value: \register27 = 0 Set init value: \register28 = 0 Set init value: \register29 = 0 Set init value: \register30 = 0 Set init value: \register31 = 0 Found init rule in `\PC.$proc$Pequeno-Risco-5/src/pc.v:0$6197'. Set init value: \PC_Register = 0 Found init rule in `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. Set init value: \i = 1023 12.4.5. Executing PROC_ARST pass (detect async resets in processes). 12.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~23 debug messages> 12.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6428'. Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$6427'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$6379'. 1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$6378_EN[3:0]$6385 2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$6378_DATA[3:0]$6384 3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$6378_ADDR[3:0]$6383 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$6321'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$6319_EN[3:0]$6327 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$6319_DATA[3:0]$6326 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$6319_ADDR[3:0]$6325 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$6320'. Creating decoders for process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:0$6203'. Creating decoders for process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. 1/32: $0\register31[31:0] 2/32: $0\register30[31:0] 3/32: $0\register29[31:0] 4/32: $0\register28[31:0] 5/32: $0\register27[31:0] 6/32: $0\register26[31:0] 7/32: $0\register25[31:0] 8/32: $0\register24[31:0] 9/32: $0\register23[31:0] 10/32: $0\register22[31:0] 11/32: $0\register21[31:0] 12/32: $0\register20[31:0] 13/32: $0\register19[31:0] 14/32: $0\register18[31:0] 15/32: $0\register17[31:0] 16/32: $0\register16[31:0] 17/32: $0\register15[31:0] 18/32: $0\register14[31:0] 19/32: $0\register13[31:0] 20/32: $0\register12[31:0] 21/32: $0\register11[31:0] 22/32: $0\register10[31:0] 23/32: $0\register9[31:0] 24/32: $0\register8[31:0] 25/32: $0\register7[31:0] 26/32: $0\register6[31:0] 27/32: $0\register5[31:0] 28/32: $0\register4[31:0] 29/32: $0\register3[31:0] 30/32: $0\register2[31:0] 31/32: $0\register1[31:0] 32/32: $0\register0[31:0] Creating decoders for process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:82$6198'. 1/2: $1\readData2[31:0] 2/2: $1\readData1[31:0] Creating decoders for process `\PC.$proc$Pequeno-Risco-5/src/pc.v:0$6197'. Creating decoders for process `\PC.$proc$Pequeno-Risco-5/src/pc.v:18$6192'. 1/1: $0\PC_Register[31:0] Creating decoders for process `\Immediate_Generator.$proc$Pequeno-Risco-5/src/immediate_generator.v:10$6187'. 1/1: $1\immediate_reg[31:0] Creating decoders for process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. Creating decoders for process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. 1/1030: $2$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$4139 2/1030: $2$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_DATA[31:0]$4138 3/1030: $2$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_ADDR[31:0]$4137 4/1030: $1\i[31:0] 5/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$4132 6/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$4131 7/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$4130 8/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$4129 9/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$4128 10/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$4127 11/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$4126 12/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$4125 13/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$4124 14/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$4123 15/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$4122 16/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$4121 17/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$4120 18/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$4119 19/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$4118 20/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$4117 21/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$4116 22/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$4115 23/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$4114 24/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$4113 25/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$4112 26/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$4111 27/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$4110 28/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$4109 29/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$4108 30/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$4107 31/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$4106 32/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$4105 33/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$4104 34/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$4103 35/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$4102 36/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$4101 37/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$4100 38/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$4099 39/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$4098 40/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$4097 41/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$4096 42/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$4095 43/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$4094 44/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$4093 45/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$4092 46/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$4091 47/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$4090 48/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$4089 49/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$4088 50/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$4087 51/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$4086 52/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$4085 53/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$4084 54/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$4083 55/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$4082 56/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$4081 57/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$4080 58/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$4079 59/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$4078 60/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$4077 61/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$4076 62/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$4075 63/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$4074 64/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$4073 65/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$4072 66/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$4071 67/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$4070 68/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$4069 69/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$4068 70/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$4067 71/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$4066 72/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$4065 73/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$4064 74/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$4063 75/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$4062 76/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$4061 77/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$4060 78/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$4059 79/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$4058 80/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$4057 81/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$4056 82/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$4055 83/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$4054 84/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$4053 85/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$4052 86/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$4051 87/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$4050 88/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$4049 89/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$4048 90/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$4047 91/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$4046 92/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$4045 93/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$4044 94/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$4043 95/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$4042 96/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$4041 97/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$4040 98/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$4039 99/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$4038 100/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$4037 101/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$4036 102/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$4035 103/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$4034 104/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$4033 105/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$4032 106/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$4031 107/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$4030 108/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$4029 109/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$4028 110/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$4027 111/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$4026 112/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$4025 113/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$4024 114/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$4023 115/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$4022 116/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$4021 117/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$4020 118/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$4019 119/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$4018 120/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$4017 121/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$4016 122/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$4015 123/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$4014 124/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$4013 125/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$4012 126/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$4011 127/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$4010 128/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$4009 129/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$4008 130/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$4007 131/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$4006 132/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$4005 133/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$4004 134/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$4003 135/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$4002 136/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$4001 137/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$4000 138/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$3999 139/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$3998 140/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$3997 141/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$3996 142/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$3995 143/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$3994 144/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$3993 145/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$3992 146/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$3991 147/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$3990 148/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$3989 149/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$3988 150/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$3987 151/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$3986 152/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$3985 153/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$3984 154/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$3983 155/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$3982 156/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$3981 157/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$3980 158/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$3979 159/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$3978 160/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$3977 161/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$3976 162/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$3975 163/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$3974 164/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$3973 165/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$3972 166/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$3971 167/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$3970 168/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$3969 169/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$3968 170/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$3967 171/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$3966 172/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$3965 173/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$3964 174/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$3963 175/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$3962 176/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$3961 177/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$3960 178/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$3959 179/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$3958 180/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$3957 181/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$3956 182/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$3955 183/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$3954 184/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$3953 185/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$3952 186/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$3951 187/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$3950 188/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$3949 189/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$3948 190/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$3947 191/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$3946 192/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$3945 193/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$3944 194/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$3943 195/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$3942 196/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$3941 197/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$3940 198/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$3939 199/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$3938 200/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$3937 201/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$3936 202/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$3935 203/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$3934 204/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$3933 205/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$3932 206/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$3931 207/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$3930 208/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$3929 209/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$3928 210/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$3927 211/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$3926 212/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$3925 213/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$3924 214/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$3923 215/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$3922 216/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$3921 217/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$3920 218/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$3919 219/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$3918 220/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$3917 221/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$3916 222/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$3915 223/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$3914 224/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$3913 225/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$3912 226/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$3911 227/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$3910 228/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$3909 229/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$3908 230/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$3907 231/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$3906 232/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$3905 233/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$3904 234/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$3903 235/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$3902 236/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$3901 237/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$3900 238/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$3899 239/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$3898 240/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$3897 241/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$3896 242/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$3895 243/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$3894 244/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$3893 245/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$3892 246/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$3891 247/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$3890 248/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$3889 249/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$3888 250/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$3887 251/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$3886 252/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$3885 253/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$3884 254/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$3883 255/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$3882 256/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$3881 257/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$3880 258/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$3879 259/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$3878 260/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$3877 261/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$3876 262/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$3875 263/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$3874 264/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$3873 265/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$3872 266/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$3871 267/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$3870 268/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$3869 269/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$3868 270/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$3867 271/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$3866 272/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$3865 273/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$3864 274/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$3863 275/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$3862 276/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$3861 277/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$3860 278/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$3859 279/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$3858 280/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$3857 281/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$3856 282/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$3855 283/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$3854 284/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$3853 285/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$3852 286/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$3851 287/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$3850 288/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$3849 289/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$3848 290/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$3847 291/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$3846 292/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$3845 293/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$3844 294/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$3843 295/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$3842 296/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$3841 297/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$3840 298/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$3839 299/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$3838 300/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$3837 301/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$3836 302/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$3835 303/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$3834 304/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$3833 305/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$3832 306/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$3831 307/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$3830 308/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$3829 309/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$3828 310/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$3827 311/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$3826 312/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$3825 313/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$3824 314/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$3823 315/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$3822 316/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$3821 317/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$3820 318/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$3819 319/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$3818 320/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$3817 321/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$3816 322/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$3815 323/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$3814 324/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$3813 325/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$3812 326/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$3811 327/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$3810 328/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$3809 329/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$3808 330/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$3807 331/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$3806 332/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$3805 333/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$3804 334/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$3803 335/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$3802 336/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$3801 337/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$3800 338/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$3799 339/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$3798 340/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$3797 341/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$3796 342/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$3795 343/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$3794 344/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$3793 345/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$3792 346/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$3791 347/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$3790 348/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$3789 349/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$3788 350/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$3787 351/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$3786 352/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$3785 353/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$3784 354/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$3783 355/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$3782 356/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$3781 357/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$3780 358/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$3779 359/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$3778 360/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$3777 361/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$3776 362/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$3775 363/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$3774 364/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$3773 365/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$3772 366/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$3771 367/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$3770 368/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$3769 369/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$3768 370/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$3767 371/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$3766 372/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$3765 373/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$3764 374/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$3763 375/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$3762 376/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$3761 377/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$3760 378/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$3759 379/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$3758 380/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$3757 381/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$3756 382/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$3755 383/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$3754 384/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$3753 385/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$3752 386/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$3751 387/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$3750 388/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$3749 389/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$3748 390/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$3747 391/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$3746 392/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$3745 393/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$3744 394/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$3743 395/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$3742 396/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$3741 397/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$3740 398/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$3739 399/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$3738 400/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$3737 401/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$3736 402/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$3735 403/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$3734 404/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$3733 405/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$3732 406/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$3731 407/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$3730 408/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$3729 409/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$3728 410/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$3727 411/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$3726 412/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$3725 413/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$3724 414/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$3723 415/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$3722 416/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$3721 417/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$3720 418/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$3719 419/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$3718 420/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$3717 421/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$3716 422/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$3715 423/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$3714 424/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$3713 425/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$3712 426/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$3711 427/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$3710 428/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$3709 429/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$3708 430/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$3707 431/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$3706 432/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$3705 433/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$3704 434/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$3703 435/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$3702 436/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$3701 437/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$3700 438/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$3699 439/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$3698 440/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$3697 441/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$3696 442/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$3695 443/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$3694 444/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$3693 445/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$3692 446/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$3691 447/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$3690 448/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$3689 449/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$3688 450/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$3687 451/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$3686 452/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$3685 453/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$3684 454/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$3683 455/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$3682 456/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$3681 457/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$3680 458/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$3679 459/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$3678 460/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$3677 461/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$3676 462/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$3675 463/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$3674 464/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$3673 465/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$3672 466/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$3671 467/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$3670 468/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$3669 469/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$3668 470/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$3667 471/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$3666 472/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$3665 473/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$3664 474/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$3663 475/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$3662 476/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$3661 477/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$3660 478/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$3659 479/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$3658 480/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$3657 481/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$3656 482/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$3655 483/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$3654 484/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$3653 485/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$3652 486/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$3651 487/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$3650 488/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$3649 489/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$3648 490/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$3647 491/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$3646 492/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$3645 493/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$3644 494/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$3643 495/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$3642 496/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$3641 497/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$3640 498/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$3639 499/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$3638 500/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$3637 501/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$3636 502/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$3635 503/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$3634 504/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$3633 505/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$3632 506/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$3631 507/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$3630 508/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$3629 509/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$3628 510/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$3627 511/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$3626 512/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$3625 513/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$3624 514/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$3623 515/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$3622 516/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$3621 517/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$3620 518/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$3619 519/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$3618 520/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$3617 521/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$3616 522/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$3615 523/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$3614 524/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$3613 525/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$3612 526/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$3611 527/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$3610 528/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$3609 529/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$3608 530/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$3607 531/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$3606 532/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$3605 533/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$3604 534/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$3603 535/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$3602 536/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$3601 537/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$3600 538/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$3599 539/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$3598 540/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$3597 541/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$3596 542/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$3595 543/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$3594 544/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$3593 545/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$3592 546/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$3591 547/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$3590 548/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$3589 549/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$3588 550/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$3587 551/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$3586 552/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$3585 553/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$3584 554/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$3583 555/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$3582 556/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$3581 557/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$3580 558/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$3579 559/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$3578 560/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$3577 561/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$3576 562/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$3575 563/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$3574 564/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$3573 565/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$3572 566/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$3571 567/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$3570 568/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$3569 569/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$3568 570/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$3567 571/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$3566 572/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$3565 573/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$3564 574/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$3563 575/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$3562 576/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$3561 577/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$3560 578/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$3559 579/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$3558 580/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$3557 581/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$3556 582/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$3555 583/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$3554 584/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$3553 585/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$3552 586/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$3551 587/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$3550 588/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$3549 589/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$3548 590/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$3547 591/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$3546 592/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$3545 593/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$3544 594/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$3543 595/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$3542 596/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$3541 597/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$3540 598/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$3539 599/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$3538 600/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$3537 601/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$3536 602/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$3535 603/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$3534 604/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$3533 605/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$3532 606/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$3531 607/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$3530 608/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$3529 609/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$3528 610/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$3527 611/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$3526 612/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$3525 613/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$3524 614/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$3523 615/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$3522 616/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$3521 617/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$3520 618/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$3519 619/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$3518 620/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$3517 621/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$3516 622/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$3515 623/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$3514 624/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$3513 625/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$3512 626/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$3511 627/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$3510 628/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$3509 629/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$3508 630/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$3507 631/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$3506 632/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$3505 633/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$3504 634/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$3503 635/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$3502 636/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$3501 637/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$3500 638/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$3499 639/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$3498 640/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$3497 641/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$3496 642/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$3495 643/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$3494 644/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$3493 645/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$3492 646/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$3491 647/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$3490 648/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$3489 649/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$3488 650/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$3487 651/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$3486 652/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$3485 653/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$3484 654/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$3483 655/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$3482 656/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$3481 657/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$3480 658/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$3479 659/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$3478 660/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$3477 661/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$3476 662/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$3475 663/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$3474 664/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$3473 665/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$3472 666/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$3471 667/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$3470 668/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$3469 669/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$3468 670/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$3467 671/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$3466 672/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$3465 673/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$3464 674/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$3463 675/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$3462 676/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$3461 677/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$3460 678/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$3459 679/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$3458 680/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$3457 681/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$3456 682/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$3455 683/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$3454 684/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$3453 685/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$3452 686/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$3451 687/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$3450 688/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$3449 689/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$3448 690/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$3447 691/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$3446 692/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$3445 693/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$3444 694/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$3443 695/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$3442 696/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$3441 697/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$3440 698/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$3439 699/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$3438 700/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$3437 701/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$3436 702/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$3435 703/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$3434 704/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$3433 705/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$3432 706/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$3431 707/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$3430 708/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$3429 709/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$3428 710/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$3427 711/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$3426 712/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$3425 713/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$3424 714/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$3423 715/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$3422 716/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$3421 717/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$3420 718/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$3419 719/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$3418 720/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$3417 721/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$3416 722/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$3415 723/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$3414 724/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$3413 725/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$3412 726/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$3411 727/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$3410 728/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$3409 729/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$3408 730/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$3407 731/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$3406 732/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$3405 733/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$3404 734/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$3403 735/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$3402 736/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$3401 737/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$3400 738/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$3399 739/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$3398 740/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$3397 741/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$3396 742/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$3395 743/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$3394 744/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$3393 745/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$3392 746/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$3391 747/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$3390 748/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$3389 749/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$3388 750/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$3387 751/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$3386 752/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$3385 753/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$3384 754/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$3383 755/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$3382 756/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$3381 757/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$3380 758/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$3379 759/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$3378 760/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$3377 761/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$3376 762/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$3375 763/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$3374 764/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$3373 765/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$3372 766/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$3371 767/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$3370 768/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$3369 769/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$3368 770/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$3367 771/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$3366 772/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$3365 773/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$3364 774/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$3363 775/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$3362 776/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$3361 777/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$3360 778/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$3359 779/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$3358 780/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$3357 781/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$3356 782/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$3355 783/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$3354 784/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$3353 785/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$3352 786/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$3351 787/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$3350 788/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$3349 789/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$3348 790/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$3347 791/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$3346 792/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$3345 793/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$3344 794/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$3343 795/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$3342 796/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$3341 797/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$3340 798/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$3339 799/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$3338 800/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$3337 801/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$3336 802/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$3335 803/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$3334 804/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$3333 805/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$3332 806/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$3331 807/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$3330 808/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$3329 809/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$3328 810/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$3327 811/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$3326 812/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$3325 813/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$3324 814/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$3323 815/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$3322 816/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$3321 817/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$3320 818/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$3319 819/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$3318 820/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$3317 821/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$3316 822/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$3315 823/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$3314 824/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$3313 825/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$3312 826/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$3311 827/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$3310 828/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$3309 829/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$3308 830/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$3307 831/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$3306 832/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$3305 833/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$3304 834/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$3303 835/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$3302 836/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$3301 837/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$3300 838/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$3299 839/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$3298 840/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$3297 841/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$3296 842/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$3295 843/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$3294 844/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$3293 845/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$3292 846/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$3291 847/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$3290 848/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$3289 849/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$3288 850/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$3287 851/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$3286 852/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$3285 853/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$3284 854/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$3283 855/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$3282 856/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$3281 857/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$3280 858/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$3279 859/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$3278 860/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$3277 861/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$3276 862/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$3275 863/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$3274 864/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$3273 865/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$3272 866/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$3271 867/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$3270 868/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$3269 869/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$3268 870/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$3267 871/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$3266 872/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$3265 873/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$3264 874/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$3263 875/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$3262 876/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$3261 877/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$3260 878/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$3259 879/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$3258 880/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$3257 881/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$3256 882/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$3255 883/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$3254 884/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$3253 885/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$3252 886/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$3251 887/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$3250 888/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$3249 889/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$3248 890/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$3247 891/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$3246 892/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$3245 893/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$3244 894/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$3243 895/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$3242 896/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$3241 897/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$3240 898/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$3239 899/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$3238 900/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$3237 901/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$3236 902/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$3235 903/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$3234 904/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$3233 905/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$3232 906/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$3231 907/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$3230 908/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$3229 909/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$3228 910/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$3227 911/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$3226 912/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$3225 913/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$3224 914/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$3223 915/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$3222 916/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$3221 917/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$3220 918/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$3219 919/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$3218 920/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$3217 921/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$3216 922/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$3215 923/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$3214 924/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$3213 925/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$3212 926/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$3211 927/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$3210 928/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$3209 929/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$3208 930/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$3207 931/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$3206 932/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$3205 933/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$3204 934/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$3203 935/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$3202 936/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$3201 937/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$3200 938/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$3199 939/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$3198 940/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$3197 941/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$3196 942/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$3195 943/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$3194 944/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$3193 945/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$3192 946/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$3191 947/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$3190 948/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$3189 949/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$3188 950/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$3187 951/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$3186 952/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$3185 953/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$3184 954/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$3183 955/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$3182 956/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$3181 957/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$3180 958/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$3179 959/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$3178 960/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$3177 961/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$3176 962/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$3175 963/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$3174 964/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$3173 965/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$3172 966/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$3171 967/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$3170 968/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$3169 969/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$3168 970/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$3167 971/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$3166 972/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$3165 973/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$3164 974/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$3163 975/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$3162 976/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$3161 977/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$3160 978/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$3159 979/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$3158 980/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$3157 981/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$3156 982/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$3155 983/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$3154 984/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$3153 985/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$3152 986/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$3151 987/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$3150 988/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$3149 989/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$3148 990/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$3147 991/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$3146 992/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$3145 993/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$3144 994/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$3143 995/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$3142 996/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$3141 997/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$3140 998/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$3139 999/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$3138 1000/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$3137 1001/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$3136 1002/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$3135 1003/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$3134 1004/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$3133 1005/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$3132 1006/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$3131 1007/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$3130 1008/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$3129 1009/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$3128 1010/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$3127 1011/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$3126 1012/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$3125 1013/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$3124 1014/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$3123 1015/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$3122 1016/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$3121 1017/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$3120 1018/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$3119 1019/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$3118 1020/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$3117 1021/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$3116 1022/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$3115 1023/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$3114 1024/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$3113 1025/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$3112 1026/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$3111 1027/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$3110 1028/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$4135 1029/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_DATA[31:0]$4134 1030/1030: $1$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_ADDR[31:0]$4133 Creating decoders for process `\Control_Unit.$proc$Pequeno-Risco-5/src/control_unit.v:12$23'. 1/7: $1\aluop[1:0] 2/7: $1\branch[0:0] 3/7: $1\memory_write[0:0] 4/7: $1\memory_read[0:0] 5/7: $1\reg_write[0:0] 6/7: $1\memory_to_reg[0:0] 7/7: $1\alu_src[0:0] Creating decoders for process `\ALU_Control.$proc$Pequeno-Risco-5/src/alu_control.v:13$19'. 1/6: $6\aluop_out_reg[3:0] 2/6: $5\aluop_out_reg[3:0] 3/6: $4\aluop_out_reg[3:0] 4/6: $3\aluop_out_reg[3:0] 5/6: $2\aluop_out_reg[3:0] 6/6: $1\aluop_out_reg[3:0] Creating decoders for process `\ALU.$proc$Pequeno-Risco-5/src/alu.v:14$4'. 1/1: $1\ALU_Result[31:0] 12.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\Registers.\readData1' from process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:82$6198'. No latch inferred for signal `\Registers.\readData2' from process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:82$6198'. No latch inferred for signal `\Immediate_Generator.\immediate_reg' from process `\Immediate_Generator.$proc$Pequeno-Risco-5/src/immediate_generator.v:10$6187'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$32_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$33_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$34_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$35_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$36_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$37_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$38_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$39_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$40_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$41_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$42_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$43_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$44_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$45_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$46_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$47_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$48_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$49_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$50_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$51_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$52_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$53_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$54_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$55_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$56_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$57_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$58_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$59_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$60_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$61_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$62_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$63_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$64_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$65_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$66_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$67_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$68_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$69_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$70_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$71_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$72_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$73_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$74_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$75_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$76_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$77_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$78_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$79_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$80_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$81_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$82_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$83_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$84_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$85_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$86_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$87_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$88_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$89_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$90_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$91_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$92_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$93_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$94_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$95_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$96_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$97_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$98_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$99_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$100_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$101_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$102_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$103_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$104_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$105_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$106_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$107_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$108_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$109_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$110_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$111_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$112_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$113_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$114_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$115_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$116_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$117_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$118_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$119_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$120_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$121_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$122_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$123_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$124_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$125_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$126_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$127_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$128_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$129_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$130_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$131_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$132_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$133_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$134_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$135_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$136_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$137_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$138_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$139_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$140_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$141_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$142_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$143_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$144_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$145_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$146_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$147_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$148_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$149_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$150_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$151_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$152_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$153_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$154_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$155_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$156_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$157_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$158_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$159_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$160_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$161_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$162_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$163_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$164_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$165_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$166_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$167_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$168_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$169_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$170_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$171_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$172_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$173_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$174_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$175_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$176_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$177_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$178_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$179_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$180_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$181_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$182_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$183_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$184_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$185_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$186_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$187_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$188_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$189_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$190_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$191_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$192_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$193_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$194_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$195_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$196_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$197_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$198_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$199_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$200_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$201_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$202_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$203_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$204_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$205_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$206_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$207_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$208_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$209_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$210_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$211_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$212_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$213_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$214_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$215_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$216_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$217_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$218_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$219_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$220_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$221_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$222_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$223_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$224_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$225_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$226_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$227_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$228_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$229_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$230_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$231_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$232_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$233_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$234_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$235_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$236_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$237_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$238_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$239_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$240_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$241_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$242_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$243_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$244_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$245_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$246_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$247_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$248_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$249_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$250_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$251_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$252_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$253_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$254_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$255_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$256_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$257_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$258_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$259_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$260_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$261_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$262_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$263_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$264_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$265_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$266_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$267_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$268_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$269_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$270_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$271_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$272_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$273_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$274_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$275_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$276_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$277_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$278_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$279_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$280_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$281_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$282_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$283_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$284_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$285_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$286_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$287_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$288_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$289_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$290_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$291_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$292_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$293_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$294_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$295_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$296_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$297_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$298_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$299_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$300_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$301_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$302_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$303_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$304_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$305_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$306_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$307_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$308_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$309_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$310_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$311_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$312_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$313_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$314_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$315_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$316_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$317_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$318_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$319_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$320_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$321_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$322_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$323_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$324_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$325_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$326_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$327_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$328_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$329_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$330_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$331_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$332_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$333_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$334_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$335_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$336_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$337_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$338_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$339_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$340_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$341_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$342_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$343_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$344_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$345_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$346_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$347_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$348_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$349_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$350_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$351_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$352_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$353_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$354_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$355_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$356_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$357_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$358_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$359_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$360_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$361_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$362_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$363_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$364_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$365_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$366_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$367_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$368_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$369_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$370_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$371_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$372_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$373_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$374_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$375_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$376_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$377_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$378_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$379_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$380_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$381_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$382_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$383_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$384_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$385_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$386_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$387_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$388_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$389_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$390_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$391_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$392_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$393_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$394_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$395_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$396_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$397_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$398_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$399_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$400_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$401_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$402_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$403_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$404_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$405_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$406_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$407_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$408_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$409_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$410_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$411_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$412_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$413_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$414_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$415_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$416_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$417_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$418_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$419_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$420_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$421_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$422_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$423_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$424_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$425_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$426_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$427_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$428_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$429_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$430_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$431_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$432_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$433_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$434_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$435_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$436_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$437_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$438_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$439_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$440_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$441_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$442_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$443_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$444_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$445_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$446_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$447_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$448_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$449_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$450_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$451_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$452_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$453_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$454_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$455_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$456_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$457_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$458_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$459_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$460_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$461_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$462_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$463_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$464_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$465_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$466_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$467_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$468_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$469_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$470_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$471_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$472_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$473_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$474_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$475_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$476_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$477_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$478_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$479_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$480_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$481_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$482_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$483_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$484_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$485_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$486_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$487_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$488_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$489_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$490_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$491_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$492_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$493_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$494_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$495_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$496_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$497_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$498_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$499_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$500_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$501_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$502_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$503_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$504_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$505_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$506_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$507_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$508_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$509_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$510_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$511_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$512_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$513_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$514_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$515_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$516_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$517_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$518_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$519_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$520_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$521_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$522_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$523_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$524_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$525_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$526_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$527_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$528_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$529_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$530_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$531_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$532_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$533_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$534_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$535_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$536_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$537_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$538_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$539_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$540_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$541_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$542_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$543_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$544_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$545_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$546_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$547_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$548_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$549_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$550_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$551_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$552_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$553_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$554_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$555_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$556_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$557_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$558_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$559_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$560_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$561_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$562_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$563_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$564_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$565_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$566_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$567_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$568_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$569_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$570_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$571_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$572_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$573_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$574_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$575_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$576_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$577_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$578_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$579_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$580_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$581_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$582_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$583_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$584_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$585_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$586_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$587_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$588_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$589_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$590_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$591_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$592_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$593_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$594_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$595_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$596_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$597_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$598_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$599_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$600_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$601_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$602_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$603_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$604_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$605_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$606_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$607_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$608_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$609_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$610_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$611_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$612_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$613_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$614_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$615_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$616_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$617_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$618_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$619_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$620_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$621_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$622_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$623_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$624_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$625_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$626_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$627_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$628_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$629_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$630_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$631_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$632_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$633_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$634_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$635_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$636_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$637_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$638_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$639_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$640_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$641_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$642_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$643_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$644_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$645_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$646_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$647_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$648_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$649_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$650_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$651_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$652_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$653_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$654_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$655_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$656_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$657_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$658_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$659_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$660_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$661_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$662_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$663_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$664_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$665_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$666_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$667_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$668_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$669_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$670_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$671_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$672_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$673_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$674_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$675_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$676_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$677_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$678_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$679_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$680_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$681_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$682_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$683_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$684_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$685_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$686_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$687_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$688_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$689_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$690_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$691_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$692_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$693_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$694_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$695_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$696_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$697_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$698_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$699_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$700_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$701_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$702_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$703_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$704_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$705_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$706_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$707_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$708_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$709_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$710_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$711_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$712_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$713_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$714_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$715_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$716_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$717_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$718_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$719_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$720_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$721_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$722_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$723_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$724_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$725_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$726_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$727_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$728_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$729_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$730_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$731_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$732_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$733_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$734_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$735_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$736_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$737_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$738_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$739_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$740_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$741_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$742_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$743_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$744_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$745_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$746_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$747_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$748_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$749_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$750_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$751_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$752_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$753_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$754_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$755_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$756_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$757_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$758_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$759_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$760_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$761_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$762_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$763_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$764_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$765_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$766_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$767_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$768_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$769_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$770_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$771_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$772_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$773_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$774_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$775_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$776_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$777_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$778_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$779_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$780_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$781_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$782_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$783_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$784_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$785_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$786_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$787_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$788_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$789_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$790_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$791_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$792_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$793_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$794_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$795_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$796_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$797_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$798_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$799_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$800_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$801_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$802_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$803_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$804_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$805_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$806_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$807_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$808_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$809_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$810_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$811_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$812_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$813_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$814_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$815_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$816_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$817_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$818_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$819_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$820_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$821_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$822_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$823_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$824_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$825_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$826_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$827_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$828_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$829_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$830_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$831_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$832_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$833_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$834_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$835_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$836_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$837_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$838_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$839_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$840_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$841_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$842_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$843_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$844_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$845_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$846_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$847_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$848_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$849_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$850_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$851_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$852_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$853_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$854_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$855_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$856_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$857_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$858_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$859_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$860_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$861_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$862_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$863_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$864_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$865_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$866_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$867_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$868_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$869_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$870_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$871_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$872_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$873_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$874_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$875_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$876_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$877_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$878_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$879_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$880_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$881_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$882_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$883_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$884_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$885_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$886_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$887_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$888_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$889_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$890_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$891_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$892_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$893_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$894_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$895_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$896_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$897_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$898_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$899_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$900_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$901_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$902_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$903_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$904_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$905_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$906_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$907_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$908_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$909_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$910_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$911_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$912_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$913_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$914_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$915_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$916_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$917_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$918_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$919_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$920_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$921_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$922_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$923_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$924_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$925_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$926_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$927_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$928_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$929_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$930_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$931_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$932_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$933_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$934_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$935_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$936_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$937_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$938_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$939_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$940_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$941_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$942_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$943_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$944_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$945_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$946_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$947_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$948_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$949_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$950_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$951_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$952_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$953_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$954_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$955_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$956_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$957_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$958_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$959_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$960_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$961_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$962_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$963_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$964_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$965_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$966_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$967_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$968_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$969_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$970_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$971_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$972_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$973_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$974_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$975_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$976_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$977_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$978_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$979_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$980_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$981_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$982_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$983_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$984_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$985_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$986_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$987_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$988_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$989_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$990_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$991_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$992_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$993_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$994_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$995_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$996_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$997_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$998_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$999_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1000_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1001_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1002_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1003_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1004_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1005_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1006_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1007_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1008_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1009_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1010_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1011_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1012_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1013_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1014_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1015_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1016_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1017_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1018_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1019_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1020_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1021_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1022_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1023_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1024_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1025_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1026_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1027_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1028_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1029_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1030_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1031_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1032_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1033_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1034_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1035_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1036_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1037_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1038_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1039_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1040_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1041_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1042_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1043_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1044_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1045_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1046_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1047_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1048_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1049_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1050_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1051_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1052_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1053_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. No latch inferred for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:22$1054_EN' from process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. Latch inferred for signal `\Control_Unit.\branch' from process `\Control_Unit.$proc$Pequeno-Risco-5/src/control_unit.v:12$23': $auto$proc_dlatch.cc:433:proc_dlatch$10490 Latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Pequeno-Risco-5/src/control_unit.v:12$23': $auto$proc_dlatch.cc:433:proc_dlatch$10525 Latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Pequeno-Risco-5/src/control_unit.v:12$23': $auto$proc_dlatch.cc:433:proc_dlatch$10560 Latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Pequeno-Risco-5/src/control_unit.v:12$23': $auto$proc_dlatch.cc:433:proc_dlatch$10595 Latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Pequeno-Risco-5/src/control_unit.v:12$23': $auto$proc_dlatch.cc:433:proc_dlatch$10630 Latch inferred for signal `\Control_Unit.\alu_src' from process `\Control_Unit.$proc$Pequeno-Risco-5/src/control_unit.v:12$23': $auto$proc_dlatch.cc:433:proc_dlatch$10665 Latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Pequeno-Risco-5/src/control_unit.v:12$23': $auto$proc_dlatch.cc:433:proc_dlatch$10700 No latch inferred for signal `\ALU_Control.\aluop_out_reg' from process `\ALU_Control.$proc$Pequeno-Risco-5/src/alu_control.v:13$19'. No latch inferred for signal `\ALU.\ALU_Result' from process `\ALU.$proc$Pequeno-Risco-5/src/alu.v:14$4'. 12.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$6427'. created $dff cell `$procdff$10735' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6363_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6364_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6365_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6366_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6367_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6368_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6369_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6370_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6371_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6372_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6373_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6374_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6375_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6376_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$6377_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$6378_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$6379'. created $dff cell `$procdff$10736' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$6378_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$6379'. created $dff cell `$procdff$10737' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$6378_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$6379'. created $dff cell `$procdff$10738' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6303_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6304_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6305_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6306_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6307_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6308_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6309_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6310_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6311_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6312_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6313_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6314_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6315_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6316_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6317_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$6318_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$6319_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$6321'. created $dff cell `$procdff$10739' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$6319_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$6321'. created $dff cell `$procdff$10740' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$6319_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$6321'. created $dff cell `$procdff$10741' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$6320'. created direct connection (no actual register cell created). Creating register for signal `\Registers.\register0' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10742' with positive edge clock. Creating register for signal `\Registers.\register1' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10743' with positive edge clock. Creating register for signal `\Registers.\register2' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10744' with positive edge clock. Creating register for signal `\Registers.\register3' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10745' with positive edge clock. Creating register for signal `\Registers.\register4' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10746' with positive edge clock. Creating register for signal `\Registers.\register5' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10747' with positive edge clock. Creating register for signal `\Registers.\register6' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10748' with positive edge clock. Creating register for signal `\Registers.\register7' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10749' with positive edge clock. Creating register for signal `\Registers.\register8' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10750' with positive edge clock. Creating register for signal `\Registers.\register9' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10751' with positive edge clock. Creating register for signal `\Registers.\register10' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10752' with positive edge clock. Creating register for signal `\Registers.\register11' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10753' with positive edge clock. Creating register for signal `\Registers.\register12' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10754' with positive edge clock. Creating register for signal `\Registers.\register13' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10755' with positive edge clock. Creating register for signal `\Registers.\register14' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10756' with positive edge clock. Creating register for signal `\Registers.\register15' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10757' with positive edge clock. Creating register for signal `\Registers.\register16' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10758' with positive edge clock. Creating register for signal `\Registers.\register17' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10759' with positive edge clock. Creating register for signal `\Registers.\register18' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10760' with positive edge clock. Creating register for signal `\Registers.\register19' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10761' with positive edge clock. Creating register for signal `\Registers.\register20' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10762' with positive edge clock. Creating register for signal `\Registers.\register21' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10763' with positive edge clock. Creating register for signal `\Registers.\register22' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10764' with positive edge clock. Creating register for signal `\Registers.\register23' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10765' with positive edge clock. Creating register for signal `\Registers.\register24' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10766' with positive edge clock. Creating register for signal `\Registers.\register25' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10767' with positive edge clock. Creating register for signal `\Registers.\register26' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10768' with positive edge clock. Creating register for signal `\Registers.\register27' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10769' with positive edge clock. Creating register for signal `\Registers.\register28' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10770' with positive edge clock. Creating register for signal `\Registers.\register29' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10771' with positive edge clock. Creating register for signal `\Registers.\register30' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10772' with positive edge clock. Creating register for signal `\Registers.\register31' using process `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. created $dff cell `$procdff$10773' with positive edge clock. Creating register for signal `\PC.\PC_Register' using process `\PC.$proc$Pequeno-Risco-5/src/pc.v:18$6192'. created $dff cell `$procdff$10774' with positive edge clock. Creating register for signal `\Data_Memory.\i' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10775' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10776' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10777' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10778' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10779' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10780' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10781' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10782' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10783' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10784' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10785' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10786' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10787' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10788' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10789' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10790' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10791' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10792' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10793' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10794' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10795' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10796' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10797' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10798' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10799' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10800' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10801' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10802' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10803' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10804' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10805' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10806' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10807' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10808' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10809' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10810' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10811' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10812' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10813' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10814' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10815' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10816' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10817' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10818' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10819' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10820' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10821' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10822' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10823' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10824' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10825' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10826' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10827' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10828' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10829' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10830' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10831' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10832' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10833' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10834' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10835' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10836' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10837' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10838' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10839' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10840' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10841' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10842' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10843' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10844' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10845' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10846' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10847' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10848' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10849' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10850' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10851' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10852' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10853' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10854' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10855' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10856' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10857' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10858' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10859' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10860' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10861' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10862' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10863' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10864' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10865' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10866' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10867' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10868' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10869' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10870' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10871' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10872' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10873' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10874' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10875' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10876' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10877' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10878' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10879' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10880' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10881' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10882' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10883' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10884' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10885' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10886' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10887' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10888' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10889' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10890' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10891' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10892' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10893' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10894' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10895' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10896' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10897' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10898' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10899' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10900' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10901' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10902' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10903' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10904' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10905' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10906' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10907' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10908' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10909' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10910' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10911' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10912' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10913' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10914' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10915' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10916' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10917' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10918' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10919' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10920' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10921' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10922' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10923' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10924' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10925' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10926' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10927' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10928' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10929' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10930' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10931' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10932' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10933' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10934' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10935' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10936' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10937' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10938' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10939' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10940' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10941' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10942' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10943' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10944' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10945' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10946' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10947' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10948' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10949' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10950' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10951' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10952' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10953' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10954' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10955' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10956' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10957' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10958' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10959' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10960' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10961' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10962' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10963' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10964' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10965' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10966' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10967' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10968' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10969' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10970' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10971' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10972' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10973' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10974' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10975' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10976' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10977' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10978' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10979' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10980' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10981' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10982' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10983' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10984' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10985' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10986' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10987' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10988' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10989' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10990' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10991' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10992' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10993' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10994' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10995' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10996' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10997' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10998' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$10999' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11000' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11001' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11002' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11003' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11004' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11005' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11006' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11007' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11008' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11009' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11010' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11011' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11012' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11013' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11014' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11015' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11016' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11017' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11018' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11019' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11020' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11021' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11022' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11023' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11024' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11025' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11026' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11027' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11028' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11029' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11030' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11031' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11032' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11033' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11034' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11035' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11036' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11037' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11038' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11039' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11040' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11041' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11042' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11043' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11044' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11045' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11046' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11047' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11048' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11049' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11050' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11051' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11052' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11053' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11054' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11055' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11056' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11057' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11058' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11059' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11060' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11061' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11062' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11063' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11064' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11065' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11066' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11067' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11068' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11069' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11070' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11071' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11072' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11073' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11074' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11075' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11076' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11077' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11078' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11079' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11080' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11081' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11082' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11083' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11084' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11085' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11086' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11087' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11088' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11089' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11090' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11091' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11092' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11093' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11094' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11095' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11096' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11097' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11098' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11099' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11100' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11101' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11102' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11103' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11104' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11105' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11106' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11107' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11108' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11109' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11110' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11111' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11112' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11113' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11114' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11115' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11116' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11117' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11118' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11119' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11120' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11121' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11122' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11123' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11124' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11125' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11126' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11127' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11128' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11129' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11130' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11131' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11132' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11133' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11134' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11135' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11136' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11137' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11138' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11139' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11140' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11141' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11142' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11143' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11144' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11145' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11146' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11147' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11148' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11149' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11150' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11151' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11152' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11153' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11154' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11155' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11156' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11157' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11158' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11159' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11160' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11161' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11162' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11163' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11164' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11165' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11166' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11167' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11168' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11169' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11170' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11171' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11172' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11173' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11174' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11175' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11176' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11177' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11178' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11179' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11180' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11181' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11182' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11183' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11184' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11185' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11186' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11187' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11188' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11189' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11190' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11191' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11192' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11193' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11194' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11195' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11196' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11197' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11198' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11199' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11200' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11201' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11202' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11203' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11204' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11205' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11206' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11207' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11208' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11209' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11210' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11211' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11212' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11213' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11214' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11215' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11216' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11217' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11218' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11219' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11220' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11221' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11222' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11223' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11224' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11225' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11226' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11227' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11228' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11229' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11230' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11231' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11232' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11233' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11234' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11235' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11236' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11237' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11238' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11239' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11240' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11241' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11242' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11243' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11244' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11245' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11246' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11247' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11248' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11249' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11250' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11251' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11252' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11253' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11254' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11255' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11256' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11257' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11258' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11259' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11260' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11261' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11262' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11263' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11264' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11265' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11266' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11267' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11268' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11269' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11270' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11271' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11272' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11273' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11274' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11275' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11276' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11277' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11278' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11279' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11280' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11281' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11282' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11283' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11284' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11285' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11286' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11287' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11288' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11289' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11290' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11291' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11292' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11293' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11294' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11295' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11296' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11297' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11298' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11299' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11300' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11301' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11302' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11303' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11304' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11305' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11306' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11307' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11308' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11309' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11310' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11311' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11312' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11313' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11314' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11315' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11316' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11317' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11318' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11319' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11320' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11321' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11322' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11323' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11324' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11325' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11326' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11327' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11328' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11329' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11330' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11331' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11332' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11333' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11334' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11335' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11336' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11337' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11338' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11339' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11340' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11341' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11342' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11343' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11344' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11345' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11346' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11347' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11348' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11349' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11350' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11351' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11352' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11353' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11354' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11355' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11356' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11357' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11358' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11359' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11360' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11361' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11362' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11363' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11364' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11365' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11366' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11367' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11368' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11369' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11370' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11371' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11372' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11373' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11374' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11375' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11376' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11377' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11378' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11379' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11380' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11381' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11382' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11383' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11384' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11385' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11386' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11387' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11388' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11389' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11390' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11391' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11392' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11393' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11394' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11395' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11396' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11397' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11398' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11399' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11400' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11401' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11402' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11403' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11404' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11405' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11406' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11407' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11408' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11409' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11410' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11411' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11412' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11413' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11414' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11415' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11416' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11417' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11418' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11419' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11420' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11421' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11422' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11423' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11424' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11425' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11426' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11427' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11428' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11429' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11430' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11431' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11432' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11433' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11434' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11435' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11436' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11437' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11438' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11439' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11440' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11441' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11442' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11443' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11444' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11445' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11446' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11447' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11448' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11449' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11450' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11451' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11452' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11453' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11454' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11455' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11456' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11457' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11458' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11459' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11460' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11461' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11462' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11463' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11464' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11465' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11466' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11467' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11468' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11469' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11470' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11471' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11472' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11473' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11474' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11475' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11476' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11477' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11478' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11479' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11480' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11481' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11482' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11483' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11484' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11485' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11486' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11487' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11488' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11489' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11490' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11491' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11492' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11493' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11494' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11495' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11496' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11497' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11498' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11499' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11500' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11501' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11502' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11503' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11504' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11505' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11506' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11507' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11508' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11509' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11510' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11511' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11512' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11513' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11514' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11515' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11516' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11517' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11518' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11519' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11520' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11521' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11522' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11523' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11524' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11525' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11526' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11527' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11528' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11529' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11530' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11531' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11532' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11533' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11534' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11535' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11536' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11537' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11538' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11539' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11540' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11541' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11542' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11543' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11544' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11545' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11546' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11547' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11548' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11549' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11550' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11551' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11552' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11553' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11554' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11555' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11556' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11557' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11558' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11559' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11560' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11561' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11562' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11563' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11564' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11565' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11566' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11567' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11568' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11569' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11570' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11571' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11572' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11573' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11574' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11575' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11576' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11577' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11578' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11579' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11580' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11581' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11582' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11583' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11584' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11585' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11586' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11587' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11588' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11589' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11590' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11591' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11592' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11593' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11594' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11595' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11596' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11597' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11598' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11599' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11600' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11601' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11602' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11603' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11604' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11605' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11606' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11607' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11608' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11609' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11610' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11611' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11612' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11613' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11614' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11615' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11616' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11617' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11618' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11619' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11620' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11621' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11622' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11623' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11624' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11625' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11626' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11627' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11628' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11629' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11630' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11631' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11632' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11633' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11634' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11635' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11636' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11637' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11638' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11639' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11640' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11641' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11642' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11643' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11644' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11645' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11646' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11647' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11648' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11649' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11650' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11651' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11652' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11653' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11654' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11655' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11656' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11657' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11658' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11659' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11660' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11661' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11662' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11663' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11664' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11665' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11666' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11667' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11668' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11669' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11670' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11671' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11672' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11673' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11674' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11675' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11676' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11677' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11678' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11679' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11680' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11681' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11682' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11683' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11684' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11685' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11686' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11687' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11688' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11689' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11690' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11691' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11692' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11693' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11694' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11695' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11696' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11697' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11698' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11699' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11700' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11701' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11702' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11703' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11704' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11705' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11706' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11707' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11708' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11709' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11710' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11711' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11712' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11713' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11714' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11715' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11716' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11717' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11718' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11719' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11720' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11721' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11722' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11723' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11724' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11725' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11726' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11727' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11728' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11729' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11730' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11731' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11732' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11733' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11734' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11735' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11736' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11737' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11738' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11739' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11740' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11741' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11742' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11743' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11744' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11745' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11746' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11747' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11748' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11749' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11750' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11751' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11752' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11753' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11754' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11755' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11756' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11757' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11758' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11759' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11760' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11761' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11762' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11763' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11764' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11765' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11766' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11767' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11768' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11769' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11770' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11771' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11772' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11773' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11774' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11775' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11776' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11777' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11778' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11779' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11780' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11781' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11782' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11783' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11784' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11785' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11786' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11787' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11788' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11789' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11790' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11791' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11792' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11793' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11794' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11795' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11796' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11797' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11798' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_ADDR' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11799' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_DATA' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11800' with positive edge clock. Creating register for signal `\Data_Memory.$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN' using process `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. created $dff cell `$procdff$11801' with positive edge clock. 12.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 12.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6428'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$6427'. Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$6427'. Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6402'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$6379'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$6345'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$6321'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$6320'. Removing empty process `Registers.$proc$Pequeno-Risco-5/src/registers.v:0$6203'. Found and cleaned up 3 empty switches in `\Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. Removing empty process `Registers.$proc$Pequeno-Risco-5/src/registers.v:158$6199'. Found and cleaned up 2 empty switches in `\Registers.$proc$Pequeno-Risco-5/src/registers.v:82$6198'. Removing empty process `Registers.$proc$Pequeno-Risco-5/src/registers.v:82$6198'. Removing empty process `PC.$proc$Pequeno-Risco-5/src/pc.v:0$6197'. Found and cleaned up 3 empty switches in `\PC.$proc$Pequeno-Risco-5/src/pc.v:18$6192'. Removing empty process `PC.$proc$Pequeno-Risco-5/src/pc.v:18$6192'. Found and cleaned up 1 empty switch in `\Immediate_Generator.$proc$Pequeno-Risco-5/src/immediate_generator.v:10$6187'. Removing empty process `Immediate_Generator.$proc$Pequeno-Risco-5/src/immediate_generator.v:10$6187'. Removing empty process `Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:0$5163'. Found and cleaned up 2 empty switches in `\Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. Removing empty process `Data_Memory.$proc$Pequeno-Risco-5/src/data_memory.v:26$2082'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Pequeno-Risco-5/src/control_unit.v:12$23'. Removing empty process `Control_Unit.$proc$Pequeno-Risco-5/src/control_unit.v:12$23'. Found and cleaned up 6 empty switches in `\ALU_Control.$proc$Pequeno-Risco-5/src/alu_control.v:13$19'. Removing empty process `ALU_Control.$proc$Pequeno-Risco-5/src/alu_control.v:13$19'. Found and cleaned up 1 empty switch in `\ALU.$proc$Pequeno-Risco-5/src/alu.v:14$4'. Removing empty process `ALU.$proc$Pequeno-Risco-5/src/alu.v:14$4'. Cleaned up 23 empty switches. 12.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module Registers. <suppressed ~5 debug messages> Optimizing module PC. <suppressed ~3 debug messages> Optimizing module MUX. <suppressed ~1 debug messages> Optimizing module $paramod$ea5ab62c4b9e74a8fc4617fff9c3041a495e653f\Instruction_Memory. Optimizing module Immediate_Generator. Optimizing module Data_Memory. <suppressed ~3 debug messages> Optimizing module $paramod$8187afbf33560b800064823d5dcb03d397aac8aa\Core. <suppressed ~4 debug messages> Optimizing module Control_Unit. <suppressed ~56 debug messages> Optimizing module ALU_Control. <suppressed ~2 debug messages> Optimizing module ALU. <suppressed ~1 debug messages> Optimizing module top. 12.5. Executing FLATTEN pass (flatten design). Deleting now unused module Registers. Deleting now unused module PC. Deleting now unused module MUX. Deleting now unused module $paramod$ea5ab62c4b9e74a8fc4617fff9c3041a495e653f\Instruction_Memory. Deleting now unused module Immediate_Generator. Deleting now unused module Data_Memory. Deleting now unused module $paramod$8187afbf33560b800064823d5dcb03d397aac8aa\Core. Deleting now unused module Control_Unit. Deleting now unused module ALU_Control. Deleting now unused module ALU. <suppressed ~11 debug messages> 12.6. Executing TRIBUF pass. 12.7. Executing DEMINOUT pass (demote inout ports to input or output). 12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1 debug messages> 12.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1038 unused cells and 6425 unused wires. <suppressed ~1045 debug messages> 12.10. Executing CHECK pass (checking for obvious problems). Checking module top... Warning: Wire top.\tx is used but has no driver. Found and reported 1 problems. 12.11. Executing OPT pass (performing simple optimizations). 12.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~276 debug messages> Removed a total of 92 cells. 12.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\Core.\Alu_Control.$procmux$10458. dead port 2/2 on $mux $flatten\Core.\Alu_Control.$procmux$10460. dead port 2/2 on $mux $flatten\Core.\Alu_Control.$procmux$10472. dead port 1/2 on $mux $flatten\Core.\Alu_Control.$procmux$10429. dead port 1/2 on $mux $flatten\Core.\Alu_Control.$procmux$10432. dead port 2/2 on $mux $flatten\Core.\Alu_Control.$procmux$10442. dead port 1/2 on $mux $flatten\Core.\Alu_Control.$procmux$10445. dead port 1/2 on $mux $flatten\Core.\Alu_Control.$procmux$10451. dead port 1/2 on $mux $flatten\Core.\Data_memory.$procmux$7272. dead port 1/2 on $mux $flatten\Core.\Data_memory.$procmux$7278. dead port 1/2 on $mux $flatten\Core.\Data_memory.$procmux$7284. dead port 2/2 on $mux $flatten\Core.\PC.$procmux$7249. Removed 12 multiplexer ports. <suppressed ~1073 debug messages> 12.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\Core.\Alu_Control.$procmux$10463: { $flatten\Core.\Alu_Control.$procmux$10471_CMP $flatten\Core.\Alu_Control.$procmux$10470_CMP $auto$opt_reduce.cc:134:opt_pmux$12838 $flatten\Core.\Alu_Control.$procmux$10467_CMP $flatten\Core.\Alu_Control.$procmux$10459_CMP $flatten\Core.\Alu_Control.$procmux$10465_CMP $flatten\Core.\Alu_Control.$procmux$10464_CMP } New ctrl vector for $pmux cell $flatten\Core.\Alu_Control.$procmux$10436: { $auto$opt_reduce.cc:134:opt_pmux$12842 $auto$opt_reduce.cc:134:opt_pmux$12840 $flatten\Core.\Alu_Control.$procmux$10437_CMP } New ctrl vector for $pmux cell $flatten\Core.\Control_unit.$procmux$10368: { $auto$opt_reduce.cc:134:opt_pmux$12844 $flatten\Core.\Alu_Control.$eq$Pequeno-Risco-5/src/alu_control.v:40$22_Y } New ctrl vector for $pmux cell $flatten\Core.\Control_unit.$procmux$10375: $flatten\Core.\Alu_Control.$eq$Pequeno-Risco-5/src/alu_control.v:40$22_Y New ctrl vector for $pmux cell $flatten\Core.\Control_unit.$procmux$10382: $flatten\Core.\Control_unit.$procmux$10370_CMP New ctrl vector for $pmux cell $flatten\Core.\Control_unit.$procmux$10389: $flatten\Core.\Control_unit.$procmux$10371_CMP New ctrl vector for $pmux cell $flatten\Core.\Control_unit.$procmux$10396: $auto$opt_reduce.cc:134:opt_pmux$12846 New ctrl vector for $pmux cell $flatten\Core.\Control_unit.$procmux$10403: $flatten\Core.\Control_unit.$procmux$10371_CMP New ctrl vector for $pmux cell $flatten\Core.\Control_unit.$procmux$10410: $auto$opt_reduce.cc:134:opt_pmux$12848 New ctrl vector for $pmux cell $flatten\Core.\Alu_Control.$procmux$10417: { $auto$opt_reduce.cc:134:opt_pmux$12854 $flatten\Core.\Alu_Control.$procmux$10425_CMP $flatten\Core.\Alu_Control.$procmux$10424_CMP $flatten\Core.\Alu_Control.$procmux$10423_CMP $auto$opt_reduce.cc:134:opt_pmux$12852 $auto$opt_reduce.cc:134:opt_pmux$12850 $flatten\Core.\Alu_Control.$procmux$10418_CMP } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10002: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1173_EN[31:0]$2201 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10005: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1172_EN[31:0]$2200 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10008: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1171_EN[31:0]$2199 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10011: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1170_EN[31:0]$2198 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10014: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1169_EN[31:0]$2197 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10017: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1168_EN[31:0]$2196 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10020: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1167_EN[31:0]$2195 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10023: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1166_EN[31:0]$2194 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10026: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1165_EN[31:0]$2193 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10029: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1164_EN[31:0]$2192 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10032: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1163_EN[31:0]$2191 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10035: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1162_EN[31:0]$2190 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10038: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1161_EN[31:0]$2189 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10041: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1160_EN[31:0]$2188 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10044: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1159_EN[31:0]$2187 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10047: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1158_EN[31:0]$2186 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10050: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1157_EN[31:0]$2185 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10053: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1156_EN[31:0]$2184 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10056: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1155_EN[31:0]$2183 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10059: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1154_EN[31:0]$2182 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10062: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1153_EN[31:0]$2181 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10065: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1152_EN[31:0]$2180 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10068: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1151_EN[31:0]$2179 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10071: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1150_EN[31:0]$2178 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10074: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1149_EN[31:0]$2177 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10077: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1148_EN[31:0]$2176 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10080: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1147_EN[31:0]$2175 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10083: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1146_EN[31:0]$2174 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10086: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1145_EN[31:0]$2173 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10089: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1144_EN[31:0]$2172 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10092: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1143_EN[31:0]$2171 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10095: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1142_EN[31:0]$2170 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10098: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1141_EN[31:0]$2169 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10101: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1140_EN[31:0]$2168 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10104: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1139_EN[31:0]$2167 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10107: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1138_EN[31:0]$2166 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10110: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1137_EN[31:0]$2165 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10113: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1136_EN[31:0]$2164 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10116: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1135_EN[31:0]$2163 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10119: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1134_EN[31:0]$2162 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10122: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1133_EN[31:0]$2161 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10125: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1132_EN[31:0]$2160 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10128: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1131_EN[31:0]$2159 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10131: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1130_EN[31:0]$2158 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10134: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1129_EN[31:0]$2157 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10137: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1128_EN[31:0]$2156 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10140: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1127_EN[31:0]$2155 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10143: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1126_EN[31:0]$2154 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10146: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1125_EN[31:0]$2153 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10149: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1124_EN[31:0]$2152 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10152: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1123_EN[31:0]$2151 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10155: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1122_EN[31:0]$2150 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10158: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1121_EN[31:0]$2149 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10161: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1120_EN[31:0]$2148 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10164: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1119_EN[31:0]$2147 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10167: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1118_EN[31:0]$2146 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10170: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1117_EN[31:0]$2145 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10173: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1116_EN[31:0]$2144 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10176: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1115_EN[31:0]$2143 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10179: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1114_EN[31:0]$2142 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10182: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1113_EN[31:0]$2141 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10185: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1112_EN[31:0]$2140 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10188: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1111_EN[31:0]$2139 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10191: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1110_EN[31:0]$2138 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10194: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1109_EN[31:0]$2137 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10197: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1108_EN[31:0]$2136 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10200: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1107_EN[31:0]$2135 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10203: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1106_EN[31:0]$2134 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10206: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1105_EN[31:0]$2133 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10209: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1104_EN[31:0]$2132 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10212: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1103_EN[31:0]$2131 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10215: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1102_EN[31:0]$2130 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10218: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1101_EN[31:0]$2129 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10221: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1100_EN[31:0]$2128 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10224: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1099_EN[31:0]$2127 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10227: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1098_EN[31:0]$2126 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10230: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1097_EN[31:0]$2125 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10233: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1096_EN[31:0]$2124 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10236: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1095_EN[31:0]$2123 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10239: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1094_EN[31:0]$2122 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10242: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1093_EN[31:0]$2121 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10245: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1092_EN[31:0]$2120 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10248: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1091_EN[31:0]$2119 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10251: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1090_EN[31:0]$2118 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10254: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1089_EN[31:0]$2117 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10257: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1088_EN[31:0]$2116 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10260: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1087_EN[31:0]$2115 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10263: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1086_EN[31:0]$2114 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10266: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1085_EN[31:0]$2113 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10269: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1084_EN[31:0]$2112 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10272: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1083_EN[31:0]$2111 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10275: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1082_EN[31:0]$2110 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10278: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1081_EN[31:0]$2109 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10281: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1080_EN[31:0]$2108 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10284: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1079_EN[31:0]$2107 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10287: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1078_EN[31:0]$2106 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10290: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1077_EN[31:0]$2105 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10293: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1076_EN[31:0]$2104 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10296: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1075_EN[31:0]$2103 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10299: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1074_EN[31:0]$2102 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10302: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1073_EN[31:0]$2101 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10305: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1072_EN[31:0]$2100 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10308: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1071_EN[31:0]$2099 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10311: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1070_EN[31:0]$2098 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10314: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1069_EN[31:0]$2097 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10317: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1068_EN[31:0]$2096 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10320: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1067_EN[31:0]$2095 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10323: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1066_EN[31:0]$2094 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10326: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1065_EN[31:0]$2093 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10329: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1064_EN[31:0]$2092 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10332: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1063_EN[31:0]$2091 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10335: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1062_EN[31:0]$2090 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10338: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1061_EN[31:0]$2089 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10341: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1060_EN[31:0]$2088 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10344: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1059_EN[31:0]$2087 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10347: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1058_EN[31:0]$2086 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10350: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1057_EN[31:0]$2085 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10353: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1056_EN[31:0]$2084 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10356: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1055_EN[31:0]$2083 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7269: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$procmux$7269_Y New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$procmux$7269_Y [0] New connections: $flatten\Core.\Data_memory.$procmux$7269_Y [31:1] = { $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] $flatten\Core.\Data_memory.$procmux$7269_Y [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7290: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2077_EN[31:0]$3105 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7293: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2076_EN[31:0]$3104 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7296: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2075_EN[31:0]$3103 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7299: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2074_EN[31:0]$3102 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7302: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2073_EN[31:0]$3101 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7305: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2072_EN[31:0]$3100 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7308: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2071_EN[31:0]$3099 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7311: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2070_EN[31:0]$3098 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7314: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2069_EN[31:0]$3097 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7317: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2068_EN[31:0]$3096 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7320: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2067_EN[31:0]$3095 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7323: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2066_EN[31:0]$3094 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7326: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2065_EN[31:0]$3093 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7329: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2064_EN[31:0]$3092 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7332: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2063_EN[31:0]$3091 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7335: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2062_EN[31:0]$3090 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7338: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2061_EN[31:0]$3089 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7341: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2060_EN[31:0]$3088 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7344: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2059_EN[31:0]$3087 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7347: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2058_EN[31:0]$3086 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7350: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2057_EN[31:0]$3085 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7353: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2056_EN[31:0]$3084 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7356: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2055_EN[31:0]$3083 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7359: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2054_EN[31:0]$3082 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7362: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2053_EN[31:0]$3081 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7365: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2052_EN[31:0]$3080 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7368: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2051_EN[31:0]$3079 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7371: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2050_EN[31:0]$3078 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7374: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2049_EN[31:0]$3077 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7377: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2048_EN[31:0]$3076 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7380: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2047_EN[31:0]$3075 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7383: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2046_EN[31:0]$3074 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7386: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2045_EN[31:0]$3073 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7389: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2044_EN[31:0]$3072 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7392: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2043_EN[31:0]$3071 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7395: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2042_EN[31:0]$3070 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7398: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2041_EN[31:0]$3069 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7401: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2040_EN[31:0]$3068 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7404: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2039_EN[31:0]$3067 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7407: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2038_EN[31:0]$3066 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7410: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2037_EN[31:0]$3065 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7413: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2036_EN[31:0]$3064 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7416: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2035_EN[31:0]$3063 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7419: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2034_EN[31:0]$3062 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7422: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2033_EN[31:0]$3061 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7425: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2032_EN[31:0]$3060 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7428: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2031_EN[31:0]$3059 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7431: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2030_EN[31:0]$3058 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7434: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2029_EN[31:0]$3057 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7437: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2028_EN[31:0]$3056 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7440: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2027_EN[31:0]$3055 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7443: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2026_EN[31:0]$3054 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7446: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2025_EN[31:0]$3053 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7449: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2024_EN[31:0]$3052 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7452: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2023_EN[31:0]$3051 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7455: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2022_EN[31:0]$3050 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7458: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2021_EN[31:0]$3049 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7461: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2020_EN[31:0]$3048 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7464: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2019_EN[31:0]$3047 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7467: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2018_EN[31:0]$3046 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7470: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2017_EN[31:0]$3045 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7473: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2016_EN[31:0]$3044 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7476: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2015_EN[31:0]$3043 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7479: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2014_EN[31:0]$3042 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7482: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2013_EN[31:0]$3041 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7485: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2012_EN[31:0]$3040 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7488: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2011_EN[31:0]$3039 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7491: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2010_EN[31:0]$3038 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7494: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2009_EN[31:0]$3037 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7497: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2008_EN[31:0]$3036 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7500: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2007_EN[31:0]$3035 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7503: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2006_EN[31:0]$3034 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7506: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2005_EN[31:0]$3033 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7509: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2004_EN[31:0]$3032 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7512: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2003_EN[31:0]$3031 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7515: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2002_EN[31:0]$3030 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7518: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2001_EN[31:0]$3029 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7521: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$2000_EN[31:0]$3028 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7524: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1999_EN[31:0]$3027 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7527: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1998_EN[31:0]$3026 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7530: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1997_EN[31:0]$3025 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7533: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1996_EN[31:0]$3024 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7536: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1995_EN[31:0]$3023 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7539: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1994_EN[31:0]$3022 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7542: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1993_EN[31:0]$3021 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7545: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1992_EN[31:0]$3020 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7548: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1991_EN[31:0]$3019 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7551: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1990_EN[31:0]$3018 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7554: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1989_EN[31:0]$3017 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7557: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1988_EN[31:0]$3016 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7560: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1987_EN[31:0]$3015 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7563: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1986_EN[31:0]$3014 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7566: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1985_EN[31:0]$3013 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7569: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1984_EN[31:0]$3012 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7572: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1983_EN[31:0]$3011 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7575: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1982_EN[31:0]$3010 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7578: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1981_EN[31:0]$3009 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7581: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1980_EN[31:0]$3008 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7584: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1979_EN[31:0]$3007 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7587: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1978_EN[31:0]$3006 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7590: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1977_EN[31:0]$3005 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7593: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1976_EN[31:0]$3004 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7596: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1975_EN[31:0]$3003 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7599: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1974_EN[31:0]$3002 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7602: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1973_EN[31:0]$3001 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7605: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1972_EN[31:0]$3000 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7608: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1971_EN[31:0]$2999 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7611: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1970_EN[31:0]$2998 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7614: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1969_EN[31:0]$2997 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7617: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1968_EN[31:0]$2996 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7620: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1967_EN[31:0]$2995 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7623: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1966_EN[31:0]$2994 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7626: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1965_EN[31:0]$2993 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7629: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1964_EN[31:0]$2992 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7632: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1963_EN[31:0]$2991 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7635: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1962_EN[31:0]$2990 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7638: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1961_EN[31:0]$2989 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7641: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1960_EN[31:0]$2988 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7644: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1959_EN[31:0]$2987 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7647: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1958_EN[31:0]$2986 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7650: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1957_EN[31:0]$2985 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7653: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1956_EN[31:0]$2984 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7656: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1955_EN[31:0]$2983 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7659: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1954_EN[31:0]$2982 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7662: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1953_EN[31:0]$2981 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7665: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1952_EN[31:0]$2980 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7668: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1951_EN[31:0]$2979 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7671: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1950_EN[31:0]$2978 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7674: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1949_EN[31:0]$2977 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7677: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1948_EN[31:0]$2976 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7680: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1947_EN[31:0]$2975 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7683: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1946_EN[31:0]$2974 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7686: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1945_EN[31:0]$2973 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7689: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1944_EN[31:0]$2972 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7692: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1943_EN[31:0]$2971 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7695: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1942_EN[31:0]$2970 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7698: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1941_EN[31:0]$2969 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7701: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1940_EN[31:0]$2968 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7704: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1939_EN[31:0]$2967 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7707: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1938_EN[31:0]$2966 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7710: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1937_EN[31:0]$2965 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7713: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1936_EN[31:0]$2964 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7716: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1935_EN[31:0]$2963 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7719: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1934_EN[31:0]$2962 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7722: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1933_EN[31:0]$2961 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7725: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1932_EN[31:0]$2960 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7728: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1931_EN[31:0]$2959 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7731: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1930_EN[31:0]$2958 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7734: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1929_EN[31:0]$2957 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7737: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1928_EN[31:0]$2956 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7740: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1927_EN[31:0]$2955 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7743: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1926_EN[31:0]$2954 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7746: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1925_EN[31:0]$2953 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7749: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1924_EN[31:0]$2952 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7752: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1923_EN[31:0]$2951 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7755: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1922_EN[31:0]$2950 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7758: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1921_EN[31:0]$2949 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7761: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1920_EN[31:0]$2948 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7764: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1919_EN[31:0]$2947 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7767: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1918_EN[31:0]$2946 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7770: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1917_EN[31:0]$2945 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7773: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1916_EN[31:0]$2944 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7776: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1915_EN[31:0]$2943 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7779: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1914_EN[31:0]$2942 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7782: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1913_EN[31:0]$2941 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7785: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1912_EN[31:0]$2940 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7788: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1911_EN[31:0]$2939 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7791: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1910_EN[31:0]$2938 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7794: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1909_EN[31:0]$2937 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7797: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1908_EN[31:0]$2936 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7800: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1907_EN[31:0]$2935 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7803: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1906_EN[31:0]$2934 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7806: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1905_EN[31:0]$2933 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7809: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1904_EN[31:0]$2932 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7812: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1903_EN[31:0]$2931 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7815: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1902_EN[31:0]$2930 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7818: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1901_EN[31:0]$2929 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7821: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1900_EN[31:0]$2928 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7824: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1899_EN[31:0]$2927 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7827: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1898_EN[31:0]$2926 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7830: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1897_EN[31:0]$2925 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7833: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1896_EN[31:0]$2924 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7836: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1895_EN[31:0]$2923 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7839: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1894_EN[31:0]$2922 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7842: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1893_EN[31:0]$2921 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7845: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1892_EN[31:0]$2920 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7848: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1891_EN[31:0]$2919 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7851: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1890_EN[31:0]$2918 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7854: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1889_EN[31:0]$2917 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7857: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1888_EN[31:0]$2916 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7860: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1887_EN[31:0]$2915 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7863: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1886_EN[31:0]$2914 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7866: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1885_EN[31:0]$2913 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7869: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1884_EN[31:0]$2912 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7872: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1883_EN[31:0]$2911 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7875: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1882_EN[31:0]$2910 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7878: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1881_EN[31:0]$2909 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7881: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1880_EN[31:0]$2908 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7884: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1879_EN[31:0]$2907 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7887: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1878_EN[31:0]$2906 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7890: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1877_EN[31:0]$2905 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7893: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1876_EN[31:0]$2904 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7896: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1875_EN[31:0]$2903 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7899: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1874_EN[31:0]$2902 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7902: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1873_EN[31:0]$2901 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7905: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1872_EN[31:0]$2900 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7908: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1871_EN[31:0]$2899 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7911: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1870_EN[31:0]$2898 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7914: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1869_EN[31:0]$2897 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7917: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1868_EN[31:0]$2896 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7920: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1867_EN[31:0]$2895 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7923: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1866_EN[31:0]$2894 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7926: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1865_EN[31:0]$2893 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7929: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1864_EN[31:0]$2892 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7932: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1863_EN[31:0]$2891 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7935: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1862_EN[31:0]$2890 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7938: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1861_EN[31:0]$2889 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7941: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1860_EN[31:0]$2888 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7944: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1859_EN[31:0]$2887 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7947: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1858_EN[31:0]$2886 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7950: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1857_EN[31:0]$2885 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7953: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1856_EN[31:0]$2884 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7956: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1855_EN[31:0]$2883 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7959: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1854_EN[31:0]$2882 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7962: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1853_EN[31:0]$2881 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7965: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1852_EN[31:0]$2880 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7968: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1851_EN[31:0]$2879 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7971: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1850_EN[31:0]$2878 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7974: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1849_EN[31:0]$2877 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7977: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1848_EN[31:0]$2876 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7980: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1847_EN[31:0]$2875 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7983: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1846_EN[31:0]$2874 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7986: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1845_EN[31:0]$2873 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7989: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1844_EN[31:0]$2872 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7992: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1843_EN[31:0]$2871 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7995: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1842_EN[31:0]$2870 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$7998: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1841_EN[31:0]$2869 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8001: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1840_EN[31:0]$2868 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8004: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1839_EN[31:0]$2867 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8007: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1838_EN[31:0]$2866 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8010: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1837_EN[31:0]$2865 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8013: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1836_EN[31:0]$2864 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8016: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1835_EN[31:0]$2863 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8019: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1834_EN[31:0]$2862 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8022: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1833_EN[31:0]$2861 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8025: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1832_EN[31:0]$2860 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8028: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1831_EN[31:0]$2859 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8031: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1830_EN[31:0]$2858 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8034: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1829_EN[31:0]$2857 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8037: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1828_EN[31:0]$2856 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8040: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1827_EN[31:0]$2855 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8043: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1826_EN[31:0]$2854 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8046: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1825_EN[31:0]$2853 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8049: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1824_EN[31:0]$2852 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8052: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1823_EN[31:0]$2851 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8055: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1822_EN[31:0]$2850 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8058: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1821_EN[31:0]$2849 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8061: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1820_EN[31:0]$2848 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8064: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1819_EN[31:0]$2847 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8067: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1818_EN[31:0]$2846 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8070: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1817_EN[31:0]$2845 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8073: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1816_EN[31:0]$2844 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8076: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1815_EN[31:0]$2843 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8079: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1814_EN[31:0]$2842 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8082: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1813_EN[31:0]$2841 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8085: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1812_EN[31:0]$2840 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8088: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1811_EN[31:0]$2839 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8091: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1810_EN[31:0]$2838 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8094: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1809_EN[31:0]$2837 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8097: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1808_EN[31:0]$2836 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8100: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1807_EN[31:0]$2835 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8103: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1806_EN[31:0]$2834 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8106: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1805_EN[31:0]$2833 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8109: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1804_EN[31:0]$2832 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8112: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1803_EN[31:0]$2831 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8115: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1802_EN[31:0]$2830 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8118: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1801_EN[31:0]$2829 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8121: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1800_EN[31:0]$2828 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8124: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1799_EN[31:0]$2827 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8127: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1798_EN[31:0]$2826 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8130: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1797_EN[31:0]$2825 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8133: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1796_EN[31:0]$2824 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8136: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1795_EN[31:0]$2823 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8139: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1794_EN[31:0]$2822 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8142: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1793_EN[31:0]$2821 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8145: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1792_EN[31:0]$2820 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8148: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1791_EN[31:0]$2819 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8151: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1790_EN[31:0]$2818 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8154: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1789_EN[31:0]$2817 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8157: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1788_EN[31:0]$2816 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8160: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1787_EN[31:0]$2815 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8163: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1786_EN[31:0]$2814 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8166: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1785_EN[31:0]$2813 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8169: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1784_EN[31:0]$2812 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8172: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1783_EN[31:0]$2811 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8175: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1782_EN[31:0]$2810 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8178: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1781_EN[31:0]$2809 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8181: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1780_EN[31:0]$2808 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8184: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1779_EN[31:0]$2807 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8187: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1778_EN[31:0]$2806 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8190: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1777_EN[31:0]$2805 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8193: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1776_EN[31:0]$2804 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8196: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1775_EN[31:0]$2803 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8199: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1774_EN[31:0]$2802 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8202: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1773_EN[31:0]$2801 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8205: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1772_EN[31:0]$2800 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8208: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1771_EN[31:0]$2799 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8211: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1770_EN[31:0]$2798 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8214: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1769_EN[31:0]$2797 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8217: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1768_EN[31:0]$2796 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8220: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1767_EN[31:0]$2795 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8223: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1766_EN[31:0]$2794 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8226: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1765_EN[31:0]$2793 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8229: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1764_EN[31:0]$2792 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8232: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1763_EN[31:0]$2791 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8235: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1762_EN[31:0]$2790 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8238: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1761_EN[31:0]$2789 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8241: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1760_EN[31:0]$2788 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8244: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1759_EN[31:0]$2787 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8247: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1758_EN[31:0]$2786 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8250: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1757_EN[31:0]$2785 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8253: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1756_EN[31:0]$2784 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8256: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1755_EN[31:0]$2783 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8259: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1754_EN[31:0]$2782 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8262: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1753_EN[31:0]$2781 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8265: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1752_EN[31:0]$2780 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8268: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1751_EN[31:0]$2779 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8271: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1750_EN[31:0]$2778 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8274: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1749_EN[31:0]$2777 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8277: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1748_EN[31:0]$2776 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8280: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1747_EN[31:0]$2775 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8283: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1746_EN[31:0]$2774 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8286: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1745_EN[31:0]$2773 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8289: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1744_EN[31:0]$2772 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8292: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1743_EN[31:0]$2771 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8295: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1742_EN[31:0]$2770 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8298: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1741_EN[31:0]$2769 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8301: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1740_EN[31:0]$2768 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8304: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1739_EN[31:0]$2767 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8307: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1738_EN[31:0]$2766 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8310: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1737_EN[31:0]$2765 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8313: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1736_EN[31:0]$2764 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8316: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1735_EN[31:0]$2763 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8319: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1734_EN[31:0]$2762 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8322: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1733_EN[31:0]$2761 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8325: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1732_EN[31:0]$2760 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8328: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1731_EN[31:0]$2759 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8331: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1730_EN[31:0]$2758 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8334: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1729_EN[31:0]$2757 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8337: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1728_EN[31:0]$2756 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8340: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1727_EN[31:0]$2755 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8343: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1726_EN[31:0]$2754 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8346: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1725_EN[31:0]$2753 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8349: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1724_EN[31:0]$2752 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8352: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1723_EN[31:0]$2751 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8355: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1722_EN[31:0]$2750 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8358: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1721_EN[31:0]$2749 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8361: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1720_EN[31:0]$2748 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8364: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1719_EN[31:0]$2747 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8367: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1718_EN[31:0]$2746 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8370: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1717_EN[31:0]$2745 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8373: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1716_EN[31:0]$2744 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8376: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1715_EN[31:0]$2743 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8379: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1714_EN[31:0]$2742 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8382: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1713_EN[31:0]$2741 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8385: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1712_EN[31:0]$2740 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8388: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1711_EN[31:0]$2739 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8391: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1710_EN[31:0]$2738 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8394: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1709_EN[31:0]$2737 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8397: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1708_EN[31:0]$2736 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8400: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1707_EN[31:0]$2735 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8403: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1706_EN[31:0]$2734 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8406: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1705_EN[31:0]$2733 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8409: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1704_EN[31:0]$2732 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8412: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1703_EN[31:0]$2731 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8415: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1702_EN[31:0]$2730 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8418: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1701_EN[31:0]$2729 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8421: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1700_EN[31:0]$2728 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8424: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1699_EN[31:0]$2727 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8427: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1698_EN[31:0]$2726 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8430: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1697_EN[31:0]$2725 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8433: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1696_EN[31:0]$2724 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8436: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1695_EN[31:0]$2723 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8439: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1694_EN[31:0]$2722 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8442: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1693_EN[31:0]$2721 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8445: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1692_EN[31:0]$2720 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8448: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1691_EN[31:0]$2719 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8451: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1690_EN[31:0]$2718 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8454: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1689_EN[31:0]$2717 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8457: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1688_EN[31:0]$2716 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8460: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1687_EN[31:0]$2715 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8463: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1686_EN[31:0]$2714 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8466: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1685_EN[31:0]$2713 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8469: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1684_EN[31:0]$2712 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8472: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1683_EN[31:0]$2711 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8475: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1682_EN[31:0]$2710 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8478: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1681_EN[31:0]$2709 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8481: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1680_EN[31:0]$2708 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8484: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1679_EN[31:0]$2707 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8487: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1678_EN[31:0]$2706 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8490: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1677_EN[31:0]$2705 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8493: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1676_EN[31:0]$2704 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8496: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1675_EN[31:0]$2703 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8499: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1674_EN[31:0]$2702 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8502: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1673_EN[31:0]$2701 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8505: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1672_EN[31:0]$2700 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8508: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1671_EN[31:0]$2699 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8511: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1670_EN[31:0]$2698 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8514: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1669_EN[31:0]$2697 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8517: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1668_EN[31:0]$2696 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8520: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1667_EN[31:0]$2695 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8523: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1666_EN[31:0]$2694 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8526: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1665_EN[31:0]$2693 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8529: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1664_EN[31:0]$2692 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8532: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1663_EN[31:0]$2691 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8535: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1662_EN[31:0]$2690 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8538: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1661_EN[31:0]$2689 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8541: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1660_EN[31:0]$2688 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8544: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1659_EN[31:0]$2687 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8547: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1658_EN[31:0]$2686 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8550: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1657_EN[31:0]$2685 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8553: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1656_EN[31:0]$2684 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8556: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1655_EN[31:0]$2683 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8559: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1654_EN[31:0]$2682 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8562: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1653_EN[31:0]$2681 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8565: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1652_EN[31:0]$2680 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8568: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1651_EN[31:0]$2679 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8571: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1650_EN[31:0]$2678 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8574: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1649_EN[31:0]$2677 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8577: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1648_EN[31:0]$2676 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8580: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1647_EN[31:0]$2675 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8583: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1646_EN[31:0]$2674 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8586: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1645_EN[31:0]$2673 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8589: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1644_EN[31:0]$2672 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8592: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1643_EN[31:0]$2671 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8595: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1642_EN[31:0]$2670 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8598: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1641_EN[31:0]$2669 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8601: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1640_EN[31:0]$2668 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8604: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1639_EN[31:0]$2667 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8607: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1638_EN[31:0]$2666 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8610: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1637_EN[31:0]$2665 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8613: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1636_EN[31:0]$2664 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8616: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1635_EN[31:0]$2663 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8619: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1634_EN[31:0]$2662 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8622: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1633_EN[31:0]$2661 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8625: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1632_EN[31:0]$2660 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8628: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1631_EN[31:0]$2659 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8631: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1630_EN[31:0]$2658 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8634: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1629_EN[31:0]$2657 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8637: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1628_EN[31:0]$2656 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8640: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1627_EN[31:0]$2655 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8643: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1626_EN[31:0]$2654 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8646: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1625_EN[31:0]$2653 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8649: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1624_EN[31:0]$2652 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8652: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1623_EN[31:0]$2651 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8655: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1622_EN[31:0]$2650 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8658: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1621_EN[31:0]$2649 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8661: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1620_EN[31:0]$2648 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8664: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1619_EN[31:0]$2647 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8667: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1618_EN[31:0]$2646 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8670: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1617_EN[31:0]$2645 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8673: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1616_EN[31:0]$2644 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8676: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1615_EN[31:0]$2643 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8679: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1614_EN[31:0]$2642 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8682: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1613_EN[31:0]$2641 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8685: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1612_EN[31:0]$2640 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8688: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1611_EN[31:0]$2639 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8691: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1610_EN[31:0]$2638 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8694: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1609_EN[31:0]$2637 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8697: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1608_EN[31:0]$2636 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8700: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1607_EN[31:0]$2635 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8703: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1606_EN[31:0]$2634 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8706: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1605_EN[31:0]$2633 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8709: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1604_EN[31:0]$2632 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8712: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1603_EN[31:0]$2631 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8715: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1602_EN[31:0]$2630 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8718: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1601_EN[31:0]$2629 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8721: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1600_EN[31:0]$2628 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8724: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1599_EN[31:0]$2627 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8727: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1598_EN[31:0]$2626 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8730: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1597_EN[31:0]$2625 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8733: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1596_EN[31:0]$2624 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8736: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1595_EN[31:0]$2623 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8739: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1594_EN[31:0]$2622 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8742: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1593_EN[31:0]$2621 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8745: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1592_EN[31:0]$2620 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8748: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1591_EN[31:0]$2619 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8751: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1590_EN[31:0]$2618 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8754: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1589_EN[31:0]$2617 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8757: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1588_EN[31:0]$2616 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8760: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1587_EN[31:0]$2615 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8763: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1586_EN[31:0]$2614 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8766: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1585_EN[31:0]$2613 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8769: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1584_EN[31:0]$2612 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8772: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1583_EN[31:0]$2611 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8775: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1582_EN[31:0]$2610 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8778: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1581_EN[31:0]$2609 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8781: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1580_EN[31:0]$2608 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8784: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1579_EN[31:0]$2607 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8787: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1578_EN[31:0]$2606 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8790: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1577_EN[31:0]$2605 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8793: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1576_EN[31:0]$2604 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8796: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1575_EN[31:0]$2603 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8799: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1574_EN[31:0]$2602 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8802: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1573_EN[31:0]$2601 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8805: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1572_EN[31:0]$2600 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8808: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1571_EN[31:0]$2599 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8811: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1570_EN[31:0]$2598 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8814: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1569_EN[31:0]$2597 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8817: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1568_EN[31:0]$2596 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8820: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1567_EN[31:0]$2595 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8823: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1566_EN[31:0]$2594 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8826: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1565_EN[31:0]$2593 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8829: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1564_EN[31:0]$2592 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8832: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1563_EN[31:0]$2591 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8835: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1562_EN[31:0]$2590 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8838: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1561_EN[31:0]$2589 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8841: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1560_EN[31:0]$2588 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8844: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1559_EN[31:0]$2587 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8847: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1558_EN[31:0]$2586 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8850: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1557_EN[31:0]$2585 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8853: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1556_EN[31:0]$2584 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8856: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1555_EN[31:0]$2583 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8859: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1554_EN[31:0]$2582 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8862: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1553_EN[31:0]$2581 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8865: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1552_EN[31:0]$2580 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8868: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1551_EN[31:0]$2579 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8871: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1550_EN[31:0]$2578 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8874: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1549_EN[31:0]$2577 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8877: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1548_EN[31:0]$2576 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8880: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1547_EN[31:0]$2575 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8883: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1546_EN[31:0]$2574 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8886: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1545_EN[31:0]$2573 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8889: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1544_EN[31:0]$2572 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8892: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1543_EN[31:0]$2571 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8895: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1542_EN[31:0]$2570 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8898: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1541_EN[31:0]$2569 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8901: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1540_EN[31:0]$2568 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8904: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1539_EN[31:0]$2567 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8907: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1538_EN[31:0]$2566 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8910: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1537_EN[31:0]$2565 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8913: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1536_EN[31:0]$2564 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8916: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1535_EN[31:0]$2563 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8919: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1534_EN[31:0]$2562 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8922: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1533_EN[31:0]$2561 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8925: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1532_EN[31:0]$2560 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8928: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1531_EN[31:0]$2559 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8931: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1530_EN[31:0]$2558 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8934: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1529_EN[31:0]$2557 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8937: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1528_EN[31:0]$2556 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8940: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1527_EN[31:0]$2555 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8943: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1526_EN[31:0]$2554 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8946: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1525_EN[31:0]$2553 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8949: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1524_EN[31:0]$2552 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8952: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1523_EN[31:0]$2551 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8955: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1522_EN[31:0]$2550 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8958: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1521_EN[31:0]$2549 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8961: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1520_EN[31:0]$2548 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8964: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1519_EN[31:0]$2547 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8967: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1518_EN[31:0]$2546 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8970: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1517_EN[31:0]$2545 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8973: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1516_EN[31:0]$2544 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8976: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1515_EN[31:0]$2543 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8979: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1514_EN[31:0]$2542 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8982: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1513_EN[31:0]$2541 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8985: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1512_EN[31:0]$2540 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8988: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1511_EN[31:0]$2539 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8991: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1510_EN[31:0]$2538 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8994: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1509_EN[31:0]$2537 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$8997: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1508_EN[31:0]$2536 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9000: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1507_EN[31:0]$2535 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9003: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1506_EN[31:0]$2534 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9006: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1505_EN[31:0]$2533 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9009: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1504_EN[31:0]$2532 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9012: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1503_EN[31:0]$2531 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9015: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1502_EN[31:0]$2530 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9018: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1501_EN[31:0]$2529 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9021: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1500_EN[31:0]$2528 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9024: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1499_EN[31:0]$2527 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9027: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1498_EN[31:0]$2526 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9030: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1497_EN[31:0]$2525 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9033: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1496_EN[31:0]$2524 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9036: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1495_EN[31:0]$2523 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9039: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1494_EN[31:0]$2522 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9042: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1493_EN[31:0]$2521 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9045: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1492_EN[31:0]$2520 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9048: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1491_EN[31:0]$2519 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9051: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1490_EN[31:0]$2518 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9054: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1489_EN[31:0]$2517 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9057: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1488_EN[31:0]$2516 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9060: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1487_EN[31:0]$2515 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9063: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1486_EN[31:0]$2514 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9066: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1485_EN[31:0]$2513 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9069: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1484_EN[31:0]$2512 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9072: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1483_EN[31:0]$2511 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9075: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1482_EN[31:0]$2510 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9078: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1481_EN[31:0]$2509 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9081: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1480_EN[31:0]$2508 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9084: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1479_EN[31:0]$2507 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9087: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1478_EN[31:0]$2506 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9090: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1477_EN[31:0]$2505 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9093: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1476_EN[31:0]$2504 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9096: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1475_EN[31:0]$2503 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9099: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1474_EN[31:0]$2502 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9102: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1473_EN[31:0]$2501 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9105: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1472_EN[31:0]$2500 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9108: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1471_EN[31:0]$2499 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9111: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1470_EN[31:0]$2498 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9114: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1469_EN[31:0]$2497 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9117: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1468_EN[31:0]$2496 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9120: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1467_EN[31:0]$2495 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9123: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1466_EN[31:0]$2494 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9126: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1465_EN[31:0]$2493 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9129: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1464_EN[31:0]$2492 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9132: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1463_EN[31:0]$2491 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9135: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1462_EN[31:0]$2490 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9138: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1461_EN[31:0]$2489 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9141: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1460_EN[31:0]$2488 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9144: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1459_EN[31:0]$2487 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9147: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1458_EN[31:0]$2486 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9150: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1457_EN[31:0]$2485 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9153: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1456_EN[31:0]$2484 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9156: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1455_EN[31:0]$2483 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9159: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1454_EN[31:0]$2482 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9162: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1453_EN[31:0]$2481 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9165: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1452_EN[31:0]$2480 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9168: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1451_EN[31:0]$2479 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9171: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1450_EN[31:0]$2478 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9174: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1449_EN[31:0]$2477 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9177: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1448_EN[31:0]$2476 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9180: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1447_EN[31:0]$2475 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9183: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1446_EN[31:0]$2474 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9186: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1445_EN[31:0]$2473 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9189: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1444_EN[31:0]$2472 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9192: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1443_EN[31:0]$2471 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9195: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1442_EN[31:0]$2470 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9198: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1441_EN[31:0]$2469 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9201: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1440_EN[31:0]$2468 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9204: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1439_EN[31:0]$2467 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9207: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1438_EN[31:0]$2466 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9210: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1437_EN[31:0]$2465 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9213: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1436_EN[31:0]$2464 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9216: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1435_EN[31:0]$2463 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9219: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1434_EN[31:0]$2462 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9222: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1433_EN[31:0]$2461 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9225: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1432_EN[31:0]$2460 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9228: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1431_EN[31:0]$2459 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9231: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1430_EN[31:0]$2458 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9234: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1429_EN[31:0]$2457 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9237: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1428_EN[31:0]$2456 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9240: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1427_EN[31:0]$2455 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9243: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1426_EN[31:0]$2454 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9246: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1425_EN[31:0]$2453 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9249: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1424_EN[31:0]$2452 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9252: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1423_EN[31:0]$2451 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9255: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1422_EN[31:0]$2450 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9258: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1421_EN[31:0]$2449 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9261: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1420_EN[31:0]$2448 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9264: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1419_EN[31:0]$2447 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9267: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1418_EN[31:0]$2446 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9270: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1417_EN[31:0]$2445 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9273: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1416_EN[31:0]$2444 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9276: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1415_EN[31:0]$2443 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9279: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1414_EN[31:0]$2442 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9282: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1413_EN[31:0]$2441 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9285: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1412_EN[31:0]$2440 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9288: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1411_EN[31:0]$2439 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9291: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1410_EN[31:0]$2438 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9294: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1409_EN[31:0]$2437 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9297: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1408_EN[31:0]$2436 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9300: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1407_EN[31:0]$2435 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9303: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1406_EN[31:0]$2434 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9306: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1405_EN[31:0]$2433 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9309: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1404_EN[31:0]$2432 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9312: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1403_EN[31:0]$2431 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9315: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1402_EN[31:0]$2430 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9318: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1401_EN[31:0]$2429 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9321: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1400_EN[31:0]$2428 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9324: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1399_EN[31:0]$2427 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9327: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1398_EN[31:0]$2426 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9330: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1397_EN[31:0]$2425 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9333: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1396_EN[31:0]$2424 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9336: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1395_EN[31:0]$2423 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9339: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1394_EN[31:0]$2422 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9342: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1393_EN[31:0]$2421 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9345: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1392_EN[31:0]$2420 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9348: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1391_EN[31:0]$2419 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9351: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1390_EN[31:0]$2418 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9354: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1389_EN[31:0]$2417 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9357: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1388_EN[31:0]$2416 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9360: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1387_EN[31:0]$2415 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9363: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1386_EN[31:0]$2414 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9366: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1385_EN[31:0]$2413 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9369: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1384_EN[31:0]$2412 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9372: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1383_EN[31:0]$2411 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9375: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1382_EN[31:0]$2410 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9378: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1381_EN[31:0]$2409 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9381: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1380_EN[31:0]$2408 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9384: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1379_EN[31:0]$2407 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9387: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1378_EN[31:0]$2406 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9390: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1377_EN[31:0]$2405 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9393: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1376_EN[31:0]$2404 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9396: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1375_EN[31:0]$2403 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9399: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1374_EN[31:0]$2402 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9402: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1373_EN[31:0]$2401 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9405: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1372_EN[31:0]$2400 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9408: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1371_EN[31:0]$2399 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9411: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1370_EN[31:0]$2398 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9414: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1369_EN[31:0]$2397 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9417: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1368_EN[31:0]$2396 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9420: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1367_EN[31:0]$2395 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9423: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1366_EN[31:0]$2394 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9426: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1365_EN[31:0]$2393 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9429: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1364_EN[31:0]$2392 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9432: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1363_EN[31:0]$2391 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9435: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1362_EN[31:0]$2390 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9438: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1361_EN[31:0]$2389 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9441: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1360_EN[31:0]$2388 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9444: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1359_EN[31:0]$2387 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9447: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1358_EN[31:0]$2386 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9450: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1357_EN[31:0]$2385 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9453: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1356_EN[31:0]$2384 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9456: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1355_EN[31:0]$2383 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9459: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1354_EN[31:0]$2382 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9462: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1353_EN[31:0]$2381 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9465: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1352_EN[31:0]$2380 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9468: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1351_EN[31:0]$2379 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9471: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1350_EN[31:0]$2378 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9474: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1349_EN[31:0]$2377 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9477: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1348_EN[31:0]$2376 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9480: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1347_EN[31:0]$2375 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9483: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1346_EN[31:0]$2374 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9486: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1345_EN[31:0]$2373 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9489: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1344_EN[31:0]$2372 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9492: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1343_EN[31:0]$2371 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9495: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1342_EN[31:0]$2370 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9498: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1341_EN[31:0]$2369 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9501: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1340_EN[31:0]$2368 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9504: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1339_EN[31:0]$2367 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9507: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1338_EN[31:0]$2366 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9510: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1337_EN[31:0]$2365 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9513: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1336_EN[31:0]$2364 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9516: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1335_EN[31:0]$2363 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9519: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1334_EN[31:0]$2362 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9522: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1333_EN[31:0]$2361 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9525: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1332_EN[31:0]$2360 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9528: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1331_EN[31:0]$2359 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9531: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1330_EN[31:0]$2358 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9534: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1329_EN[31:0]$2357 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9537: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1328_EN[31:0]$2356 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9540: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1327_EN[31:0]$2355 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9543: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1326_EN[31:0]$2354 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9546: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1325_EN[31:0]$2353 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9549: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1324_EN[31:0]$2352 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9552: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1323_EN[31:0]$2351 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9555: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1322_EN[31:0]$2350 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9558: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1321_EN[31:0]$2349 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9561: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1320_EN[31:0]$2348 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9564: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1319_EN[31:0]$2347 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9567: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1318_EN[31:0]$2346 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9570: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1317_EN[31:0]$2345 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9573: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1316_EN[31:0]$2344 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9576: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1315_EN[31:0]$2343 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9579: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1314_EN[31:0]$2342 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9582: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1313_EN[31:0]$2341 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9585: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1312_EN[31:0]$2340 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9588: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1311_EN[31:0]$2339 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9591: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1310_EN[31:0]$2338 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9594: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1309_EN[31:0]$2337 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9597: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1308_EN[31:0]$2336 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9600: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1307_EN[31:0]$2335 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9603: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1306_EN[31:0]$2334 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9606: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1305_EN[31:0]$2333 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9609: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1304_EN[31:0]$2332 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9612: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1303_EN[31:0]$2331 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9615: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1302_EN[31:0]$2330 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9618: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1301_EN[31:0]$2329 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9621: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1300_EN[31:0]$2328 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9624: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1299_EN[31:0]$2327 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9627: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1298_EN[31:0]$2326 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9630: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1297_EN[31:0]$2325 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9633: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1296_EN[31:0]$2324 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9636: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1295_EN[31:0]$2323 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9639: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1294_EN[31:0]$2322 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9642: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1293_EN[31:0]$2321 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9645: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1292_EN[31:0]$2320 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9648: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1291_EN[31:0]$2319 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9651: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1290_EN[31:0]$2318 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9654: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1289_EN[31:0]$2317 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9657: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1288_EN[31:0]$2316 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9660: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1287_EN[31:0]$2315 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9663: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1286_EN[31:0]$2314 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9666: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1285_EN[31:0]$2313 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9669: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1284_EN[31:0]$2312 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9672: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1283_EN[31:0]$2311 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9675: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1282_EN[31:0]$2310 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9678: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1281_EN[31:0]$2309 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9681: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1280_EN[31:0]$2308 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9684: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1279_EN[31:0]$2307 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9687: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1278_EN[31:0]$2306 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9690: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1277_EN[31:0]$2305 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9693: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1276_EN[31:0]$2304 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9696: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1275_EN[31:0]$2303 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9699: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1274_EN[31:0]$2302 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9702: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1273_EN[31:0]$2301 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9705: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1272_EN[31:0]$2300 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9708: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1271_EN[31:0]$2299 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9711: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1270_EN[31:0]$2298 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9714: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1269_EN[31:0]$2297 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9717: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1268_EN[31:0]$2296 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9720: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1267_EN[31:0]$2295 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9723: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1266_EN[31:0]$2294 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9726: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1265_EN[31:0]$2293 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9729: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1264_EN[31:0]$2292 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9732: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1263_EN[31:0]$2291 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9735: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1262_EN[31:0]$2290 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9738: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1261_EN[31:0]$2289 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9741: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1260_EN[31:0]$2288 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9744: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1259_EN[31:0]$2287 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9747: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1258_EN[31:0]$2286 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9750: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1257_EN[31:0]$2285 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9753: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1256_EN[31:0]$2284 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9756: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1255_EN[31:0]$2283 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9759: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1254_EN[31:0]$2282 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9762: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1253_EN[31:0]$2281 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9765: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1252_EN[31:0]$2280 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9768: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1251_EN[31:0]$2279 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9771: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1250_EN[31:0]$2278 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9774: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1249_EN[31:0]$2277 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9777: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1248_EN[31:0]$2276 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9780: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1247_EN[31:0]$2275 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9783: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1246_EN[31:0]$2274 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9786: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1245_EN[31:0]$2273 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9789: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1244_EN[31:0]$2272 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9792: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1243_EN[31:0]$2271 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9795: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1242_EN[31:0]$2270 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9798: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1241_EN[31:0]$2269 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9801: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1240_EN[31:0]$2268 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9804: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1239_EN[31:0]$2267 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9807: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1238_EN[31:0]$2266 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9810: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1237_EN[31:0]$2265 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9813: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1236_EN[31:0]$2264 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9816: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1235_EN[31:0]$2263 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9819: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1234_EN[31:0]$2262 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9822: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1233_EN[31:0]$2261 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9825: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1232_EN[31:0]$2260 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9828: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1231_EN[31:0]$2259 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9831: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1230_EN[31:0]$2258 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9834: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1229_EN[31:0]$2257 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9837: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1228_EN[31:0]$2256 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9840: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1227_EN[31:0]$2255 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9843: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1226_EN[31:0]$2254 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9846: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1225_EN[31:0]$2253 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9849: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1224_EN[31:0]$2252 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9852: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1223_EN[31:0]$2251 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9855: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1222_EN[31:0]$2250 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9858: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1221_EN[31:0]$2249 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9861: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1220_EN[31:0]$2248 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9864: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1219_EN[31:0]$2247 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9867: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1218_EN[31:0]$2246 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9870: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1217_EN[31:0]$2245 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9873: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1216_EN[31:0]$2244 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9876: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1215_EN[31:0]$2243 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9879: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1214_EN[31:0]$2242 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9882: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1213_EN[31:0]$2241 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9885: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1212_EN[31:0]$2240 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9888: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1211_EN[31:0]$2239 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9891: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1210_EN[31:0]$2238 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9894: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1209_EN[31:0]$2237 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9897: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1208_EN[31:0]$2236 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9900: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1207_EN[31:0]$2235 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9903: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1206_EN[31:0]$2234 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9906: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1205_EN[31:0]$2233 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9909: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1204_EN[31:0]$2232 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9912: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1203_EN[31:0]$2231 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9915: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1202_EN[31:0]$2230 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9918: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1201_EN[31:0]$2229 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9921: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1200_EN[31:0]$2228 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9924: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1199_EN[31:0]$2227 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9927: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1198_EN[31:0]$2226 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9930: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1197_EN[31:0]$2225 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9933: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1196_EN[31:0]$2224 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9936: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1195_EN[31:0]$2223 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9939: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1194_EN[31:0]$2222 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9942: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1193_EN[31:0]$2221 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9945: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1192_EN[31:0]$2220 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9948: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1191_EN[31:0]$2219 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9951: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1190_EN[31:0]$2218 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9954: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1189_EN[31:0]$2217 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9957: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1188_EN[31:0]$2216 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9960: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1187_EN[31:0]$2215 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9963: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1186_EN[31:0]$2214 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9966: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1185_EN[31:0]$2213 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9969: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1184_EN[31:0]$2212 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9972: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1183_EN[31:0]$2211 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9975: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1182_EN[31:0]$2210 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9978: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1181_EN[31:0]$2209 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9981: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1180_EN[31:0]$2208 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9984: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1179_EN[31:0]$2207 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9987: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1178_EN[31:0]$2206 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9990: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1177_EN[31:0]$2205 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9993: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1176_EN[31:0]$2204 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9996: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1175_EN[31:0]$2203 [0] } Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$9999: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 New ports: A=1'0, B=1'1, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:29$1174_EN[31:0]$2202 [0] } New ctrl vector for $pmux cell $flatten\Core.\Immediate_generator.$procmux$7258: { $flatten\Core.\Alu_Control.$eq$Pequeno-Risco-5/src/alu_control.v:40$22_Y $flatten\Core.\Immediate_generator.$procmux$7266_CMP $auto$opt_reduce.cc:134:opt_pmux$12858 $auto$opt_reduce.cc:134:opt_pmux$12856 $flatten\Core.\Control_unit.$procmux$10370_CMP } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\Core.\Data_memory.$procmux$10359: Old ports: A=$flatten\Core.\Data_memory.$2$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$4139, B=0, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 New ports: A=$flatten\Core.\Data_memory.$procmux$7269_Y [0], B=1'0, Y=$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] New connections: $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [31:1] = { $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] $flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_EN[31:0]$3108 [0] } Optimizing cells in module \top. Performed a total of 1036 changes. 12.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3075 debug messages> Removed a total of 1025 cells. 12.11.6. Executing OPT_DFF pass (perform DFF optimizations). 12.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1128 unused wires. <suppressed ~1 debug messages> 12.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.11.9. Rerunning OPT passes. (Maybe there is more to do..) 12.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\Core.\Data_memory.$ternary$Pequeno-Risco-5/src/data_memory.v:18$2081. Removed 1 multiplexer ports. <suppressed ~50 debug messages> 12.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 12.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.11.13. Executing OPT_DFF pass (perform DFF optimizations). 12.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1 unused wires. <suppressed ~1 debug messages> 12.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.11.16. Rerunning OPT passes. (Maybe there is more to do..) 12.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~50 debug messages> 12.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 12.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.11.20. Executing OPT_DFF pass (perform DFF optimizations). 12.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 12.11.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.11.23. Finished OPT passes. (There is nothing left to do.) 12.12. Executing FSM pass (extract and optimize FSM). 12.12.1. Executing FSM_DETECT pass (finding FSMs in design). 12.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 12.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 12.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 12.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 12.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 12.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 12.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 12.13. Executing OPT pass (performing simple optimizations). 12.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~50 debug messages> 12.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 12.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\Core.\registers.$procdff$10773 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6465_Y, Q = \Core.registers.register31, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12859 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register31). Adding SRST signal on $flatten\Core.\registers.$procdff$10772 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6473_Y, Q = \Core.registers.register30, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12863 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register30). Adding SRST signal on $flatten\Core.\registers.$procdff$10771 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6482_Y, Q = \Core.registers.register29, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12867 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register29). Adding SRST signal on $flatten\Core.\registers.$procdff$10770 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6492_Y, Q = \Core.registers.register28, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12871 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register28). Adding SRST signal on $flatten\Core.\registers.$procdff$10769 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6503_Y, Q = \Core.registers.register27, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12875 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register27). Adding SRST signal on $flatten\Core.\registers.$procdff$10768 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6515_Y, Q = \Core.registers.register26, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12879 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register26). Adding SRST signal on $flatten\Core.\registers.$procdff$10767 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6528_Y, Q = \Core.registers.register25, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12883 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register25). Adding SRST signal on $flatten\Core.\registers.$procdff$10766 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6542_Y, Q = \Core.registers.register24, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12887 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register24). Adding SRST signal on $flatten\Core.\registers.$procdff$10765 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6557_Y, Q = \Core.registers.register23, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12891 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register23). Adding SRST signal on $flatten\Core.\registers.$procdff$10764 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6573_Y, Q = \Core.registers.register22, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12895 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register22). Adding SRST signal on $flatten\Core.\registers.$procdff$10763 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6590_Y, Q = \Core.registers.register21, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12899 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register21). Adding SRST signal on $flatten\Core.\registers.$procdff$10762 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6608_Y, Q = \Core.registers.register20, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12903 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register20). Adding SRST signal on $flatten\Core.\registers.$procdff$10761 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6627_Y, Q = \Core.registers.register19, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12907 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register19). Adding SRST signal on $flatten\Core.\registers.$procdff$10760 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6647_Y, Q = \Core.registers.register18, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12911 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register18). Adding SRST signal on $flatten\Core.\registers.$procdff$10759 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6668_Y, Q = \Core.registers.register17, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12915 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register17). Adding SRST signal on $flatten\Core.\registers.$procdff$10758 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6690_Y, Q = \Core.registers.register16, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12919 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register16). Adding SRST signal on $flatten\Core.\registers.$procdff$10757 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6713_Y, Q = \Core.registers.register15, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12923 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register15). Adding SRST signal on $flatten\Core.\registers.$procdff$10756 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6737_Y, Q = \Core.registers.register14, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12927 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register14). Adding SRST signal on $flatten\Core.\registers.$procdff$10755 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6762_Y, Q = \Core.registers.register13, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12931 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register13). Adding SRST signal on $flatten\Core.\registers.$procdff$10754 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6788_Y, Q = \Core.registers.register12, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12935 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register12). Adding SRST signal on $flatten\Core.\registers.$procdff$10753 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6815_Y, Q = \Core.registers.register11, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12939 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register11). Adding SRST signal on $flatten\Core.\registers.$procdff$10752 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6843_Y, Q = \Core.registers.register10, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12943 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register10). Adding SRST signal on $flatten\Core.\registers.$procdff$10751 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6872_Y, Q = \Core.registers.register9, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12947 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register9). Adding SRST signal on $flatten\Core.\registers.$procdff$10750 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6902_Y, Q = \Core.registers.register8, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12951 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register8). Adding SRST signal on $flatten\Core.\registers.$procdff$10749 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6933_Y, Q = \Core.registers.register7, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12955 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register7). Adding SRST signal on $flatten\Core.\registers.$procdff$10748 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6965_Y, Q = \Core.registers.register6, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12959 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register6). Adding SRST signal on $flatten\Core.\registers.$procdff$10747 ($dff) from module top (D = $flatten\Core.\registers.$procmux$6998_Y, Q = \Core.registers.register5, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12963 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register5). Adding SRST signal on $flatten\Core.\registers.$procdff$10746 ($dff) from module top (D = $flatten\Core.\registers.$procmux$7032_Y, Q = \Core.registers.register4, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12967 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register4). Adding SRST signal on $flatten\Core.\registers.$procdff$10745 ($dff) from module top (D = $flatten\Core.\registers.$procmux$7067_Y, Q = \Core.registers.register3, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12971 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register3). Adding SRST signal on $flatten\Core.\registers.$procdff$10744 ($dff) from module top (D = $flatten\Core.\registers.$procmux$7103_Y, Q = \Core.registers.register2, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12975 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register2). Adding SRST signal on $flatten\Core.\registers.$procdff$10743 ($dff) from module top (D = $flatten\Core.\registers.$procmux$7140_Y, Q = \Core.registers.register1, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12979 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register1). Adding SRST signal on $flatten\Core.\registers.$procdff$10742 ($dff) from module top (D = $flatten\Core.\registers.$procmux$7178_Y, Q = \Core.registers.register0, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$12983 ($sdff) from module top (D = \Core.registers.writeData, Q = \Core.registers.register0). Adding SRST signal on $flatten\Core.\PC.$procdff$10774 ($dff) from module top (D = $flatten\Core.\PC.$procmux$7252_Y, Q = \Core.PC.PC_Register, rval = 0). 12.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 97 unused cells and 97 unused wires. <suppressed ~98 debug messages> 12.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.13.9. Rerunning OPT passes. (Maybe there is more to do..) 12.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~18 debug messages> 12.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 12.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.13.13. Executing OPT_DFF pass (perform DFF optimizations). 12.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 12.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.13.16. Finished OPT passes. (There is nothing left to do.) 12.14. Executing WREDUCE pass (reducing word size of cells). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11802 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11803 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11804 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11805 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11806 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11807 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11808 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11809 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11810 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11811 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11812 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11813 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11814 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11815 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11816 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11817 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11818 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11819 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11820 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11821 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11822 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11823 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11824 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11825 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11826 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11827 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11828 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11829 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11830 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11831 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11832 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11833 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11834 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11835 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11836 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11837 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11838 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11839 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11840 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11841 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11842 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11843 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11844 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11845 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11846 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11847 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11848 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11849 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11850 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11851 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11852 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11853 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11854 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11855 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11856 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11857 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11858 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11859 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11860 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11861 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11862 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11863 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11864 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11865 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11866 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11867 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11868 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11869 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11870 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11871 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11872 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11873 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11874 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11875 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11876 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11877 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11878 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11879 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11880 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11881 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11882 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11883 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11884 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11885 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11886 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11887 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11888 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11889 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11890 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11891 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11892 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11893 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11894 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11895 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11896 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11897 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11898 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11899 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11900 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11901 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11902 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11903 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11904 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11905 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11906 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11907 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11908 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11909 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11910 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11911 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11912 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11913 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11914 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11915 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11916 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11917 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11918 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11919 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11920 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11921 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11922 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11923 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11924 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11925 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11926 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11927 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11928 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11929 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11930 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11931 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11932 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11933 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11934 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11935 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11936 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11937 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11938 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11939 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11940 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11941 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11942 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11943 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11944 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11945 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11946 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11947 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11948 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11949 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11950 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11951 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11952 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11953 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11954 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11955 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11956 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11957 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11958 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11959 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11960 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11961 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11962 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11963 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11964 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11965 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11966 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11967 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11968 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11969 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11970 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11971 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11972 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11973 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11974 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11975 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11976 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11977 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11978 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11979 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11980 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11981 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11982 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11983 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11984 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11985 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11986 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11987 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11988 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11989 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11990 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11991 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11992 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11993 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11994 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11995 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11996 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11997 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11998 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$11999 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12000 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12001 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12002 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12003 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12004 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12005 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12006 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12007 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12008 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12009 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12010 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12011 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12012 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12013 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12014 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12015 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12016 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12017 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12018 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12019 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12020 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12021 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12022 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12023 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12024 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12025 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12026 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12027 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12028 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12029 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12030 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12031 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12032 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12033 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12034 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12035 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12036 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12037 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12038 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12039 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12040 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12041 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12042 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12043 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12044 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12045 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12046 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12047 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12048 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12049 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12050 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12051 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12052 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12053 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12054 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12055 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12056 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12057 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12058 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12059 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12060 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12061 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12062 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12063 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12064 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12065 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12066 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12067 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12068 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12069 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12070 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12071 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12072 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12073 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12074 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12075 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12076 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12077 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12078 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12079 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12080 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12081 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12082 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12083 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12084 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12085 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12086 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12087 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12088 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12089 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12090 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12091 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12092 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12093 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12094 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12095 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12096 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12097 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12098 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12099 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12100 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12101 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12102 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12103 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12104 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12105 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12106 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12107 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12108 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12109 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12110 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12111 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12112 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12113 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12114 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12115 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12116 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12117 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12118 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12119 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12120 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12121 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12122 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12123 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12124 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12125 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12126 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12127 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12128 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12129 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12130 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12131 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12132 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12133 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12134 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12135 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12136 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12137 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12138 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12139 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12140 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12141 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12142 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12143 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12144 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12145 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12146 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12147 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12148 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12149 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12150 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12151 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12152 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12153 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12154 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12155 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12156 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12157 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12158 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12159 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12160 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12161 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12162 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12163 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12164 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12165 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12166 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12167 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12168 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12169 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12170 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12171 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12172 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12173 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12174 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12175 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12176 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12177 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12178 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12179 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12180 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12181 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12182 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12183 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12184 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12185 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12186 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12187 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12188 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12189 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12190 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12191 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12192 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12193 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12194 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12195 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12196 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12197 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12198 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12199 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12200 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12201 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12202 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12203 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12204 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12205 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12206 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12207 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12208 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12209 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12210 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12211 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12212 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12213 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12214 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12215 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12216 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12217 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12218 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12219 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12220 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12221 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12222 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12223 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12224 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12225 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12226 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12227 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12228 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12229 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12230 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12231 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12232 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12233 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12234 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12235 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12236 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12237 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12238 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12239 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12240 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12241 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12242 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12243 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12244 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12245 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12246 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12247 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12248 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12249 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12250 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12251 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12252 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12253 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12254 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12255 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12256 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12257 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12258 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12259 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12260 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12261 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12262 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12263 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12264 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12265 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12266 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12267 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12268 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12269 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12270 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12271 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12272 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12273 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12274 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12275 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12276 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12277 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12278 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12279 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12280 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12281 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12282 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12283 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12284 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12285 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12286 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12287 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12288 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12289 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12290 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12291 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12292 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12293 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12294 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12295 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12296 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12297 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12298 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12299 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12300 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12301 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12302 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12303 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12304 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12305 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12306 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12307 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12308 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12309 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12310 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12311 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12312 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12313 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12314 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12315 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12316 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12317 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12318 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12319 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12320 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12321 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12322 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12323 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12324 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12325 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12326 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12327 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12328 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12329 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12330 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12331 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12332 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12333 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12334 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12335 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12336 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12337 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12338 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12339 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12340 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12341 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12342 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12343 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12344 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12345 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12346 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12347 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12348 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12349 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12350 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12351 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12352 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12353 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12354 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12355 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12356 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12357 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12358 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12359 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12360 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12361 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12362 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12363 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12364 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12365 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12366 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12367 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12368 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12369 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12370 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12371 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12372 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12373 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12374 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12375 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12376 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12377 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12378 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12379 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12380 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12381 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12382 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12383 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12384 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12385 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12386 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12387 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12388 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12389 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12390 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12391 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12392 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12393 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12394 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12395 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12396 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12397 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12398 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12399 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12400 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12401 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12402 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12403 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12404 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12405 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12406 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12407 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12408 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12409 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12410 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12411 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12412 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12413 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12414 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12415 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12416 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12417 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12418 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12419 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12420 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12421 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12422 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12423 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12424 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12425 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12426 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12427 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12428 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12429 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12430 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12431 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12432 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12433 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12434 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12435 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12436 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12437 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12438 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12439 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12440 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12441 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12442 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12443 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12444 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12445 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12446 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12447 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12448 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12449 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12450 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12451 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12452 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12453 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12454 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12455 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12456 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12457 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12458 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12459 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12460 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12461 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12462 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12463 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12464 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12465 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12466 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12467 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12468 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12469 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12470 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12471 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12472 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12473 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12474 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12475 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12476 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12477 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12478 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12479 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12480 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12481 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12482 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12483 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12484 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12485 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12486 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12487 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12488 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12489 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12490 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12491 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12492 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12493 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12494 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12495 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12496 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12497 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12498 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12499 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12500 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12501 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12502 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12503 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12504 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12505 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12506 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12507 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12508 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12509 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12510 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12511 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12512 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12513 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12514 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12515 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12516 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12517 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12518 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12519 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12520 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12521 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12522 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12523 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12524 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12525 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12526 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12527 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12528 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12529 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12530 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12531 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12532 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12533 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12534 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12535 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12536 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12537 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12538 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12539 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12540 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12541 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12542 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12543 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12544 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12545 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12546 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12547 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12548 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12549 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12550 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12551 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12552 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12553 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12554 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12555 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12556 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12557 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12558 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12559 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12560 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12561 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12562 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12563 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12564 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12565 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12566 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12567 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12568 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12569 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12570 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12571 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12572 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12573 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12574 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12575 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12576 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12577 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12578 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12579 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12580 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12581 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12582 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12583 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12584 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12585 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12586 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12587 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12588 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12589 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12590 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12591 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12592 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12593 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12594 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12595 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12596 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12597 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12598 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12599 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12600 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12601 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12602 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12603 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12604 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12605 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12606 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12607 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12608 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12609 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12610 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12611 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12612 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12613 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12614 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12615 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12616 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12617 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12618 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12619 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12620 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12621 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12622 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12623 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12624 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12625 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12626 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12627 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12628 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12629 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12630 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12631 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12632 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12633 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12634 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12635 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12636 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12637 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12638 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12639 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12640 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12641 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12642 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12643 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12644 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12645 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12646 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12647 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12648 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12649 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12650 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12651 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12652 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12653 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12654 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12655 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12656 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12657 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12658 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12659 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12660 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12661 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12662 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12663 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12664 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12665 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12666 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12667 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12668 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12669 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12670 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12671 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12672 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12673 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12674 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12675 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12676 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12677 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12678 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12679 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12680 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12681 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12682 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12683 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12684 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12685 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12686 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12687 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12688 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12689 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12690 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12691 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12692 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12693 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12694 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12695 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12696 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12697 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12698 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12699 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12700 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12701 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12702 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12703 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12704 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12705 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12706 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12707 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12708 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12709 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12710 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12711 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12712 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12713 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12714 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12715 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12716 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12717 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12718 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12719 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12720 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12721 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12722 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12723 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12724 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12725 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12726 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12727 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12728 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12729 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12730 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12731 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12732 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12733 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12734 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12735 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12736 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12737 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12738 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12739 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12740 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12741 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12742 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12743 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12744 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12745 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12746 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12747 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12748 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12749 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12750 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12751 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12752 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12753 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12754 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12755 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12756 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12757 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12758 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12759 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12760 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12761 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12762 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12763 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12764 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12765 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12766 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12767 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12768 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12769 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12770 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12771 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12772 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12773 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12774 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12775 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12776 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12777 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12778 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12779 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12780 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12781 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12782 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12783 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12784 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12785 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12786 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12787 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12788 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12789 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12790 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12791 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12792 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12793 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12794 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12795 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12796 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12797 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12798 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12799 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12800 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12801 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12802 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12803 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12804 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12805 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12806 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12807 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12808 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12809 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12810 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12811 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12812 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12813 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12814 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12815 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12816 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12817 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12818 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12819 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12820 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12821 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12822 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12823 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12824 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$auto$proc_memwr.cc:45:proc_memwr$12825 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4140 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4141 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4142 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4143 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4144 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4145 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4146 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4147 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4148 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4149 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4150 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4151 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4152 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4153 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4154 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4155 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4156 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4157 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4158 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4159 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4160 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4161 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4162 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4163 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4164 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4165 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4166 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4167 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4168 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4169 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4170 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4171 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4172 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4173 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4174 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4175 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4176 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4177 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4178 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4179 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4180 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4181 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4182 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4183 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4184 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4185 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4186 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4187 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4188 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4189 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4190 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4191 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4192 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4193 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4194 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4195 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4196 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4197 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4198 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4199 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4200 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4201 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4202 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4203 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4204 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4205 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4206 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4207 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4208 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4209 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4210 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4211 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4212 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4213 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4214 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4215 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4216 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4217 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4218 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4219 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4220 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4221 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4222 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4223 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4224 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4225 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4226 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4227 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4228 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4229 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4230 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4231 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4232 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4233 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4234 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4235 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4236 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4237 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4238 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4239 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4240 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4241 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4242 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4243 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4244 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4245 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4246 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4247 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4248 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4249 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4250 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4251 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4252 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4253 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4254 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4255 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4256 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4257 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4258 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4259 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4260 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4261 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4262 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4263 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4264 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4265 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4266 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4267 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4268 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4269 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4270 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4271 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4272 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4273 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4274 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4275 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4276 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4277 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4278 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4279 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4280 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4281 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4282 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4283 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4284 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4285 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4286 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4287 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4288 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4289 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4290 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4291 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4292 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4293 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4294 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4295 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4296 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4297 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4298 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4299 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4300 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4301 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4302 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4303 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4304 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4305 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4306 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4307 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4308 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4309 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4310 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4311 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4312 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4313 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4314 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4315 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4316 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4317 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4318 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4319 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4320 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4321 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4322 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4323 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4324 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4325 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4326 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4327 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4328 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4329 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4330 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4331 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4332 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4333 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4334 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4335 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4336 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4337 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4338 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4339 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4340 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4341 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4342 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4343 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4344 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4345 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4346 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4347 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4348 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4349 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4350 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4351 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4352 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4353 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4354 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4355 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4356 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4357 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4358 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4359 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4360 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4361 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4362 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4363 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4364 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4365 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4366 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4367 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4368 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4369 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4370 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4371 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4372 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4373 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4374 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4375 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4376 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4377 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4378 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4379 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4380 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4381 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4382 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4383 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4384 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4385 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4386 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4387 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4388 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4389 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4390 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4391 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4392 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4393 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4394 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4395 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4396 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4397 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4398 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4399 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4400 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4401 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4402 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4403 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4404 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4405 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4406 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4407 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4408 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4409 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4410 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4411 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4412 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4413 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4414 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4415 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4416 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4417 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4418 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4419 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4420 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4421 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4422 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4423 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4424 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4425 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4426 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4427 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4428 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4429 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4430 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4431 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4432 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4433 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4434 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4435 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4436 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4437 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4438 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4439 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4440 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4441 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4442 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4443 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4444 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4445 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4446 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4447 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4448 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4449 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4450 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4451 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4452 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4453 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4454 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4455 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4456 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4457 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4458 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4459 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4460 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4461 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4462 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4463 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4464 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4465 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4466 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4467 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4468 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4469 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4470 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4471 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4472 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4473 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4474 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4475 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4476 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4477 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4478 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4479 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4480 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4481 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4482 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4483 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4484 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4485 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4486 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4487 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4488 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4489 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4490 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4491 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4492 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4493 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4494 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4495 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4496 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4497 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4498 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4499 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4500 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4501 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4502 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4503 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4504 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4505 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4506 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4507 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4508 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4509 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4510 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4511 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4512 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4513 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4514 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4515 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4516 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4517 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4518 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4519 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4520 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4521 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4522 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4523 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4524 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4525 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4526 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4527 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4528 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4529 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4530 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4531 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4532 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4533 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4534 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4535 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4536 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4537 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4538 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4539 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4540 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4541 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4542 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4543 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4544 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4545 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4546 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4547 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4548 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4549 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4550 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4551 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4552 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4553 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4554 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4555 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4556 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4557 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4558 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4559 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4560 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4561 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4562 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4563 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4564 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4565 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4566 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4567 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4568 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4569 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4570 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4571 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4572 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4573 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4574 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4575 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4576 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4577 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4578 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4579 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4580 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4581 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4582 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4583 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4584 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4585 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4586 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4587 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4588 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4589 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4590 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4591 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4592 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4593 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4594 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4595 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4596 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4597 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4598 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4599 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4600 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4601 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4602 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4603 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4604 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4605 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4606 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4607 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4608 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4609 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4610 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4611 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4612 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4613 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4614 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4615 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4616 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4617 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4618 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4619 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4620 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4621 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4622 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4623 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4624 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4625 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4626 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4627 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4628 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4629 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4630 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4631 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4632 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4633 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4634 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4635 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4636 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4637 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4638 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4639 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4640 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4641 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4642 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4643 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4644 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4645 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4646 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4647 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4648 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4649 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4650 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4651 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4652 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4653 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4654 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4655 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4656 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4657 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4658 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4659 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4660 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4661 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4662 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4663 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4664 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4665 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4666 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4667 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4668 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4669 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4670 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4671 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4672 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4673 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4674 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4675 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4676 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4677 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4678 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4679 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4680 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4681 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4682 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4683 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4684 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4685 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4686 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4687 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4688 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4689 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4690 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4691 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4692 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4693 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4694 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4695 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4696 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4697 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4698 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4699 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4700 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4701 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4702 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4703 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4704 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4705 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4706 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4707 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4708 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4709 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4710 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4711 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4712 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4713 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4714 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4715 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4716 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4717 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4718 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4719 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4720 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4721 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4722 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4723 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4724 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4725 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4726 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4727 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4728 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4729 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4730 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4731 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4732 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4733 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4734 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4735 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4736 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4737 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4738 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4739 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4740 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4741 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4742 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4743 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4744 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4745 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4746 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4747 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4748 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4749 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4750 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4751 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4752 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4753 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4754 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4755 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4756 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4757 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4758 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4759 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4760 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4761 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4762 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4763 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4764 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4765 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4766 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4767 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4768 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4769 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4770 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4771 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4772 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4773 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4774 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4775 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4776 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4777 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4778 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4779 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4780 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4781 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4782 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4783 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4784 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4785 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4786 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4787 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4788 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4789 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4790 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4791 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4792 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4793 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4794 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4795 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4796 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4797 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4798 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4799 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4800 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4801 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4802 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4803 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4804 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4805 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4806 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4807 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4808 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4809 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4810 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4811 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4812 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4813 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4814 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4815 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4816 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4817 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4818 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4819 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4820 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4821 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4822 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4823 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4824 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4825 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4826 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4827 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4828 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4829 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4830 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4831 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4832 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4833 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4834 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4835 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4836 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4837 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4838 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4839 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4840 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4841 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4842 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4843 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4844 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4845 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4846 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4847 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4848 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4849 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4850 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4851 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4852 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4853 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4854 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4855 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4856 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4857 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4858 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4859 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4860 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4861 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4862 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4863 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4864 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4865 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4866 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4867 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4868 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4869 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4870 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4871 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4872 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4873 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4874 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4875 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4876 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4877 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4878 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4879 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4880 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4881 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4882 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4883 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4884 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4885 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4886 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4887 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4888 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4889 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4890 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4891 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4892 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4893 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4894 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4895 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4896 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4897 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4898 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4899 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4900 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4901 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4902 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4903 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4904 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4905 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4906 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4907 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4908 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4909 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4910 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4911 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4912 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4913 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4914 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4915 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4916 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4917 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4918 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4919 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4920 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4921 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4922 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4923 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4924 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4925 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4926 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4927 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4928 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4929 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4930 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4931 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4932 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4933 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4934 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4935 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4936 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4937 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4938 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4939 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4940 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4941 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4942 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4943 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4944 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4945 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4946 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4947 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4948 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4949 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4950 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4951 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4952 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4953 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4954 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4955 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4956 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4957 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4958 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4959 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4960 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4961 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4962 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4963 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4964 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4965 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4966 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4967 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4968 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4969 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4970 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4971 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4972 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4973 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4974 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4975 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4976 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4977 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4978 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4979 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4980 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4981 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4982 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4983 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4984 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4985 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4986 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4987 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4988 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4989 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4990 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4991 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4992 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4993 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4994 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4995 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4996 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4997 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4998 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$4999 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5000 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5001 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5002 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5003 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5004 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5005 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5006 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5007 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5008 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5009 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5010 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5011 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5012 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5013 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5014 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5015 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5016 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5017 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5018 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5019 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5020 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5021 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5022 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5023 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5024 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5025 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5026 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5027 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5028 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5029 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5030 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5031 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5032 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5033 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5034 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5035 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5036 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5037 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5038 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5039 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5040 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5041 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5042 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5043 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5044 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5045 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5046 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5047 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5048 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5049 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5050 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5051 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5052 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5053 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5054 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5055 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5056 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5057 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5058 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5059 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5060 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5061 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5062 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5063 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5064 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5065 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5066 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5067 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5068 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5069 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5070 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5071 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5072 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5073 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5074 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5075 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5076 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5077 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5078 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5079 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5080 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5081 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5082 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5083 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5084 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5085 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5086 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5087 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5088 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5089 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5090 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5091 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5092 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5093 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5094 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5095 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5096 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5097 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5098 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5099 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5100 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5101 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5102 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5103 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5104 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5105 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5106 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5107 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5108 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5109 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5110 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5111 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5112 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5113 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5114 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5115 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5116 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5117 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5118 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5119 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5120 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5121 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5122 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5123 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5124 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5125 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5126 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5127 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5128 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5129 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5130 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5131 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5132 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5133 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5134 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5135 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5136 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5137 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5138 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5139 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5140 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5141 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5142 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5143 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5144 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5145 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5146 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5147 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5148 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5149 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5150 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5151 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5152 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5153 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5154 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5155 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5156 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5157 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5158 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5159 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5160 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5161 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory init port top.$flatten\Core.\Data_memory.$meminit$\ram$Pequeno-Risco-5/src/data_memory.v:22$5162 (Core.Data_memory.ram). Removed top 22 address bits (of 32) from memory read port top.$flatten\Core.\Data_memory.$memrd$\ram$Pequeno-Risco-5/src/data_memory.v:18$2080 (Core.Data_memory.ram). Removed top 24 address bits (of 32) from memory init port top.$flatten\Core.\Instruction_memory.$meminit$\memory$Pequeno-Risco-5/src/instruction_memory.v:0$6438 (Core.Instruction_memory.memory). Removed top 24 address bits (of 32) from memory read port top.$flatten\Core.\Instruction_memory.$memrd$\memory$Pequeno-Risco-5/src/instruction_memory.v:14$6437 (Core.Instruction_memory.memory). Removed top 22 bits (of 32) from mux cell top.$flatten\Core.\Data_memory.$procmux$10365 ($mux). Removed top 1 bits (of 7) from port B of cell top.$flatten\Core.\Control_unit.$procmux$10370_CMP0 ($eq). Removed top 5 bits (of 7) from port B of cell top.$flatten\Core.\Control_unit.$procmux$10371_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\Core.\Control_unit.$procmux$10373_CMP0 ($eq). Removed top 1 bits (of 12) from port B of cell top.$flatten\Core.\Alu_Control.$procmux$10427_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\Alu_Control.$procmux$10437_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\Alu_Control.$procmux$10438_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\Alu_Control.$procmux$10439_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\Alu_Control.$procmux$10440_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\Alu_Control.$procmux$10441_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\Core.\Alu_Control.$procmux$10468_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\Core.\Alu_Control.$procmux$10469_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\Core.\Alu_Control.$procmux$10470_CMP0 ($eq). Removed top 31 bits (of 32) from mux cell top.$flatten\Core.\Alu.$ternary$Pequeno-Risco-5/src/alu.v:25$10 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\Core.\Alu.$ternary$Pequeno-Risco-5/src/alu.v:37$18 ($mux). Removed top 1 bits (of 4) from port B of cell top.$flatten\Core.\Alu.$procmux$10485_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\Core.\Alu.$procmux$10486_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\Core.\Alu.$procmux$10487_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\Core.\Alu.$procmux$10488_CMP0 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\Core.\PC.$add$Pequeno-Risco-5/src/pc.v:24$6195 ($add). Removed top 1 bits (of 7) from port B of cell top.$flatten\Core.\Immediate_generator.$procmux$7264_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\Core.\Immediate_generator.$procmux$7265_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$6712_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$6736_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$6761_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$6787_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$6814_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$6842_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$6871_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$6901_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$6932_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$6964_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$6997_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7031_CMP0 ($eq). Removed top 3 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7066_CMP0 ($eq). Removed top 3 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7102_CMP0 ($eq). Removed top 4 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7139_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7200_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7201_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7202_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7203_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7204_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7205_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7206_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7207_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7208_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7209_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7210_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7211_CMP0 ($eq). Removed top 3 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7212_CMP0 ($eq). Removed top 3 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7213_CMP0 ($eq). Removed top 4 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7214_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7233_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7234_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7235_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7236_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7237_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7238_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7239_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7240_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7241_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7242_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7243_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7244_CMP0 ($eq). Removed top 3 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7245_CMP0 ($eq). Removed top 3 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7246_CMP0 ($eq). Removed top 4 bits (of 5) from port B of cell top.$flatten\Core.\registers.$procmux$7247_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\Core.\Alu_Control.$eq$Pequeno-Risco-5/src/alu_control.v:14$20 ($eq). Removed top 1 bits (of 32) from port B of cell top.$flatten\Core.$add$Pequeno-Risco-5/src/core.v:23$6430 ($add). Removed top 22 bits (of 32) from mux cell top.$flatten\Core.\Data_memory.$procmux$7281 ($mux). Removed top 31 bits (of 32) from wire top.$flatten\Core.\Alu.$eq$Pequeno-Risco-5/src/alu.v:35$16_Y. Removed top 31 bits (of 32) from wire top.$flatten\Core.\Alu.$ternary$Pequeno-Risco-5/src/alu.v:25$10_Y. Removed top 31 bits (of 32) from wire top.$flatten\Core.\Alu.$ternary$Pequeno-Risco-5/src/alu.v:37$18_Y. Removed top 22 bits (of 32) from wire top.$flatten\Core.\Data_memory.$0$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_ADDR[31:0]$3106. Removed top 22 bits (of 32) from wire top.$flatten\Core.\Data_memory.$2$memwr$\ram$Pequeno-Risco-5/src/data_memory.v:32$2078_ADDR[31:0]$4137. 12.15. Executing PEEPOPT pass (run peephole optimizers). 12.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 5 unused wires. <suppressed ~1 debug messages> 12.17. Executing SHARE pass (SAT-based resource sharing). Found 3 cells in module top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\Core.\Data_memory.$memrd$\ram$Pequeno-Risco-5/src/data_memory.v:18$2080 ($memrd): Found 1 activation_patterns using ctrl signal \Core.Control_unit.memory_read. No candidates found. Analyzing resource sharing options for $flatten\Core.\Alu.$shr$Pequeno-Risco-5/src/alu.v:31$14 ($shr): Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$10482_CMP. No candidates found. Analyzing resource sharing options for $flatten\Core.\Alu.$shl$Pequeno-Risco-5/src/alu.v:29$13 ($shl): Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$10483_CMP. No candidates found. 12.18. Executing TECHMAP pass (map to technology primitives). 12.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 12.18.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~62 debug messages> 12.19. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 12.21. Executing TECHMAP pass (map to technology primitives). 12.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 12.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 12.21.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 12.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\Core.$add$Pequeno-Risco-5/src/core.v:23$6430 ($add). creating $macc model for $flatten\Core.\Alu.$add$Pequeno-Risco-5/src/alu.v:21$7 ($add). creating $macc model for $flatten\Core.\Alu.$sub$Pequeno-Risco-5/src/alu.v:23$8 ($sub). creating $macc model for $flatten\Core.\PC.$add$Pequeno-Risco-5/src/pc.v:24$6195 ($add). creating $alu model for $macc $flatten\Core.\PC.$add$Pequeno-Risco-5/src/pc.v:24$6195. creating $alu model for $macc $flatten\Core.\Alu.$sub$Pequeno-Risco-5/src/alu.v:23$8. creating $alu model for $macc $flatten\Core.\Alu.$add$Pequeno-Risco-5/src/alu.v:21$7. creating $alu model for $macc $flatten\Core.$add$Pequeno-Risco-5/src/core.v:23$6430. creating $alu model for $flatten\Core.\Alu.$ge$Pequeno-Risco-5/src/alu.v:37$17 ($ge): merged with $flatten\Core.\Alu.$sub$Pequeno-Risco-5/src/alu.v:23$8. creating $alu model for $flatten\Core.\Alu.$lt$Pequeno-Risco-5/src/alu.v:25$9 ($lt): merged with $flatten\Core.\Alu.$sub$Pequeno-Risco-5/src/alu.v:23$8. creating $alu model for $flatten\Core.\Alu.$eq$Pequeno-Risco-5/src/alu.v:35$16 ($eq): merged with $flatten\Core.\Alu.$sub$Pequeno-Risco-5/src/alu.v:23$8. creating $alu cell for $flatten\Core.$add$Pequeno-Risco-5/src/core.v:23$6430: $auto$alumacc.cc:485:replace_alu$12994 creating $alu cell for $flatten\Core.\Alu.$add$Pequeno-Risco-5/src/alu.v:21$7: $auto$alumacc.cc:485:replace_alu$12997 creating $alu cell for $flatten\Core.\Alu.$sub$Pequeno-Risco-5/src/alu.v:23$8, $flatten\Core.\Alu.$ge$Pequeno-Risco-5/src/alu.v:37$17, $flatten\Core.\Alu.$lt$Pequeno-Risco-5/src/alu.v:25$9, $flatten\Core.\Alu.$eq$Pequeno-Risco-5/src/alu.v:35$16: $auto$alumacc.cc:485:replace_alu$13000 creating $alu cell for $flatten\Core.\PC.$add$Pequeno-Risco-5/src/pc.v:24$6195: $auto$alumacc.cc:485:replace_alu$13013 created 4 $alu and 0 $macc cells. 12.23. Executing OPT pass (performing simple optimizations). 12.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1 debug messages> 12.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~18 debug messages> 12.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 12.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.23.6. Executing OPT_DFF pass (perform DFF optimizations). 12.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 3 unused wires. <suppressed ~1 debug messages> 12.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.23.9. Rerunning OPT passes. (Maybe there is more to do..) 12.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~18 debug messages> 12.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 12.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.23.13. Executing OPT_DFF pass (perform DFF optimizations). 12.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 12.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.23.16. Finished OPT passes. (There is nothing left to do.) 12.24. Executing MEMORY pass. 12.24.1. Executing OPT_MEM pass (optimize memories). top.Core.Instruction_memory.memory: removing const-1 lane 0 top.Core.Instruction_memory.memory: removing const-1 lane 1 top.Core.Instruction_memory.memory: removing const-0 lane 2 top.Core.Instruction_memory.memory: removing const-0 lane 3 top.Core.Instruction_memory.memory: removing const-1 lane 4 top.Core.Instruction_memory.memory: removing const-0 lane 5 top.Core.Instruction_memory.memory: removing const-0 lane 6 top.Core.Instruction_memory.memory: removing const-1 lane 8 top.Core.Instruction_memory.memory: removing const-0 lane 11 top.Core.Instruction_memory.memory: removing const-0 lane 13 top.Core.Instruction_memory.memory: removing const-0 lane 14 top.Core.Instruction_memory.memory: removing const-0 lane 15 top.Core.Instruction_memory.memory: removing const-0 lane 17 top.Core.Instruction_memory.memory: removing const-0 lane 18 top.Core.Instruction_memory.memory: removing const-0 lane 19 top.Core.Instruction_memory.memory: removing const-1 lane 20 top.Core.Instruction_memory.memory: removing const-1 lane 23 top.Core.Instruction_memory.memory: removing const-0 lane 31 Performed a total of 1 transformations. 12.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 522753 transformations. 12.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing top.Core.Data_memory.ram write port 0. Analyzing top.Core.Data_memory.ram write port 1. Analyzing top.Core.Data_memory.ram write port 2. Analyzing top.Core.Data_memory.ram write port 3. Analyzing top.Core.Data_memory.ram write port 4. Analyzing top.Core.Data_memory.ram write port 5. Analyzing top.Core.Data_memory.ram write port 6. Analyzing top.Core.Data_memory.ram write port 7. Analyzing top.Core.Data_memory.ram write port 8. Analyzing top.Core.Data_memory.ram write port 9. Analyzing top.Core.Data_memory.ram write port 10. Analyzing top.Core.Data_memory.ram write port 11. Analyzing top.Core.Data_memory.ram write port 12. Analyzing top.Core.Data_memory.ram write port 13. Analyzing top.Core.Data_memory.ram write port 14. Analyzing top.Core.Data_memory.ram write port 15. Analyzing top.Core.Data_memory.ram write port 16. Analyzing top.Core.Data_memory.ram write port 17. Analyzing top.Core.Data_memory.ram write port 18. Analyzing top.Core.Data_memory.ram write port 19. Analyzing top.Core.Data_memory.ram write port 20. Analyzing top.Core.Data_memory.ram write port 21. Analyzing top.Core.Data_memory.ram write port 22. Analyzing top.Core.Data_memory.ram write port 23. Analyzing top.Core.Data_memory.ram write port 24. Analyzing top.Core.Data_memory.ram write port 25. Analyzing top.Core.Data_memory.ram write port 26. Analyzing top.Core.Data_memory.ram write port 27. Analyzing top.Core.Data_memory.ram write port 28. Analyzing top.Core.Data_memory.ram write port 29. Analyzing top.Core.Data_memory.ram write port 30. Analyzing top.Core.Data_memory.ram write port 31. Analyzing top.Core.Data_memory.ram write port 32. Analyzing top.Core.Data_memory.ram write port 33. Analyzing top.Core.Data_memory.ram write port 34. Analyzing top.Core.Data_memory.ram write port 35. Analyzing top.Core.Data_memory.ram write port 36. Analyzing top.Core.Data_memory.ram write port 37. Analyzing top.Core.Data_memory.ram write port 38. Analyzing top.Core.Data_memory.ram write port 39. Analyzing top.Core.Data_memory.ram write port 40. Analyzing top.Core.Data_memory.ram write port 41. Analyzing top.Core.Data_memory.ram write port 42. Analyzing top.Core.Data_memory.ram write port 43. Analyzing top.Core.Data_memory.ram write port 44. Analyzing top.Core.Data_memory.ram write port 45. Analyzing top.Core.Data_memory.ram write port 46. Analyzing top.Core.Data_memory.ram write port 47. Analyzing top.Core.Data_memory.ram write port 48. Analyzing top.Core.Data_memory.ram write port 49. Analyzing top.Core.Data_memory.ram write port 50. Analyzing top.Core.Data_memory.ram write port 51. Analyzing top.Core.Data_memory.ram write port 52. Analyzing top.Core.Data_memory.ram write port 53. Analyzing top.Core.Data_memory.ram write port 54. Analyzing top.Core.Data_memory.ram write port 55. Analyzing top.Core.Data_memory.ram write port 56. Analyzing top.Core.Data_memory.ram write port 57. Analyzing top.Core.Data_memory.ram write port 58. Analyzing top.Core.Data_memory.ram write port 59. Analyzing top.Core.Data_memory.ram write port 60. Analyzing top.Core.Data_memory.ram write port 61. Analyzing top.Core.Data_memory.ram write port 62. Analyzing top.Core.Data_memory.ram write port 63. Analyzing top.Core.Data_memory.ram write port 64. Analyzing top.Core.Data_memory.ram write port 65. Analyzing top.Core.Data_memory.ram write port 66. Analyzing top.Core.Data_memory.ram write port 67. Analyzing top.Core.Data_memory.ram write port 68. Analyzing top.Core.Data_memory.ram write port 69. Analyzing top.Core.Data_memory.ram write port 70. Analyzing top.Core.Data_memory.ram write port 71. Analyzing top.Core.Data_memory.ram write port 72. Analyzing top.Core.Data_memory.ram write port 73. Analyzing top.Core.Data_memory.ram write port 74. Analyzing top.Core.Data_memory.ram write port 75. Analyzing top.Core.Data_memory.ram write port 76. Analyzing top.Core.Data_memory.ram write port 77. Analyzing top.Core.Data_memory.ram write port 78. Analyzing top.Core.Data_memory.ram write port 79. Analyzing top.Core.Data_memory.ram write port 80. Analyzing top.Core.Data_memory.ram write port 81. Analyzing top.Core.Data_memory.ram write port 82. Analyzing top.Core.Data_memory.ram write port 83. Analyzing top.Core.Data_memory.ram write port 84. Analyzing top.Core.Data_memory.ram write port 85. Analyzing top.Core.Data_memory.ram write port 86. Analyzing top.Core.Data_memory.ram write port 87. Analyzing top.Core.Data_memory.ram write port 88. Analyzing top.Core.Data_memory.ram write port 89. Analyzing top.Core.Data_memory.ram write port 90. Analyzing top.Core.Data_memory.ram write port 91. Analyzing top.Core.Data_memory.ram write port 92. Analyzing top.Core.Data_memory.ram write port 93. Analyzing top.Core.Data_memory.ram write port 94. Analyzing top.Core.Data_memory.ram write port 95. Analyzing top.Core.Data_memory.ram write port 96. Analyzing top.Core.Data_memory.ram write port 97. Analyzing top.Core.Data_memory.ram write port 98. Analyzing top.Core.Data_memory.ram write port 99. Analyzing top.Core.Data_memory.ram write port 100. Analyzing top.Core.Data_memory.ram write port 101. Analyzing top.Core.Data_memory.ram write port 102. Analyzing top.Core.Data_memory.ram write port 103. Analyzing top.Core.Data_memory.ram write port 104. Analyzing top.Core.Data_memory.ram write port 105. Analyzing top.Core.Data_memory.ram write port 106. Analyzing top.Core.Data_memory.ram write port 107. Analyzing top.Core.Data_memory.ram write port 108. Analyzing top.Core.Data_memory.ram write port 109. Analyzing top.Core.Data_memory.ram write port 110. Analyzing top.Core.Data_memory.ram write port 111. Analyzing top.Core.Data_memory.ram write port 112. Analyzing top.Core.Data_memory.ram write port 113. Analyzing top.Core.Data_memory.ram write port 114. Analyzing top.Core.Data_memory.ram write port 115. Analyzing top.Core.Data_memory.ram write port 116. Analyzing top.Core.Data_memory.ram write port 117. Analyzing top.Core.Data_memory.ram write port 118. Analyzing top.Core.Data_memory.ram write port 119. Analyzing top.Core.Data_memory.ram write port 120. Analyzing top.Core.Data_memory.ram write port 121. Analyzing top.Core.Data_memory.ram write port 122. Analyzing top.Core.Data_memory.ram write port 123. Analyzing top.Core.Data_memory.ram write port 124. Analyzing top.Core.Data_memory.ram write port 125. Analyzing top.Core.Data_memory.ram write port 126. Analyzing top.Core.Data_memory.ram write port 127. Analyzing top.Core.Data_memory.ram write port 128. Analyzing top.Core.Data_memory.ram write port 129. Analyzing top.Core.Data_memory.ram write port 130. Analyzing top.Core.Data_memory.ram write port 131. Analyzing top.Core.Data_memory.ram write port 132. Analyzing top.Core.Data_memory.ram write port 133. Analyzing top.Core.Data_memory.ram write port 134. Analyzing top.Core.Data_memory.ram write port 135. Analyzing top.Core.Data_memory.ram write port 136. Analyzing top.Core.Data_memory.ram write port 137. Analyzing top.Core.Data_memory.ram write port 138. Analyzing top.Core.Data_memory.ram write port 139. Analyzing top.Core.Data_memory.ram write port 140. Analyzing top.Core.Data_memory.ram write port 141. Analyzing top.Core.Data_memory.ram write port 142. Analyzing top.Core.Data_memory.ram write port 143. Analyzing top.Core.Data_memory.ram write port 144. Analyzing top.Core.Data_memory.ram write port 145. Analyzing top.Core.Data_memory.ram write port 146. Analyzing top.Core.Data_memory.ram write port 147. Analyzing top.Core.Data_memory.ram write port 148. Analyzing top.Core.Data_memory.ram write port 149. Analyzing top.Core.Data_memory.ram write port 150. Analyzing top.Core.Data_memory.ram write port 151. Analyzing top.Core.Data_memory.ram write port 152. Analyzing top.Core.Data_memory.ram write port 153. Analyzing top.Core.Data_memory.ram write port 154. Analyzing top.Core.Data_memory.ram write port 155. Analyzing top.Core.Data_memory.ram write port 156. Analyzing top.Core.Data_memory.ram write port 157. Analyzing top.Core.Data_memory.ram write port 158. Analyzing top.Core.Data_memory.ram write port 159. Analyzing top.Core.Data_memory.ram write port 160. Analyzing top.Core.Data_memory.ram write port 161. Analyzing top.Core.Data_memory.ram write port 162. Analyzing top.Core.Data_memory.ram write port 163. Analyzing top.Core.Data_memory.ram write port 164. Analyzing top.Core.Data_memory.ram write port 165. Analyzing top.Core.Data_memory.ram write port 166. Analyzing top.Core.Data_memory.ram write port 167. Analyzing top.Core.Data_memory.ram write port 168. Analyzing top.Core.Data_memory.ram write port 169. Analyzing top.Core.Data_memory.ram write port 170. Analyzing top.Core.Data_memory.ram write port 171. Analyzing top.Core.Data_memory.ram write port 172. Analyzing top.Core.Data_memory.ram write port 173. Analyzing top.Core.Data_memory.ram write port 174. Analyzing top.Core.Data_memory.ram write port 175. Analyzing top.Core.Data_memory.ram write port 176. Analyzing top.Core.Data_memory.ram write port 177. Analyzing top.Core.Data_memory.ram write port 178. Analyzing top.Core.Data_memory.ram write port 179. Analyzing top.Core.Data_memory.ram write port 180. Analyzing top.Core.Data_memory.ram write port 181. Analyzing top.Core.Data_memory.ram write port 182. Analyzing top.Core.Data_memory.ram write port 183. Analyzing top.Core.Data_memory.ram write port 184. Analyzing top.Core.Data_memory.ram write port 185. Analyzing top.Core.Data_memory.ram write port 186. Analyzing top.Core.Data_memory.ram write port 187. Analyzing top.Core.Data_memory.ram write port 188. Analyzing top.Core.Data_memory.ram write port 189. Analyzing top.Core.Data_memory.ram write port 190. Analyzing top.Core.Data_memory.ram write port 191. Analyzing top.Core.Data_memory.ram write port 192. Analyzing top.Core.Data_memory.ram write port 193. Analyzing top.Core.Data_memory.ram write port 194. Analyzing top.Core.Data_memory.ram write port 195. Analyzing top.Core.Data_memory.ram write port 196. Analyzing top.Core.Data_memory.ram write port 197. Analyzing top.Core.Data_memory.ram write port 198. Analyzing top.Core.Data_memory.ram write port 199. Analyzing top.Core.Data_memory.ram write port 200. Analyzing top.Core.Data_memory.ram write port 201. Analyzing top.Core.Data_memory.ram write port 202. Analyzing top.Core.Data_memory.ram write port 203. Analyzing top.Core.Data_memory.ram write port 204. Analyzing top.Core.Data_memory.ram write port 205. Analyzing top.Core.Data_memory.ram write port 206. Analyzing top.Core.Data_memory.ram write port 207. Analyzing top.Core.Data_memory.ram write port 208. Analyzing top.Core.Data_memory.ram write port 209. Analyzing top.Core.Data_memory.ram write port 210. Analyzing top.Core.Data_memory.ram write port 211. Analyzing top.Core.Data_memory.ram write port 212. Analyzing top.Core.Data_memory.ram write port 213. Analyzing top.Core.Data_memory.ram write port 214. Analyzing top.Core.Data_memory.ram write port 215. Analyzing top.Core.Data_memory.ram write port 216. Analyzing top.Core.Data_memory.ram write port 217. Analyzing top.Core.Data_memory.ram write port 218. Analyzing top.Core.Data_memory.ram write port 219. Analyzing top.Core.Data_memory.ram write port 220. Analyzing top.Core.Data_memory.ram write port 221. Analyzing top.Core.Data_memory.ram write port 222. Analyzing top.Core.Data_memory.ram write port 223. Analyzing top.Core.Data_memory.ram write port 224. Analyzing top.Core.Data_memory.ram write port 225. Analyzing top.Core.Data_memory.ram write port 226. Analyzing top.Core.Data_memory.ram write port 227. Analyzing top.Core.Data_memory.ram write port 228. Analyzing top.Core.Data_memory.ram write port 229. Analyzing top.Core.Data_memory.ram write port 230. Analyzing top.Core.Data_memory.ram write port 231. Analyzing top.Core.Data_memory.ram write port 232. Analyzing top.Core.Data_memory.ram write port 233. Analyzing top.Core.Data_memory.ram write port 234. Analyzing top.Core.Data_memory.ram write port 235. Analyzing top.Core.Data_memory.ram write port 236. Analyzing top.Core.Data_memory.ram write port 237. Analyzing top.Core.Data_memory.ram write port 238. Analyzing top.Core.Data_memory.ram write port 239. Analyzing top.Core.Data_memory.ram write port 240. Analyzing top.Core.Data_memory.ram write port 241. Analyzing top.Core.Data_memory.ram write port 242. Analyzing top.Core.Data_memory.ram write port 243. Analyzing top.Core.Data_memory.ram write port 244. Analyzing top.Core.Data_memory.ram write port 245. Analyzing top.Core.Data_memory.ram write port 246. Analyzing top.Core.Data_memory.ram write port 247. Analyzing top.Core.Data_memory.ram write port 248. Analyzing top.Core.Data_memory.ram write port 249. Analyzing top.Core.Data_memory.ram write port 250. Analyzing top.Core.Data_memory.ram write port 251. Analyzing top.Core.Data_memory.ram write port 252. Analyzing top.Core.Data_memory.ram write port 253. Analyzing top.Core.Data_memory.ram write port 254. Analyzing top.Core.Data_memory.ram write port 255. Analyzing top.Core.Data_memory.ram write port 256. Analyzing top.Core.Data_memory.ram write port 257. Analyzing top.Core.Data_memory.ram write port 258. Analyzing top.Core.Data_memory.ram write port 259. Analyzing top.Core.Data_memory.ram write port 260. Analyzing top.Core.Data_memory.ram write port 261. Analyzing top.Core.Data_memory.ram write port 262. Analyzing top.Core.Data_memory.ram write port 263. Analyzing top.Core.Data_memory.ram write port 264. Analyzing top.Core.Data_memory.ram write port 265. Analyzing top.Core.Data_memory.ram write port 266. Analyzing top.Core.Data_memory.ram write port 267. Analyzing top.Core.Data_memory.ram write port 268. Analyzing top.Core.Data_memory.ram write port 269. Analyzing top.Core.Data_memory.ram write port 270. Analyzing top.Core.Data_memory.ram write port 271. Analyzing top.Core.Data_memory.ram write port 272. Analyzing top.Core.Data_memory.ram write port 273. Analyzing top.Core.Data_memory.ram write port 274. Analyzing top.Core.Data_memory.ram write port 275. Analyzing top.Core.Data_memory.ram write port 276. Analyzing top.Core.Data_memory.ram write port 277. Analyzing top.Core.Data_memory.ram write port 278. Analyzing top.Core.Data_memory.ram write port 279. Analyzing top.Core.Data_memory.ram write port 280. Analyzing top.Core.Data_memory.ram write port 281. Analyzing top.Core.Data_memory.ram write port 282. Analyzing top.Core.Data_memory.ram write port 283. Analyzing top.Core.Data_memory.ram write port 284. Analyzing top.Core.Data_memory.ram write port 285. Analyzing top.Core.Data_memory.ram write port 286. Analyzing top.Core.Data_memory.ram write port 287. Analyzing top.Core.Data_memory.ram write port 288. Analyzing top.Core.Data_memory.ram write port 289. Analyzing top.Core.Data_memory.ram write port 290. Analyzing top.Core.Data_memory.ram write port 291. Analyzing top.Core.Data_memory.ram write port 292. Analyzing top.Core.Data_memory.ram write port 293. Analyzing top.Core.Data_memory.ram write port 294. Analyzing top.Core.Data_memory.ram write port 295. Analyzing top.Core.Data_memory.ram write port 296. Analyzing top.Core.Data_memory.ram write port 297. Analyzing top.Core.Data_memory.ram write port 298. Analyzing top.Core.Data_memory.ram write port 299. Analyzing top.Core.Data_memory.ram write port 300. Analyzing top.Core.Data_memory.ram write port 301. Analyzing top.Core.Data_memory.ram write port 302. Analyzing top.Core.Data_memory.ram write port 303. Analyzing top.Core.Data_memory.ram write port 304. Analyzing top.Core.Data_memory.ram write port 305. Analyzing top.Core.Data_memory.ram write port 306. Analyzing top.Core.Data_memory.ram write port 307. Analyzing top.Core.Data_memory.ram write port 308. Analyzing top.Core.Data_memory.ram write port 309. Analyzing top.Core.Data_memory.ram write port 310. Analyzing top.Core.Data_memory.ram write port 311. Analyzing top.Core.Data_memory.ram write port 312. Analyzing top.Core.Data_memory.ram write port 313. Analyzing top.Core.Data_memory.ram write port 314. Analyzing top.Core.Data_memory.ram write port 315. Analyzing top.Core.Data_memory.ram write port 316. Analyzing top.Core.Data_memory.ram write port 317. Analyzing top.Core.Data_memory.ram write port 318. Analyzing top.Core.Data_memory.ram write port 319. Analyzing top.Core.Data_memory.ram write port 320. Analyzing top.Core.Data_memory.ram write port 321. Analyzing top.Core.Data_memory.ram write port 322. Analyzing top.Core.Data_memory.ram write port 323. Analyzing top.Core.Data_memory.ram write port 324. Analyzing top.Core.Data_memory.ram write port 325. Analyzing top.Core.Data_memory.ram write port 326. Analyzing top.Core.Data_memory.ram write port 327. Analyzing top.Core.Data_memory.ram write port 328. Analyzing top.Core.Data_memory.ram write port 329. Analyzing top.Core.Data_memory.ram write port 330. Analyzing top.Core.Data_memory.ram write port 331. Analyzing top.Core.Data_memory.ram write port 332. Analyzing top.Core.Data_memory.ram write port 333. Analyzing top.Core.Data_memory.ram write port 334. Analyzing top.Core.Data_memory.ram write port 335. Analyzing top.Core.Data_memory.ram write port 336. Analyzing top.Core.Data_memory.ram write port 337. Analyzing top.Core.Data_memory.ram write port 338. Analyzing top.Core.Data_memory.ram write port 339. Analyzing top.Core.Data_memory.ram write port 340. Analyzing top.Core.Data_memory.ram write port 341. Analyzing top.Core.Data_memory.ram write port 342. Analyzing top.Core.Data_memory.ram write port 343. Analyzing top.Core.Data_memory.ram write port 344. Analyzing top.Core.Data_memory.ram write port 345. Analyzing top.Core.Data_memory.ram write port 346. Analyzing top.Core.Data_memory.ram write port 347. Analyzing top.Core.Data_memory.ram write port 348. Analyzing top.Core.Data_memory.ram write port 349. Analyzing top.Core.Data_memory.ram write port 350. Analyzing top.Core.Data_memory.ram write port 351. Analyzing top.Core.Data_memory.ram write port 352. Analyzing top.Core.Data_memory.ram write port 353. Analyzing top.Core.Data_memory.ram write port 354. Analyzing top.Core.Data_memory.ram write port 355. Analyzing top.Core.Data_memory.ram write port 356. Analyzing top.Core.Data_memory.ram write port 357. Analyzing top.Core.Data_memory.ram write port 358. Analyzing top.Core.Data_memory.ram write port 359. Analyzing top.Core.Data_memory.ram write port 360. Analyzing top.Core.Data_memory.ram write port 361. Analyzing top.Core.Data_memory.ram write port 362. Analyzing top.Core.Data_memory.ram write port 363. Analyzing top.Core.Data_memory.ram write port 364. Analyzing top.Core.Data_memory.ram write port 365. Analyzing top.Core.Data_memory.ram write port 366. Analyzing top.Core.Data_memory.ram write port 367. Analyzing top.Core.Data_memory.ram write port 368. Analyzing top.Core.Data_memory.ram write port 369. Analyzing top.Core.Data_memory.ram write port 370. Analyzing top.Core.Data_memory.ram write port 371. Analyzing top.Core.Data_memory.ram write port 372. Analyzing top.Core.Data_memory.ram write port 373. Analyzing top.Core.Data_memory.ram write port 374. Analyzing top.Core.Data_memory.ram write port 375. Analyzing top.Core.Data_memory.ram write port 376. Analyzing top.Core.Data_memory.ram write port 377. Analyzing top.Core.Data_memory.ram write port 378. Analyzing top.Core.Data_memory.ram write port 379. Analyzing top.Core.Data_memory.ram write port 380. Analyzing top.Core.Data_memory.ram write port 381. Analyzing top.Core.Data_memory.ram write port 382. Analyzing top.Core.Data_memory.ram write port 383. Analyzing top.Core.Data_memory.ram write port 384. Analyzing top.Core.Data_memory.ram write port 385. Analyzing top.Core.Data_memory.ram write port 386. Analyzing top.Core.Data_memory.ram write port 387. Analyzing top.Core.Data_memory.ram write port 388. Analyzing top.Core.Data_memory.ram write port 389. Analyzing top.Core.Data_memory.ram write port 390. Analyzing top.Core.Data_memory.ram write port 391. Analyzing top.Core.Data_memory.ram write port 392. Analyzing top.Core.Data_memory.ram write port 393. Analyzing top.Core.Data_memory.ram write port 394. Analyzing top.Core.Data_memory.ram write port 395. Analyzing top.Core.Data_memory.ram write port 396. Analyzing top.Core.Data_memory.ram write port 397. Analyzing top.Core.Data_memory.ram write port 398. Analyzing top.Core.Data_memory.ram write port 399. Analyzing top.Core.Data_memory.ram write port 400. Analyzing top.Core.Data_memory.ram write port 401. Analyzing top.Core.Data_memory.ram write port 402. Analyzing top.Core.Data_memory.ram write port 403. Analyzing top.Core.Data_memory.ram write port 404. Analyzing top.Core.Data_memory.ram write port 405. Analyzing top.Core.Data_memory.ram write port 406. Analyzing top.Core.Data_memory.ram write port 407. Analyzing top.Core.Data_memory.ram write port 408. Analyzing top.Core.Data_memory.ram write port 409. Analyzing top.Core.Data_memory.ram write port 410. Analyzing top.Core.Data_memory.ram write port 411. Analyzing top.Core.Data_memory.ram write port 412. Analyzing top.Core.Data_memory.ram write port 413. Analyzing top.Core.Data_memory.ram write port 414. Analyzing top.Core.Data_memory.ram write port 415. Analyzing top.Core.Data_memory.ram write port 416. Analyzing top.Core.Data_memory.ram write port 417. Analyzing top.Core.Data_memory.ram write port 418. Analyzing top.Core.Data_memory.ram write port 419. Analyzing top.Core.Data_memory.ram write port 420. Analyzing top.Core.Data_memory.ram write port 421. Analyzing top.Core.Data_memory.ram write port 422. Analyzing top.Core.Data_memory.ram write port 423. Analyzing top.Core.Data_memory.ram write port 424. Analyzing top.Core.Data_memory.ram write port 425. Analyzing top.Core.Data_memory.ram write port 426. Analyzing top.Core.Data_memory.ram write port 427. Analyzing top.Core.Data_memory.ram write port 428. Analyzing top.Core.Data_memory.ram write port 429. Analyzing top.Core.Data_memory.ram write port 430. Analyzing top.Core.Data_memory.ram write port 431. Analyzing top.Core.Data_memory.ram write port 432. Analyzing top.Core.Data_memory.ram write port 433. Analyzing top.Core.Data_memory.ram write port 434. Analyzing top.Core.Data_memory.ram write port 435. Analyzing top.Core.Data_memory.ram write port 436. Analyzing top.Core.Data_memory.ram write port 437. Analyzing top.Core.Data_memory.ram write port 438. Analyzing top.Core.Data_memory.ram write port 439. Analyzing top.Core.Data_memory.ram write port 440. Analyzing top.Core.Data_memory.ram write port 441. Analyzing top.Core.Data_memory.ram write port 442. Analyzing top.Core.Data_memory.ram write port 443. Analyzing top.Core.Data_memory.ram write port 444. Analyzing top.Core.Data_memory.ram write port 445. Analyzing top.Core.Data_memory.ram write port 446. Analyzing top.Core.Data_memory.ram write port 447. Analyzing top.Core.Data_memory.ram write port 448. Analyzing top.Core.Data_memory.ram write port 449. Analyzing top.Core.Data_memory.ram write port 450. Analyzing top.Core.Data_memory.ram write port 451. Analyzing top.Core.Data_memory.ram write port 452. Analyzing top.Core.Data_memory.ram write port 453. Analyzing top.Core.Data_memory.ram write port 454. Analyzing top.Core.Data_memory.ram write port 455. Analyzing top.Core.Data_memory.ram write port 456. Analyzing top.Core.Data_memory.ram write port 457. Analyzing top.Core.Data_memory.ram write port 458. Analyzing top.Core.Data_memory.ram write port 459. Analyzing top.Core.Data_memory.ram write port 460. Analyzing top.Core.Data_memory.ram write port 461. Analyzing top.Core.Data_memory.ram write port 462. Analyzing top.Core.Data_memory.ram write port 463. Analyzing top.Core.Data_memory.ram write port 464. Analyzing top.Core.Data_memory.ram write port 465. Analyzing top.Core.Data_memory.ram write port 466. Analyzing top.Core.Data_memory.ram write port 467. Analyzing top.Core.Data_memory.ram write port 468. Analyzing top.Core.Data_memory.ram write port 469. Analyzing top.Core.Data_memory.ram write port 470. Analyzing top.Core.Data_memory.ram write port 471. Analyzing top.Core.Data_memory.ram write port 472. Analyzing top.Core.Data_memory.ram write port 473. Analyzing top.Core.Data_memory.ram write port 474. Analyzing top.Core.Data_memory.ram write port 475. Analyzing top.Core.Data_memory.ram write port 476. Analyzing top.Core.Data_memory.ram write port 477. Analyzing top.Core.Data_memory.ram write port 478. Analyzing top.Core.Data_memory.ram write port 479. Analyzing top.Core.Data_memory.ram write port 480. Analyzing top.Core.Data_memory.ram write port 481. Analyzing top.Core.Data_memory.ram write port 482. Analyzing top.Core.Data_memory.ram write port 483. Analyzing top.Core.Data_memory.ram write port 484. Analyzing top.Core.Data_memory.ram write port 485. Analyzing top.Core.Data_memory.ram write port 486. Analyzing top.Core.Data_memory.ram write port 487. Analyzing top.Core.Data_memory.ram write port 488. Analyzing top.Core.Data_memory.ram write port 489. Analyzing top.Core.Data_memory.ram write port 490. Analyzing top.Core.Data_memory.ram write port 491. Analyzing top.Core.Data_memory.ram write port 492. Analyzing top.Core.Data_memory.ram write port 493. Analyzing top.Core.Data_memory.ram write port 494. Analyzing top.Core.Data_memory.ram write port 495. Analyzing top.Core.Data_memory.ram write port 496. Analyzing top.Core.Data_memory.ram write port 497. Analyzing top.Core.Data_memory.ram write port 498. Analyzing top.Core.Data_memory.ram write port 499. Analyzing top.Core.Data_memory.ram write port 500. Analyzing top.Core.Data_memory.ram write port 501. Analyzing top.Core.Data_memory.ram write port 502. Analyzing top.Core.Data_memory.ram write port 503. Analyzing top.Core.Data_memory.ram write port 504. Analyzing top.Core.Data_memory.ram write port 505. Analyzing top.Core.Data_memory.ram write port 506. Analyzing top.Core.Data_memory.ram write port 507. Analyzing top.Core.Data_memory.ram write port 508. Analyzing top.Core.Data_memory.ram write port 509. Analyzing top.Core.Data_memory.ram write port 510. Analyzing top.Core.Data_memory.ram write port 511. Analyzing top.Core.Data_memory.ram write port 512. Analyzing top.Core.Data_memory.ram write port 513. Analyzing top.Core.Data_memory.ram write port 514. Analyzing top.Core.Data_memory.ram write port 515. Analyzing top.Core.Data_memory.ram write port 516. Analyzing top.Core.Data_memory.ram write port 517. Analyzing top.Core.Data_memory.ram write port 518. Analyzing top.Core.Data_memory.ram write port 519. Analyzing top.Core.Data_memory.ram write port 520. Analyzing top.Core.Data_memory.ram write port 521. Analyzing top.Core.Data_memory.ram write port 522. Analyzing top.Core.Data_memory.ram write port 523. Analyzing top.Core.Data_memory.ram write port 524. Analyzing top.Core.Data_memory.ram write port 525. Analyzing top.Core.Data_memory.ram write port 526. Analyzing top.Core.Data_memory.ram write port 527. Analyzing top.Core.Data_memory.ram write port 528. Analyzing top.Core.Data_memory.ram write port 529. Analyzing top.Core.Data_memory.ram write port 530. Analyzing top.Core.Data_memory.ram write port 531. Analyzing top.Core.Data_memory.ram write port 532. Analyzing top.Core.Data_memory.ram write port 533. Analyzing top.Core.Data_memory.ram write port 534. Analyzing top.Core.Data_memory.ram write port 535. Analyzing top.Core.Data_memory.ram write port 536. Analyzing top.Core.Data_memory.ram write port 537. Analyzing top.Core.Data_memory.ram write port 538. Analyzing top.Core.Data_memory.ram write port 539. Analyzing top.Core.Data_memory.ram write port 540. Analyzing top.Core.Data_memory.ram write port 541. Analyzing top.Core.Data_memory.ram write port 542. Analyzing top.Core.Data_memory.ram write port 543. Analyzing top.Core.Data_memory.ram write port 544. Analyzing top.Core.Data_memory.ram write port 545. Analyzing top.Core.Data_memory.ram write port 546. Analyzing top.Core.Data_memory.ram write port 547. Analyzing top.Core.Data_memory.ram write port 548. Analyzing top.Core.Data_memory.ram write port 549. Analyzing top.Core.Data_memory.ram write port 550. Analyzing top.Core.Data_memory.ram write port 551. Analyzing top.Core.Data_memory.ram write port 552. Analyzing top.Core.Data_memory.ram write port 553. Analyzing top.Core.Data_memory.ram write port 554. Analyzing top.Core.Data_memory.ram write port 555. Analyzing top.Core.Data_memory.ram write port 556. Analyzing top.Core.Data_memory.ram write port 557. Analyzing top.Core.Data_memory.ram write port 558. Analyzing top.Core.Data_memory.ram write port 559. Analyzing top.Core.Data_memory.ram write port 560. Analyzing top.Core.Data_memory.ram write port 561. Analyzing top.Core.Data_memory.ram write port 562. Analyzing top.Core.Data_memory.ram write port 563. Analyzing top.Core.Data_memory.ram write port 564. Analyzing top.Core.Data_memory.ram write port 565. Analyzing top.Core.Data_memory.ram write port 566. Analyzing top.Core.Data_memory.ram write port 567. Analyzing top.Core.Data_memory.ram write port 568. Analyzing top.Core.Data_memory.ram write port 569. Analyzing top.Core.Data_memory.ram write port 570. Analyzing top.Core.Data_memory.ram write port 571. Analyzing top.Core.Data_memory.ram write port 572. Analyzing top.Core.Data_memory.ram write port 573. Analyzing top.Core.Data_memory.ram write port 574. Analyzing top.Core.Data_memory.ram write port 575. Analyzing top.Core.Data_memory.ram write port 576. Analyzing top.Core.Data_memory.ram write port 577. Analyzing top.Core.Data_memory.ram write port 578. Analyzing top.Core.Data_memory.ram write port 579. Analyzing top.Core.Data_memory.ram write port 580. Analyzing top.Core.Data_memory.ram write port 581. Analyzing top.Core.Data_memory.ram write port 582. Analyzing top.Core.Data_memory.ram write port 583. Analyzing top.Core.Data_memory.ram write port 584. Analyzing top.Core.Data_memory.ram write port 585. Analyzing top.Core.Data_memory.ram write port 586. Analyzing top.Core.Data_memory.ram write port 587. Analyzing top.Core.Data_memory.ram write port 588. Analyzing top.Core.Data_memory.ram write port 589. Analyzing top.Core.Data_memory.ram write port 590. Analyzing top.Core.Data_memory.ram write port 591. Analyzing top.Core.Data_memory.ram write port 592. Analyzing top.Core.Data_memory.ram write port 593. Analyzing top.Core.Data_memory.ram write port 594. Analyzing top.Core.Data_memory.ram write port 595. Analyzing top.Core.Data_memory.ram write port 596. Analyzing top.Core.Data_memory.ram write port 597. Analyzing top.Core.Data_memory.ram write port 598. Analyzing top.Core.Data_memory.ram write port 599. Analyzing top.Core.Data_memory.ram write port 600. Analyzing top.Core.Data_memory.ram write port 601. Analyzing top.Core.Data_memory.ram write port 602. Analyzing top.Core.Data_memory.ram write port 603. Analyzing top.Core.Data_memory.ram write port 604. Analyzing top.Core.Data_memory.ram write port 605. Analyzing top.Core.Data_memory.ram write port 606. Analyzing top.Core.Data_memory.ram write port 607. Analyzing top.Core.Data_memory.ram write port 608. Analyzing top.Core.Data_memory.ram write port 609. Analyzing top.Core.Data_memory.ram write port 610. Analyzing top.Core.Data_memory.ram write port 611. Analyzing top.Core.Data_memory.ram write port 612. Analyzing top.Core.Data_memory.ram write port 613. Analyzing top.Core.Data_memory.ram write port 614. Analyzing top.Core.Data_memory.ram write port 615. Analyzing top.Core.Data_memory.ram write port 616. Analyzing top.Core.Data_memory.ram write port 617. Analyzing top.Core.Data_memory.ram write port 618. Analyzing top.Core.Data_memory.ram write port 619. Analyzing top.Core.Data_memory.ram write port 620. Analyzing top.Core.Data_memory.ram write port 621. Analyzing top.Core.Data_memory.ram write port 622. Analyzing top.Core.Data_memory.ram write port 623. Analyzing top.Core.Data_memory.ram write port 624. Analyzing top.Core.Data_memory.ram write port 625. Analyzing top.Core.Data_memory.ram write port 626. Analyzing top.Core.Data_memory.ram write port 627. Analyzing top.Core.Data_memory.ram write port 628. Analyzing top.Core.Data_memory.ram write port 629. Analyzing top.Core.Data_memory.ram write port 630. Analyzing top.Core.Data_memory.ram write port 631. Analyzing top.Core.Data_memory.ram write port 632. Analyzing top.Core.Data_memory.ram write port 633. Analyzing top.Core.Data_memory.ram write port 634. Analyzing top.Core.Data_memory.ram write port 635. Analyzing top.Core.Data_memory.ram write port 636. Analyzing top.Core.Data_memory.ram write port 637. Analyzing top.Core.Data_memory.ram write port 638. Analyzing top.Core.Data_memory.ram write port 639. Analyzing top.Core.Data_memory.ram write port 640. Analyzing top.Core.Data_memory.ram write port 641. Analyzing top.Core.Data_memory.ram write port 642. Analyzing top.Core.Data_memory.ram write port 643. Analyzing top.Core.Data_memory.ram write port 644. Analyzing top.Core.Data_memory.ram write port 645. Analyzing top.Core.Data_memory.ram write port 646. Analyzing top.Core.Data_memory.ram write port 647. Analyzing top.Core.Data_memory.ram write port 648. Analyzing top.Core.Data_memory.ram write port 649. Analyzing top.Core.Data_memory.ram write port 650. Analyzing top.Core.Data_memory.ram write port 651. Analyzing top.Core.Data_memory.ram write port 652. Analyzing top.Core.Data_memory.ram write port 653. Analyzing top.Core.Data_memory.ram write port 654. Analyzing top.Core.Data_memory.ram write port 655. Analyzing top.Core.Data_memory.ram write port 656. Analyzing top.Core.Data_memory.ram write port 657. Analyzing top.Core.Data_memory.ram write port 658. Analyzing top.Core.Data_memory.ram write port 659. Analyzing top.Core.Data_memory.ram write port 660. Analyzing top.Core.Data_memory.ram write port 661. Analyzing top.Core.Data_memory.ram write port 662. Analyzing top.Core.Data_memory.ram write port 663. Analyzing top.Core.Data_memory.ram write port 664. Analyzing top.Core.Data_memory.ram write port 665. Analyzing top.Core.Data_memory.ram write port 666. Analyzing top.Core.Data_memory.ram write port 667. Analyzing top.Core.Data_memory.ram write port 668. Analyzing top.Core.Data_memory.ram write port 669. Analyzing top.Core.Data_memory.ram write port 670. Analyzing top.Core.Data_memory.ram write port 671. Analyzing top.Core.Data_memory.ram write port 672. Analyzing top.Core.Data_memory.ram write port 673. Analyzing top.Core.Data_memory.ram write port 674. Analyzing top.Core.Data_memory.ram write port 675. Analyzing top.Core.Data_memory.ram write port 676. Analyzing top.Core.Data_memory.ram write port 677. Analyzing top.Core.Data_memory.ram write port 678. Analyzing top.Core.Data_memory.ram write port 679. Analyzing top.Core.Data_memory.ram write port 680. Analyzing top.Core.Data_memory.ram write port 681. Analyzing top.Core.Data_memory.ram write port 682. Analyzing top.Core.Data_memory.ram write port 683. Analyzing top.Core.Data_memory.ram write port 684. Analyzing top.Core.Data_memory.ram write port 685. Analyzing top.Core.Data_memory.ram write port 686. Analyzing top.Core.Data_memory.ram write port 687. Analyzing top.Core.Data_memory.ram write port 688. Analyzing top.Core.Data_memory.ram write port 689. Analyzing top.Core.Data_memory.ram write port 690. Analyzing top.Core.Data_memory.ram write port 691. Analyzing top.Core.Data_memory.ram write port 692. Analyzing top.Core.Data_memory.ram write port 693. Analyzing top.Core.Data_memory.ram write port 694. Analyzing top.Core.Data_memory.ram write port 695. Analyzing top.Core.Data_memory.ram write port 696. Analyzing top.Core.Data_memory.ram write port 697. Analyzing top.Core.Data_memory.ram write port 698. Analyzing top.Core.Data_memory.ram write port 699. Analyzing top.Core.Data_memory.ram write port 700. Analyzing top.Core.Data_memory.ram write port 701. Analyzing top.Core.Data_memory.ram write port 702. Analyzing top.Core.Data_memory.ram write port 703. Analyzing top.Core.Data_memory.ram write port 704. Analyzing top.Core.Data_memory.ram write port 705. Analyzing top.Core.Data_memory.ram write port 706. Analyzing top.Core.Data_memory.ram write port 707. Analyzing top.Core.Data_memory.ram write port 708. Analyzing top.Core.Data_memory.ram write port 709. Analyzing top.Core.Data_memory.ram write port 710. Analyzing top.Core.Data_memory.ram write port 711. Analyzing top.Core.Data_memory.ram write port 712. Analyzing top.Core.Data_memory.ram write port 713. Analyzing top.Core.Data_memory.ram write port 714. Analyzing top.Core.Data_memory.ram write port 715. Analyzing top.Core.Data_memory.ram write port 716. Analyzing top.Core.Data_memory.ram write port 717. Analyzing top.Core.Data_memory.ram write port 718. Analyzing top.Core.Data_memory.ram write port 719. Analyzing top.Core.Data_memory.ram write port 720. Analyzing top.Core.Data_memory.ram write port 721. Analyzing top.Core.Data_memory.ram write port 722. Analyzing top.Core.Data_memory.ram write port 723. Analyzing top.Core.Data_memory.ram write port 724. Analyzing top.Core.Data_memory.ram write port 725. Analyzing top.Core.Data_memory.ram write port 726. Analyzing top.Core.Data_memory.ram write port 727. Analyzing top.Core.Data_memory.ram write port 728. Analyzing top.Core.Data_memory.ram write port 729. Analyzing top.Core.Data_memory.ram write port 730. Analyzing top.Core.Data_memory.ram write port 731. Analyzing top.Core.Data_memory.ram write port 732. Analyzing top.Core.Data_memory.ram write port 733. Analyzing top.Core.Data_memory.ram write port 734. Analyzing top.Core.Data_memory.ram write port 735. Analyzing top.Core.Data_memory.ram write port 736. Analyzing top.Core.Data_memory.ram write port 737. Analyzing top.Core.Data_memory.ram write port 738. Analyzing top.Core.Data_memory.ram write port 739. Analyzing top.Core.Data_memory.ram write port 740. Analyzing top.Core.Data_memory.ram write port 741. Analyzing top.Core.Data_memory.ram write port 742. Analyzing top.Core.Data_memory.ram write port 743. Analyzing top.Core.Data_memory.ram write port 744. Analyzing top.Core.Data_memory.ram write port 745. Analyzing top.Core.Data_memory.ram write port 746. Analyzing top.Core.Data_memory.ram write port 747. Analyzing top.Core.Data_memory.ram write port 748. Analyzing top.Core.Data_memory.ram write port 749. Analyzing top.Core.Data_memory.ram write port 750. Analyzing top.Core.Data_memory.ram write port 751. Analyzing top.Core.Data_memory.ram write port 752. Analyzing top.Core.Data_memory.ram write port 753. Analyzing top.Core.Data_memory.ram write port 754. Analyzing top.Core.Data_memory.ram write port 755. Analyzing top.Core.Data_memory.ram write port 756. Analyzing top.Core.Data_memory.ram write port 757. Analyzing top.Core.Data_memory.ram write port 758. Analyzing top.Core.Data_memory.ram write port 759. Analyzing top.Core.Data_memory.ram write port 760. Analyzing top.Core.Data_memory.ram write port 761. Analyzing top.Core.Data_memory.ram write port 762. Analyzing top.Core.Data_memory.ram write port 763. Analyzing top.Core.Data_memory.ram write port 764. Analyzing top.Core.Data_memory.ram write port 765. Analyzing top.Core.Data_memory.ram write port 766. Analyzing top.Core.Data_memory.ram write port 767. Analyzing top.Core.Data_memory.ram write port 768. Analyzing top.Core.Data_memory.ram write port 769. Analyzing top.Core.Data_memory.ram write port 770. Analyzing top.Core.Data_memory.ram write port 771. Analyzing top.Core.Data_memory.ram write port 772. Analyzing top.Core.Data_memory.ram write port 773. Analyzing top.Core.Data_memory.ram write port 774. Analyzing top.Core.Data_memory.ram write port 775. Analyzing top.Core.Data_memory.ram write port 776. Analyzing top.Core.Data_memory.ram write port 777. Analyzing top.Core.Data_memory.ram write port 778. Analyzing top.Core.Data_memory.ram write port 779. Analyzing top.Core.Data_memory.ram write port 780. Analyzing top.Core.Data_memory.ram write port 781. Analyzing top.Core.Data_memory.ram write port 782. Analyzing top.Core.Data_memory.ram write port 783. Analyzing top.Core.Data_memory.ram write port 784. Analyzing top.Core.Data_memory.ram write port 785. Analyzing top.Core.Data_memory.ram write port 786. Analyzing top.Core.Data_memory.ram write port 787. Analyzing top.Core.Data_memory.ram write port 788. Analyzing top.Core.Data_memory.ram write port 789. Analyzing top.Core.Data_memory.ram write port 790. Analyzing top.Core.Data_memory.ram write port 791. Analyzing top.Core.Data_memory.ram write port 792. Analyzing top.Core.Data_memory.ram write port 793. Analyzing top.Core.Data_memory.ram write port 794. Analyzing top.Core.Data_memory.ram write port 795. Analyzing top.Core.Data_memory.ram write port 796. Analyzing top.Core.Data_memory.ram write port 797. Analyzing top.Core.Data_memory.ram write port 798. Analyzing top.Core.Data_memory.ram write port 799. Analyzing top.Core.Data_memory.ram write port 800. Analyzing top.Core.Data_memory.ram write port 801. Analyzing top.Core.Data_memory.ram write port 802. Analyzing top.Core.Data_memory.ram write port 803. Analyzing top.Core.Data_memory.ram write port 804. Analyzing top.Core.Data_memory.ram write port 805. Analyzing top.Core.Data_memory.ram write port 806. Analyzing top.Core.Data_memory.ram write port 807. Analyzing top.Core.Data_memory.ram write port 808. Analyzing top.Core.Data_memory.ram write port 809. Analyzing top.Core.Data_memory.ram write port 810. Analyzing top.Core.Data_memory.ram write port 811. Analyzing top.Core.Data_memory.ram write port 812. Analyzing top.Core.Data_memory.ram write port 813. Analyzing top.Core.Data_memory.ram write port 814. Analyzing top.Core.Data_memory.ram write port 815. Analyzing top.Core.Data_memory.ram write port 816. Analyzing top.Core.Data_memory.ram write port 817. Analyzing top.Core.Data_memory.ram write port 818. Analyzing top.Core.Data_memory.ram write port 819. Analyzing top.Core.Data_memory.ram write port 820. Analyzing top.Core.Data_memory.ram write port 821. Analyzing top.Core.Data_memory.ram write port 822. Analyzing top.Core.Data_memory.ram write port 823. Analyzing top.Core.Data_memory.ram write port 824. Analyzing top.Core.Data_memory.ram write port 825. Analyzing top.Core.Data_memory.ram write port 826. Analyzing top.Core.Data_memory.ram write port 827. Analyzing top.Core.Data_memory.ram write port 828. Analyzing top.Core.Data_memory.ram write port 829. Analyzing top.Core.Data_memory.ram write port 830. Analyzing top.Core.Data_memory.ram write port 831. Analyzing top.Core.Data_memory.ram write port 832. Analyzing top.Core.Data_memory.ram write port 833. Analyzing top.Core.Data_memory.ram write port 834. Analyzing top.Core.Data_memory.ram write port 835. Analyzing top.Core.Data_memory.ram write port 836. Analyzing top.Core.Data_memory.ram write port 837. Analyzing top.Core.Data_memory.ram write port 838. Analyzing top.Core.Data_memory.ram write port 839. Analyzing top.Core.Data_memory.ram write port 840. Analyzing top.Core.Data_memory.ram write port 841. Analyzing top.Core.Data_memory.ram write port 842. Analyzing top.Core.Data_memory.ram write port 843. Analyzing top.Core.Data_memory.ram write port 844. Analyzing top.Core.Data_memory.ram write port 845. Analyzing top.Core.Data_memory.ram write port 846. Analyzing top.Core.Data_memory.ram write port 847. Analyzing top.Core.Data_memory.ram write port 848. Analyzing top.Core.Data_memory.ram write port 849. Analyzing top.Core.Data_memory.ram write port 850. Analyzing top.Core.Data_memory.ram write port 851. Analyzing top.Core.Data_memory.ram write port 852. Analyzing top.Core.Data_memory.ram write port 853. Analyzing top.Core.Data_memory.ram write port 854. Analyzing top.Core.Data_memory.ram write port 855. Analyzing top.Core.Data_memory.ram write port 856. Analyzing top.Core.Data_memory.ram write port 857. Analyzing top.Core.Data_memory.ram write port 858. Analyzing top.Core.Data_memory.ram write port 859. Analyzing top.Core.Data_memory.ram write port 860. Analyzing top.Core.Data_memory.ram write port 861. Analyzing top.Core.Data_memory.ram write port 862. Analyzing top.Core.Data_memory.ram write port 863. Analyzing top.Core.Data_memory.ram write port 864. Analyzing top.Core.Data_memory.ram write port 865. Analyzing top.Core.Data_memory.ram write port 866. Analyzing top.Core.Data_memory.ram write port 867. Analyzing top.Core.Data_memory.ram write port 868. Analyzing top.Core.Data_memory.ram write port 869. Analyzing top.Core.Data_memory.ram write port 870. Analyzing top.Core.Data_memory.ram write port 871. Analyzing top.Core.Data_memory.ram write port 872. Analyzing top.Core.Data_memory.ram write port 873. Analyzing top.Core.Data_memory.ram write port 874. Analyzing top.Core.Data_memory.ram write port 875. Analyzing top.Core.Data_memory.ram write port 876. Analyzing top.Core.Data_memory.ram write port 877. Analyzing top.Core.Data_memory.ram write port 878. Analyzing top.Core.Data_memory.ram write port 879. Analyzing top.Core.Data_memory.ram write port 880. Analyzing top.Core.Data_memory.ram write port 881. Analyzing top.Core.Data_memory.ram write port 882. Analyzing top.Core.Data_memory.ram write port 883. Analyzing top.Core.Data_memory.ram write port 884. Analyzing top.Core.Data_memory.ram write port 885. Analyzing top.Core.Data_memory.ram write port 886. Analyzing top.Core.Data_memory.ram write port 887. Analyzing top.Core.Data_memory.ram write port 888. Analyzing top.Core.Data_memory.ram write port 889. Analyzing top.Core.Data_memory.ram write port 890. Analyzing top.Core.Data_memory.ram write port 891. Analyzing top.Core.Data_memory.ram write port 892. Analyzing top.Core.Data_memory.ram write port 893. Analyzing top.Core.Data_memory.ram write port 894. Analyzing top.Core.Data_memory.ram write port 895. Analyzing top.Core.Data_memory.ram write port 896. Analyzing top.Core.Data_memory.ram write port 897. Analyzing top.Core.Data_memory.ram write port 898. Analyzing top.Core.Data_memory.ram write port 899. Analyzing top.Core.Data_memory.ram write port 900. Analyzing top.Core.Data_memory.ram write port 901. Analyzing top.Core.Data_memory.ram write port 902. Analyzing top.Core.Data_memory.ram write port 903. Analyzing top.Core.Data_memory.ram write port 904. Analyzing top.Core.Data_memory.ram write port 905. Analyzing top.Core.Data_memory.ram write port 906. Analyzing top.Core.Data_memory.ram write port 907. Analyzing top.Core.Data_memory.ram write port 908. Analyzing top.Core.Data_memory.ram write port 909. Analyzing top.Core.Data_memory.ram write port 910. Analyzing top.Core.Data_memory.ram write port 911. Analyzing top.Core.Data_memory.ram write port 912. Analyzing top.Core.Data_memory.ram write port 913. Analyzing top.Core.Data_memory.ram write port 914. Analyzing top.Core.Data_memory.ram write port 915. Analyzing top.Core.Data_memory.ram write port 916. Analyzing top.Core.Data_memory.ram write port 917. Analyzing top.Core.Data_memory.ram write port 918. Analyzing top.Core.Data_memory.ram write port 919. Analyzing top.Core.Data_memory.ram write port 920. Analyzing top.Core.Data_memory.ram write port 921. Analyzing top.Core.Data_memory.ram write port 922. Analyzing top.Core.Data_memory.ram write port 923. Analyzing top.Core.Data_memory.ram write port 924. Analyzing top.Core.Data_memory.ram write port 925. Analyzing top.Core.Data_memory.ram write port 926. Analyzing top.Core.Data_memory.ram write port 927. Analyzing top.Core.Data_memory.ram write port 928. Analyzing top.Core.Data_memory.ram write port 929. Analyzing top.Core.Data_memory.ram write port 930. Analyzing top.Core.Data_memory.ram write port 931. Analyzing top.Core.Data_memory.ram write port 932. Analyzing top.Core.Data_memory.ram write port 933. Analyzing top.Core.Data_memory.ram write port 934. Analyzing top.Core.Data_memory.ram write port 935. Analyzing top.Core.Data_memory.ram write port 936. Analyzing top.Core.Data_memory.ram write port 937. Analyzing top.Core.Data_memory.ram write port 938. Analyzing top.Core.Data_memory.ram write port 939. Analyzing top.Core.Data_memory.ram write port 940. Analyzing top.Core.Data_memory.ram write port 941. Analyzing top.Core.Data_memory.ram write port 942. Analyzing top.Core.Data_memory.ram write port 943. Analyzing top.Core.Data_memory.ram write port 944. Analyzing top.Core.Data_memory.ram write port 945. Analyzing top.Core.Data_memory.ram write port 946. Analyzing top.Core.Data_memory.ram write port 947. Analyzing top.Core.Data_memory.ram write port 948. Analyzing top.Core.Data_memory.ram write port 949. Analyzing top.Core.Data_memory.ram write port 950. Analyzing top.Core.Data_memory.ram write port 951. Analyzing top.Core.Data_memory.ram write port 952. Analyzing top.Core.Data_memory.ram write port 953. Analyzing top.Core.Data_memory.ram write port 954. Analyzing top.Core.Data_memory.ram write port 955. Analyzing top.Core.Data_memory.ram write port 956. Analyzing top.Core.Data_memory.ram write port 957. Analyzing top.Core.Data_memory.ram write port 958. Analyzing top.Core.Data_memory.ram write port 959. Analyzing top.Core.Data_memory.ram write port 960. Analyzing top.Core.Data_memory.ram write port 961. Analyzing top.Core.Data_memory.ram write port 962. Analyzing top.Core.Data_memory.ram write port 963. Analyzing top.Core.Data_memory.ram write port 964. Analyzing top.Core.Data_memory.ram write port 965. Analyzing top.Core.Data_memory.ram write port 966. Analyzing top.Core.Data_memory.ram write port 967. Analyzing top.Core.Data_memory.ram write port 968. Analyzing top.Core.Data_memory.ram write port 969. Analyzing top.Core.Data_memory.ram write port 970. Analyzing top.Core.Data_memory.ram write port 971. Analyzing top.Core.Data_memory.ram write port 972. Analyzing top.Core.Data_memory.ram write port 973. Analyzing top.Core.Data_memory.ram write port 974. Analyzing top.Core.Data_memory.ram write port 975. Analyzing top.Core.Data_memory.ram write port 976. Analyzing top.Core.Data_memory.ram write port 977. Analyzing top.Core.Data_memory.ram write port 978. Analyzing top.Core.Data_memory.ram write port 979. Analyzing top.Core.Data_memory.ram write port 980. Analyzing top.Core.Data_memory.ram write port 981. Analyzing top.Core.Data_memory.ram write port 982. Analyzing top.Core.Data_memory.ram write port 983. Analyzing top.Core.Data_memory.ram write port 984. Analyzing top.Core.Data_memory.ram write port 985. Analyzing top.Core.Data_memory.ram write port 986. Analyzing top.Core.Data_memory.ram write port 987. Analyzing top.Core.Data_memory.ram write port 988. Analyzing top.Core.Data_memory.ram write port 989. Analyzing top.Core.Data_memory.ram write port 990. Analyzing top.Core.Data_memory.ram write port 991. Analyzing top.Core.Data_memory.ram write port 992. Analyzing top.Core.Data_memory.ram write port 993. Analyzing top.Core.Data_memory.ram write port 994. Analyzing top.Core.Data_memory.ram write port 995. Analyzing top.Core.Data_memory.ram write port 996. Analyzing top.Core.Data_memory.ram write port 997. Analyzing top.Core.Data_memory.ram write port 998. Analyzing top.Core.Data_memory.ram write port 999. Analyzing top.Core.Data_memory.ram write port 1000. Analyzing top.Core.Data_memory.ram write port 1001. Analyzing top.Core.Data_memory.ram write port 1002. Analyzing top.Core.Data_memory.ram write port 1003. Analyzing top.Core.Data_memory.ram write port 1004. Analyzing top.Core.Data_memory.ram write port 1005. Analyzing top.Core.Data_memory.ram write port 1006. Analyzing top.Core.Data_memory.ram write port 1007. Analyzing top.Core.Data_memory.ram write port 1008. Analyzing top.Core.Data_memory.ram write port 1009. Analyzing top.Core.Data_memory.ram write port 1010. Analyzing top.Core.Data_memory.ram write port 1011. Analyzing top.Core.Data_memory.ram write port 1012. Analyzing top.Core.Data_memory.ram write port 1013. Analyzing top.Core.Data_memory.ram write port 1014. Analyzing top.Core.Data_memory.ram write port 1015. Analyzing top.Core.Data_memory.ram write port 1016. Analyzing top.Core.Data_memory.ram write port 1017. Analyzing top.Core.Data_memory.ram write port 1018. Analyzing top.Core.Data_memory.ram write port 1019. Analyzing top.Core.Data_memory.ram write port 1020. Analyzing top.Core.Data_memory.ram write port 1021. Analyzing top.Core.Data_memory.ram write port 1022. Analyzing top.Core.Data_memory.ram write port 1023. 12.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 12.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\Core.Data_memory.ram'[0] in module `\top': no output FF found. Checking read port `\Core.Instruction_memory.memory'[0] in module `\top': no output FF found. Checking read port address `\Core.Data_memory.ram'[0] in module `\top': no address FF found. Checking read port address `\Core.Instruction_memory.memory'[0] in module `\top': address FF has fully-defined init value, not supported. 12.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 12.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory top.Core.Data_memory.ram by address: Merging ports 0, 1 (address 10'0000000000). Merging ports 0, 2 (address 10'0000000000). Merging ports 0, 3 (address 10'0000000000). Merging ports 0, 4 (address 10'0000000000). Merging ports 0, 5 (address 10'0000000000). Merging ports 0, 6 (address 10'0000000000). Merging ports 0, 7 (address 10'0000000000). Merging ports 0, 8 (address 10'0000000000). Merging ports 0, 9 (address 10'0000000000). Merging ports 0, 10 (address 10'0000000000). Merging ports 0, 11 (address 10'0000000000). Merging ports 0, 12 (address 10'0000000000). Merging ports 0, 13 (address 10'0000000000). Merging ports 0, 14 (address 10'0000000000). Merging ports 0, 15 (address 10'0000000000). Merging ports 0, 16 (address 10'0000000000). Merging ports 0, 17 (address 10'0000000000). Merging ports 0, 18 (address 10'0000000000). Merging ports 0, 19 (address 10'0000000000). Merging ports 0, 20 (address 10'0000000000). Merging ports 0, 21 (address 10'0000000000). Merging ports 0, 22 (address 10'0000000000). Merging ports 0, 23 (address 10'0000000000). Merging ports 0, 24 (address 10'0000000000). Merging ports 0, 25 (address 10'0000000000). Merging ports 0, 26 (address 10'0000000000). Merging ports 0, 27 (address 10'0000000000). Merging ports 0, 28 (address 10'0000000000). Merging ports 0, 29 (address 10'0000000000). Merging ports 0, 30 (address 10'0000000000). Merging ports 0, 31 (address 10'0000000000). Merging ports 0, 32 (address 10'0000000000). Merging ports 0, 33 (address 10'0000000000). Merging ports 0, 34 (address 10'0000000000). Merging ports 0, 35 (address 10'0000000000). Merging ports 0, 36 (address 10'0000000000). Merging ports 0, 37 (address 10'0000000000). Merging ports 0, 38 (address 10'0000000000). Merging ports 0, 39 (address 10'0000000000). Merging ports 0, 40 (address 10'0000000000). Merging ports 0, 41 (address 10'0000000000). Merging ports 0, 42 (address 10'0000000000). Merging ports 0, 43 (address 10'0000000000). Merging ports 0, 44 (address 10'0000000000). Merging ports 0, 45 (address 10'0000000000). Merging ports 0, 46 (address 10'0000000000). Merging ports 0, 47 (address 10'0000000000). Merging ports 0, 48 (address 10'0000000000). Merging ports 0, 49 (address 10'0000000000). Merging ports 0, 50 (address 10'0000000000). Merging ports 0, 51 (address 10'0000000000). Merging ports 0, 52 (address 10'0000000000). Merging ports 0, 53 (address 10'0000000000). Merging ports 0, 54 (address 10'0000000000). Merging ports 0, 55 (address 10'0000000000). Merging ports 0, 56 (address 10'0000000000). Merging ports 0, 57 (address 10'0000000000). Merging ports 0, 58 (address 10'0000000000). Merging ports 0, 59 (address 10'0000000000). Merging ports 0, 60 (address 10'0000000000). Merging ports 0, 61 (address 10'0000000000). Merging ports 0, 62 (address 10'0000000000). Merging ports 0, 63 (address 10'0000000000). Merging ports 0, 64 (address 10'0000000000). Merging ports 0, 65 (address 10'0000000000). Merging ports 0, 66 (address 10'0000000000). Merging ports 0, 67 (address 10'0000000000). Merging ports 0, 68 (address 10'0000000000). Merging ports 0, 69 (address 10'0000000000). Merging ports 0, 70 (address 10'0000000000). Merging ports 0, 71 (address 10'0000000000). Merging ports 0, 72 (address 10'0000000000). Merging ports 0, 73 (address 10'0000000000). Merging ports 0, 74 (address 10'0000000000). Merging ports 0, 75 (address 10'0000000000). Merging ports 0, 76 (address 10'0000000000). Merging ports 0, 77 (address 10'0000000000). Merging ports 0, 78 (address 10'0000000000). Merging ports 0, 79 (address 10'0000000000). Merging ports 0, 80 (address 10'0000000000). Merging ports 0, 81 (address 10'0000000000). Merging ports 0, 82 (address 10'0000000000). Merging ports 0, 83 (address 10'0000000000). Merging ports 0, 84 (address 10'0000000000). Merging ports 0, 85 (address 10'0000000000). Merging ports 0, 86 (address 10'0000000000). Merging ports 0, 87 (address 10'0000000000). Merging ports 0, 88 (address 10'0000000000). Merging ports 0, 89 (address 10'0000000000). Merging ports 0, 90 (address 10'0000000000). Merging ports 0, 91 (address 10'0000000000). Merging ports 0, 92 (address 10'0000000000). Merging ports 0, 93 (address 10'0000000000). Merging ports 0, 94 (address 10'0000000000). Merging ports 0, 95 (address 10'0000000000). Merging ports 0, 96 (address 10'0000000000). Merging ports 0, 97 (address 10'0000000000). Merging ports 0, 98 (address 10'0000000000). Merging ports 0, 99 (address 10'0000000000). Merging ports 0, 100 (address 10'0000000000). Merging ports 0, 101 (address 10'0000000000). Merging ports 0, 102 (address 10'0000000000). Merging ports 0, 103 (address 10'0000000000). Merging ports 0, 104 (address 10'0000000000). Merging ports 0, 105 (address 10'0000000000). Merging ports 0, 106 (address 10'0000000000). Merging ports 0, 107 (address 10'0000000000). Merging ports 0, 108 (address 10'0000000000). Merging ports 0, 109 (address 10'0000000000). Merging ports 0, 110 (address 10'0000000000). Merging ports 0, 111 (address 10'0000000000). Merging ports 0, 112 (address 10'0000000000). Merging ports 0, 113 (address 10'0000000000). Merging ports 0, 114 (address 10'0000000000). Merging ports 0, 115 (address 10'0000000000). Merging ports 0, 116 (address 10'0000000000). Merging ports 0, 117 (address 10'0000000000). Merging ports 0, 118 (address 10'0000000000). Merging ports 0, 119 (address 10'0000000000). Merging ports 0, 120 (address 10'0000000000). Merging ports 0, 121 (address 10'0000000000). Merging ports 0, 122 (address 10'0000000000). Merging ports 0, 123 (address 10'0000000000). Merging ports 0, 124 (address 10'0000000000). Merging ports 0, 125 (address 10'0000000000). Merging ports 0, 126 (address 10'0000000000). Merging ports 0, 127 (address 10'0000000000). Merging ports 0, 128 (address 10'0000000000). Merging ports 0, 129 (address 10'0000000000). Merging ports 0, 130 (address 10'0000000000). Merging ports 0, 131 (address 10'0000000000). Merging ports 0, 132 (address 10'0000000000). Merging ports 0, 133 (address 10'0000000000). Merging ports 0, 134 (address 10'0000000000). Merging ports 0, 135 (address 10'0000000000). Merging ports 0, 136 (address 10'0000000000). Merging ports 0, 137 (address 10'0000000000). Merging ports 0, 138 (address 10'0000000000). Merging ports 0, 139 (address 10'0000000000). Merging ports 0, 140 (address 10'0000000000). Merging ports 0, 141 (address 10'0000000000). Merging ports 0, 142 (address 10'0000000000). Merging ports 0, 143 (address 10'0000000000). Merging ports 0, 144 (address 10'0000000000). Merging ports 0, 145 (address 10'0000000000). Merging ports 0, 146 (address 10'0000000000). Merging ports 0, 147 (address 10'0000000000). Merging ports 0, 148 (address 10'0000000000). Merging ports 0, 149 (address 10'0000000000). Merging ports 0, 150 (address 10'0000000000). Merging ports 0, 151 (address 10'0000000000). Merging ports 0, 152 (address 10'0000000000). Merging ports 0, 153 (address 10'0000000000). Merging ports 0, 154 (address 10'0000000000). Merging ports 0, 155 (address 10'0000000000). Merging ports 0, 156 (address 10'0000000000). Merging ports 0, 157 (address 10'0000000000). Merging ports 0, 158 (address 10'0000000000). Merging ports 0, 159 (address 10'0000000000). Merging ports 0, 160 (address 10'0000000000). Merging ports 0, 161 (address 10'0000000000). Merging ports 0, 162 (address 10'0000000000). Merging ports 0, 163 (address 10'0000000000). Merging ports 0, 164 (address 10'0000000000). Merging ports 0, 165 (address 10'0000000000). Merging ports 0, 166 (address 10'0000000000). Merging ports 0, 167 (address 10'0000000000). Merging ports 0, 168 (address 10'0000000000). Merging ports 0, 169 (address 10'0000000000). Merging ports 0, 170 (address 10'0000000000). Merging ports 0, 171 (address 10'0000000000). Merging ports 0, 172 (address 10'0000000000). Merging ports 0, 173 (address 10'0000000000). Merging ports 0, 174 (address 10'0000000000). Merging ports 0, 175 (address 10'0000000000). Merging ports 0, 176 (address 10'0000000000). Merging ports 0, 177 (address 10'0000000000). Merging ports 0, 178 (address 10'0000000000). Merging ports 0, 179 (address 10'0000000000). Merging ports 0, 180 (address 10'0000000000). Merging ports 0, 181 (address 10'0000000000). Merging ports 0, 182 (address 10'0000000000). Merging ports 0, 183 (address 10'0000000000). Merging ports 0, 184 (address 10'0000000000). Merging ports 0, 185 (address 10'0000000000). Merging ports 0, 186 (address 10'0000000000). Merging ports 0, 187 (address 10'0000000000). Merging ports 0, 188 (address 10'0000000000). Merging ports 0, 189 (address 10'0000000000). Merging ports 0, 190 (address 10'0000000000). Merging ports 0, 191 (address 10'0000000000). Merging ports 0, 192 (address 10'0000000000). Merging ports 0, 193 (address 10'0000000000). Merging ports 0, 194 (address 10'0000000000). Merging ports 0, 195 (address 10'0000000000). Merging ports 0, 196 (address 10'0000000000). Merging ports 0, 197 (address 10'0000000000). Merging ports 0, 198 (address 10'0000000000). Merging ports 0, 199 (address 10'0000000000). Merging ports 0, 200 (address 10'0000000000). Merging ports 0, 201 (address 10'0000000000). Merging ports 0, 202 (address 10'0000000000). Merging ports 0, 203 (address 10'0000000000). Merging ports 0, 204 (address 10'0000000000). Merging ports 0, 205 (address 10'0000000000). Merging ports 0, 206 (address 10'0000000000). Merging ports 0, 207 (address 10'0000000000). Merging ports 0, 208 (address 10'0000000000). Merging ports 0, 209 (address 10'0000000000). Merging ports 0, 210 (address 10'0000000000). Merging ports 0, 211 (address 10'0000000000). Merging ports 0, 212 (address 10'0000000000). Merging ports 0, 213 (address 10'0000000000). Merging ports 0, 214 (address 10'0000000000). Merging ports 0, 215 (address 10'0000000000). Merging ports 0, 216 (address 10'0000000000). Merging ports 0, 217 (address 10'0000000000). Merging ports 0, 218 (address 10'0000000000). Merging ports 0, 219 (address 10'0000000000). Merging ports 0, 220 (address 10'0000000000). Merging ports 0, 221 (address 10'0000000000). Merging ports 0, 222 (address 10'0000000000). Merging ports 0, 223 (address 10'0000000000). Merging ports 0, 224 (address 10'0000000000). Merging ports 0, 225 (address 10'0000000000). Merging ports 0, 226 (address 10'0000000000). Merging ports 0, 227 (address 10'0000000000). Merging ports 0, 228 (address 10'0000000000). Merging ports 0, 229 (address 10'0000000000). Merging ports 0, 230 (address 10'0000000000). Merging ports 0, 231 (address 10'0000000000). Merging ports 0, 232 (address 10'0000000000). Merging ports 0, 233 (address 10'0000000000). Merging ports 0, 234 (address 10'0000000000). Merging ports 0, 235 (address 10'0000000000). Merging ports 0, 236 (address 10'0000000000). Merging ports 0, 237 (address 10'0000000000). Merging ports 0, 238 (address 10'0000000000). Merging ports 0, 239 (address 10'0000000000). Merging ports 0, 240 (address 10'0000000000). Merging ports 0, 241 (address 10'0000000000). Merging ports 0, 242 (address 10'0000000000). Merging ports 0, 243 (address 10'0000000000). Merging ports 0, 244 (address 10'0000000000). Merging ports 0, 245 (address 10'0000000000). Merging ports 0, 246 (address 10'0000000000). Merging ports 0, 247 (address 10'0000000000). Merging ports 0, 248 (address 10'0000000000). Merging ports 0, 249 (address 10'0000000000). Merging ports 0, 250 (address 10'0000000000). Merging ports 0, 251 (address 10'0000000000). Merging ports 0, 252 (address 10'0000000000). Merging ports 0, 253 (address 10'0000000000). Merging ports 0, 254 (address 10'0000000000). Merging ports 0, 255 (address 10'0000000000). Merging ports 0, 256 (address 10'0000000000). Merging ports 0, 257 (address 10'0000000000). Merging ports 0, 258 (address 10'0000000000). Merging ports 0, 259 (address 10'0000000000). Merging ports 0, 260 (address 10'0000000000). Merging ports 0, 261 (address 10'0000000000). Merging ports 0, 262 (address 10'0000000000). Merging ports 0, 263 (address 10'0000000000). Merging ports 0, 264 (address 10'0000000000). Merging ports 0, 265 (address 10'0000000000). Merging ports 0, 266 (address 10'0000000000). Merging ports 0, 267 (address 10'0000000000). Merging ports 0, 268 (address 10'0000000000). Merging ports 0, 269 (address 10'0000000000). Merging ports 0, 270 (address 10'0000000000). Merging ports 0, 271 (address 10'0000000000). Merging ports 0, 272 (address 10'0000000000). Merging ports 0, 273 (address 10'0000000000). Merging ports 0, 274 (address 10'0000000000). Merging ports 0, 275 (address 10'0000000000). Merging ports 0, 276 (address 10'0000000000). Merging ports 0, 277 (address 10'0000000000). Merging ports 0, 278 (address 10'0000000000). Merging ports 0, 279 (address 10'0000000000). Merging ports 0, 280 (address 10'0000000000). Merging ports 0, 281 (address 10'0000000000). Merging ports 0, 282 (address 10'0000000000). Merging ports 0, 283 (address 10'0000000000). Merging ports 0, 284 (address 10'0000000000). Merging ports 0, 285 (address 10'0000000000). Merging ports 0, 286 (address 10'0000000000). Merging ports 0, 287 (address 10'0000000000). Merging ports 0, 288 (address 10'0000000000). Merging ports 0, 289 (address 10'0000000000). Merging ports 0, 290 (address 10'0000000000). Merging ports 0, 291 (address 10'0000000000). Merging ports 0, 292 (address 10'0000000000). Merging ports 0, 293 (address 10'0000000000). Merging ports 0, 294 (address 10'0000000000). Merging ports 0, 295 (address 10'0000000000). Merging ports 0, 296 (address 10'0000000000). Merging ports 0, 297 (address 10'0000000000). Merging ports 0, 298 (address 10'0000000000). Merging ports 0, 299 (address 10'0000000000). Merging ports 0, 300 (address 10'0000000000). Merging ports 0, 301 (address 10'0000000000). Merging ports 0, 302 (address 10'0000000000). Merging ports 0, 303 (address 10'0000000000). Merging ports 0, 304 (address 10'0000000000). Merging ports 0, 305 (address 10'0000000000). Merging ports 0, 306 (address 10'0000000000). Merging ports 0, 307 (address 10'0000000000). Merging ports 0, 308 (address 10'0000000000). Merging ports 0, 309 (address 10'0000000000). Merging ports 0, 310 (address 10'0000000000). Merging ports 0, 311 (address 10'0000000000). Merging ports 0, 312 (address 10'0000000000). Merging ports 0, 313 (address 10'0000000000). Merging ports 0, 314 (address 10'0000000000). Merging ports 0, 315 (address 10'0000000000). Merging ports 0, 316 (address 10'0000000000). Merging ports 0, 317 (address 10'0000000000). Merging ports 0, 318 (address 10'0000000000). Merging ports 0, 319 (address 10'0000000000). Merging ports 0, 320 (address 10'0000000000). Merging ports 0, 321 (address 10'0000000000). Merging ports 0, 322 (address 10'0000000000). Merging ports 0, 323 (address 10'0000000000). Merging ports 0, 324 (address 10'0000000000). Merging ports 0, 325 (address 10'0000000000). Merging ports 0, 326 (address 10'0000000000). Merging ports 0, 327 (address 10'0000000000). Merging ports 0, 328 (address 10'0000000000). Merging ports 0, 329 (address 10'0000000000). Merging ports 0, 330 (address 10'0000000000). Merging ports 0, 331 (address 10'0000000000). Merging ports 0, 332 (address 10'0000000000). Merging ports 0, 333 (address 10'0000000000). Merging ports 0, 334 (address 10'0000000000). Merging ports 0, 335 (address 10'0000000000). Merging ports 0, 336 (address 10'0000000000). Merging ports 0, 337 (address 10'0000000000). Merging ports 0, 338 (address 10'0000000000). Merging ports 0, 339 (address 10'0000000000). Merging ports 0, 340 (address 10'0000000000). Merging ports 0, 341 (address 10'0000000000). Merging ports 0, 342 (address 10'0000000000). Merging ports 0, 343 (address 10'0000000000). Merging ports 0, 344 (address 10'0000000000). Merging ports 0, 345 (address 10'0000000000). Merging ports 0, 346 (address 10'0000000000). Merging ports 0, 347 (address 10'0000000000). Merging ports 0, 348 (address 10'0000000000). Merging ports 0, 349 (address 10'0000000000). Merging ports 0, 350 (address 10'0000000000). Merging ports 0, 351 (address 10'0000000000). Merging ports 0, 352 (address 10'0000000000). Merging ports 0, 353 (address 10'0000000000). Merging ports 0, 354 (address 10'0000000000). Merging ports 0, 355 (address 10'0000000000). Merging ports 0, 356 (address 10'0000000000). Merging ports 0, 357 (address 10'0000000000). Merging ports 0, 358 (address 10'0000000000). Merging ports 0, 359 (address 10'0000000000). Merging ports 0, 360 (address 10'0000000000). Merging ports 0, 361 (address 10'0000000000). Merging ports 0, 362 (address 10'0000000000). Merging ports 0, 363 (address 10'0000000000). Merging ports 0, 364 (address 10'0000000000). Merging ports 0, 365 (address 10'0000000000). Merging ports 0, 366 (address 10'0000000000). Merging ports 0, 367 (address 10'0000000000). Merging ports 0, 368 (address 10'0000000000). Merging ports 0, 369 (address 10'0000000000). Merging ports 0, 370 (address 10'0000000000). Merging ports 0, 371 (address 10'0000000000). Merging ports 0, 372 (address 10'0000000000). Merging ports 0, 373 (address 10'0000000000). Merging ports 0, 374 (address 10'0000000000). Merging ports 0, 375 (address 10'0000000000). Merging ports 0, 376 (address 10'0000000000). Merging ports 0, 377 (address 10'0000000000). Merging ports 0, 378 (address 10'0000000000). Merging ports 0, 379 (address 10'0000000000). Merging ports 0, 380 (address 10'0000000000). Merging ports 0, 381 (address 10'0000000000). Merging ports 0, 382 (address 10'0000000000). Merging ports 0, 383 (address 10'0000000000). Merging ports 0, 384 (address 10'0000000000). Merging ports 0, 385 (address 10'0000000000). Merging ports 0, 386 (address 10'0000000000). Merging ports 0, 387 (address 10'0000000000). Merging ports 0, 388 (address 10'0000000000). Merging ports 0, 389 (address 10'0000000000). Merging ports 0, 390 (address 10'0000000000). Merging ports 0, 391 (address 10'0000000000). Merging ports 0, 392 (address 10'0000000000). Merging ports 0, 393 (address 10'0000000000). Merging ports 0, 394 (address 10'0000000000). Merging ports 0, 395 (address 10'0000000000). Merging ports 0, 396 (address 10'0000000000). Merging ports 0, 397 (address 10'0000000000). Merging ports 0, 398 (address 10'0000000000). Merging ports 0, 399 (address 10'0000000000). Merging ports 0, 400 (address 10'0000000000). Merging ports 0, 401 (address 10'0000000000). Merging ports 0, 402 (address 10'0000000000). Merging ports 0, 403 (address 10'0000000000). Merging ports 0, 404 (address 10'0000000000). Merging ports 0, 405 (address 10'0000000000). Merging ports 0, 406 (address 10'0000000000). Merging ports 0, 407 (address 10'0000000000). Merging ports 0, 408 (address 10'0000000000). Merging ports 0, 409 (address 10'0000000000). Merging ports 0, 410 (address 10'0000000000). Merging ports 0, 411 (address 10'0000000000). Merging ports 0, 412 (address 10'0000000000). Merging ports 0, 413 (address 10'0000000000). Merging ports 0, 414 (address 10'0000000000). Merging ports 0, 415 (address 10'0000000000). Merging ports 0, 416 (address 10'0000000000). Merging ports 0, 417 (address 10'0000000000). Merging ports 0, 418 (address 10'0000000000). Merging ports 0, 419 (address 10'0000000000). Merging ports 0, 420 (address 10'0000000000). Merging ports 0, 421 (address 10'0000000000). Merging ports 0, 422 (address 10'0000000000). Merging ports 0, 423 (address 10'0000000000). Merging ports 0, 424 (address 10'0000000000). Merging ports 0, 425 (address 10'0000000000). Merging ports 0, 426 (address 10'0000000000). Merging ports 0, 427 (address 10'0000000000). Merging ports 0, 428 (address 10'0000000000). Merging ports 0, 429 (address 10'0000000000). Merging ports 0, 430 (address 10'0000000000). Merging ports 0, 431 (address 10'0000000000). Merging ports 0, 432 (address 10'0000000000). Merging ports 0, 433 (address 10'0000000000). Merging ports 0, 434 (address 10'0000000000). Merging ports 0, 435 (address 10'0000000000). Merging ports 0, 436 (address 10'0000000000). Merging ports 0, 437 (address 10'0000000000). Merging ports 0, 438 (address 10'0000000000). Merging ports 0, 439 (address 10'0000000000). Merging ports 0, 440 (address 10'0000000000). Merging ports 0, 441 (address 10'0000000000). Merging ports 0, 442 (address 10'0000000000). Merging ports 0, 443 (address 10'0000000000). Merging ports 0, 444 (address 10'0000000000). Merging ports 0, 445 (address 10'0000000000). Merging ports 0, 446 (address 10'0000000000). Merging ports 0, 447 (address 10'0000000000). Merging ports 0, 448 (address 10'0000000000). Merging ports 0, 449 (address 10'0000000000). Merging ports 0, 450 (address 10'0000000000). Merging ports 0, 451 (address 10'0000000000). Merging ports 0, 452 (address 10'0000000000). Merging ports 0, 453 (address 10'0000000000). Merging ports 0, 454 (address 10'0000000000). Merging ports 0, 455 (address 10'0000000000). Merging ports 0, 456 (address 10'0000000000). Merging ports 0, 457 (address 10'0000000000). Merging ports 0, 458 (address 10'0000000000). Merging ports 0, 459 (address 10'0000000000). Merging ports 0, 460 (address 10'0000000000). Merging ports 0, 461 (address 10'0000000000). Merging ports 0, 462 (address 10'0000000000). Merging ports 0, 463 (address 10'0000000000). Merging ports 0, 464 (address 10'0000000000). Merging ports 0, 465 (address 10'0000000000). Merging ports 0, 466 (address 10'0000000000). Merging ports 0, 467 (address 10'0000000000). Merging ports 0, 468 (address 10'0000000000). Merging ports 0, 469 (address 10'0000000000). Merging ports 0, 470 (address 10'0000000000). Merging ports 0, 471 (address 10'0000000000). Merging ports 0, 472 (address 10'0000000000). Merging ports 0, 473 (address 10'0000000000). Merging ports 0, 474 (address 10'0000000000). Merging ports 0, 475 (address 10'0000000000). Merging ports 0, 476 (address 10'0000000000). Merging ports 0, 477 (address 10'0000000000). Merging ports 0, 478 (address 10'0000000000). Merging ports 0, 479 (address 10'0000000000). Merging ports 0, 480 (address 10'0000000000). Merging ports 0, 481 (address 10'0000000000). Merging ports 0, 482 (address 10'0000000000). Merging ports 0, 483 (address 10'0000000000). Merging ports 0, 484 (address 10'0000000000). Merging ports 0, 485 (address 10'0000000000). Merging ports 0, 486 (address 10'0000000000). Merging ports 0, 487 (address 10'0000000000). Merging ports 0, 488 (address 10'0000000000). Merging ports 0, 489 (address 10'0000000000). Merging ports 0, 490 (address 10'0000000000). Merging ports 0, 491 (address 10'0000000000). Merging ports 0, 492 (address 10'0000000000). Merging ports 0, 493 (address 10'0000000000). Merging ports 0, 494 (address 10'0000000000). Merging ports 0, 495 (address 10'0000000000). Merging ports 0, 496 (address 10'0000000000). Merging ports 0, 497 (address 10'0000000000). Merging ports 0, 498 (address 10'0000000000). Merging ports 0, 499 (address 10'0000000000). Merging ports 0, 500 (address 10'0000000000). Merging ports 0, 501 (address 10'0000000000). Merging ports 0, 502 (address 10'0000000000). Merging ports 0, 503 (address 10'0000000000). Merging ports 0, 504 (address 10'0000000000). Merging ports 0, 505 (address 10'0000000000). Merging ports 0, 506 (address 10'0000000000). Merging ports 0, 507 (address 10'0000000000). Merging ports 0, 508 (address 10'0000000000). Merging ports 0, 509 (address 10'0000000000). Merging ports 0, 510 (address 10'0000000000). Merging ports 0, 511 (address 10'0000000000). Merging ports 0, 512 (address 10'0000000000). Merging ports 514, 515 (address 10'1000000010). Merging ports 516, 517 (address 10'1000000100). Merging ports 516, 518 (address 10'1000000100). Merging ports 516, 519 (address 10'1000000100). Merging ports 520, 521 (address 10'1000001000). Merging ports 520, 522 (address 10'1000001000). Merging ports 520, 523 (address 10'1000001000). Merging ports 520, 524 (address 10'1000001000). Merging ports 520, 525 (address 10'1000001000). Merging ports 520, 526 (address 10'1000001000). Merging ports 520, 527 (address 10'1000001000). Merging ports 528, 529 (address 10'1000010000). Merging ports 528, 530 (address 10'1000010000). Merging ports 528, 531 (address 10'1000010000). Merging ports 528, 532 (address 10'1000010000). Merging ports 528, 533 (address 10'1000010000). Merging ports 528, 534 (address 10'1000010000). Merging ports 528, 535 (address 10'1000010000). Merging ports 528, 536 (address 10'1000010000). Merging ports 528, 537 (address 10'1000010000). Merging ports 528, 538 (address 10'1000010000). Merging ports 528, 539 (address 10'1000010000). Merging ports 528, 540 (address 10'1000010000). Merging ports 528, 541 (address 10'1000010000). Merging ports 528, 542 (address 10'1000010000). Merging ports 528, 543 (address 10'1000010000). Merging ports 544, 545 (address 10'1000100000). Merging ports 544, 546 (address 10'1000100000). Merging ports 544, 547 (address 10'1000100000). Merging ports 544, 548 (address 10'1000100000). Merging ports 544, 549 (address 10'1000100000). Merging ports 544, 550 (address 10'1000100000). Merging ports 544, 551 (address 10'1000100000). Merging ports 544, 552 (address 10'1000100000). Merging ports 544, 553 (address 10'1000100000). Merging ports 544, 554 (address 10'1000100000). Merging ports 544, 555 (address 10'1000100000). Merging ports 544, 556 (address 10'1000100000). Merging ports 544, 557 (address 10'1000100000). Merging ports 544, 558 (address 10'1000100000). Merging ports 544, 559 (address 10'1000100000). Merging ports 544, 560 (address 10'1000100000). Merging ports 544, 561 (address 10'1000100000). Merging ports 544, 562 (address 10'1000100000). Merging ports 544, 563 (address 10'1000100000). Merging ports 544, 564 (address 10'1000100000). Merging ports 544, 565 (address 10'1000100000). Merging ports 544, 566 (address 10'1000100000). Merging ports 544, 567 (address 10'1000100000). Merging ports 544, 568 (address 10'1000100000). Merging ports 544, 569 (address 10'1000100000). Merging ports 544, 570 (address 10'1000100000). Merging ports 544, 571 (address 10'1000100000). Merging ports 544, 572 (address 10'1000100000). Merging ports 544, 573 (address 10'1000100000). Merging ports 544, 574 (address 10'1000100000). Merging ports 544, 575 (address 10'1000100000). Merging ports 576, 577 (address 10'1001000000). Merging ports 576, 578 (address 10'1001000000). Merging ports 576, 579 (address 10'1001000000). Merging ports 576, 580 (address 10'1001000000). Merging ports 576, 581 (address 10'1001000000). Merging ports 576, 582 (address 10'1001000000). Merging ports 576, 583 (address 10'1001000000). Merging ports 576, 584 (address 10'1001000000). Merging ports 576, 585 (address 10'1001000000). Merging ports 576, 586 (address 10'1001000000). Merging ports 576, 587 (address 10'1001000000). Merging ports 576, 588 (address 10'1001000000). Merging ports 576, 589 (address 10'1001000000). Merging ports 576, 590 (address 10'1001000000). Merging ports 576, 591 (address 10'1001000000). Merging ports 576, 592 (address 10'1001000000). Merging ports 576, 593 (address 10'1001000000). Merging ports 576, 594 (address 10'1001000000). Merging ports 576, 595 (address 10'1001000000). Merging ports 576, 596 (address 10'1001000000). Merging ports 576, 597 (address 10'1001000000). Merging ports 576, 598 (address 10'1001000000). Merging ports 576, 599 (address 10'1001000000). Merging ports 576, 600 (address 10'1001000000). Merging ports 576, 601 (address 10'1001000000). Merging ports 576, 602 (address 10'1001000000). Merging ports 576, 603 (address 10'1001000000). Merging ports 576, 604 (address 10'1001000000). Merging ports 576, 605 (address 10'1001000000). Merging ports 576, 606 (address 10'1001000000). Merging ports 576, 607 (address 10'1001000000). Merging ports 576, 608 (address 10'1001000000). Merging ports 576, 609 (address 10'1001000000). Merging ports 576, 610 (address 10'1001000000). Merging ports 576, 611 (address 10'1001000000). Merging ports 576, 612 (address 10'1001000000). Merging ports 576, 613 (address 10'1001000000). Merging ports 576, 614 (address 10'1001000000). Merging ports 576, 615 (address 10'1001000000). Merging ports 576, 616 (address 10'1001000000). Merging ports 576, 617 (address 10'1001000000). Merging ports 576, 618 (address 10'1001000000). Merging ports 576, 619 (address 10'1001000000). Merging ports 576, 620 (address 10'1001000000). Merging ports 576, 621 (address 10'1001000000). Merging ports 576, 622 (address 10'1001000000). Merging ports 576, 623 (address 10'1001000000). Merging ports 576, 624 (address 10'1001000000). Merging ports 576, 625 (address 10'1001000000). Merging ports 576, 626 (address 10'1001000000). Merging ports 576, 627 (address 10'1001000000). Merging ports 576, 628 (address 10'1001000000). Merging ports 576, 629 (address 10'1001000000). Merging ports 576, 630 (address 10'1001000000). Merging ports 576, 631 (address 10'1001000000). Merging ports 576, 632 (address 10'1001000000). Merging ports 576, 633 (address 10'1001000000). Merging ports 576, 634 (address 10'1001000000). Merging ports 576, 635 (address 10'1001000000). Merging ports 576, 636 (address 10'1001000000). Merging ports 576, 637 (address 10'1001000000). Merging ports 576, 638 (address 10'1001000000). Merging ports 576, 639 (address 10'1001000000). Merging ports 640, 641 (address 10'1010000000). Merging ports 640, 642 (address 10'1010000000). Merging ports 640, 643 (address 10'1010000000). Merging ports 640, 644 (address 10'1010000000). Merging ports 640, 645 (address 10'1010000000). Merging ports 640, 646 (address 10'1010000000). Merging ports 640, 647 (address 10'1010000000). Merging ports 640, 648 (address 10'1010000000). Merging ports 640, 649 (address 10'1010000000). Merging ports 640, 650 (address 10'1010000000). Merging ports 640, 651 (address 10'1010000000). Merging ports 640, 652 (address 10'1010000000). Merging ports 640, 653 (address 10'1010000000). Merging ports 640, 654 (address 10'1010000000). Merging ports 640, 655 (address 10'1010000000). Merging ports 640, 656 (address 10'1010000000). Merging ports 640, 657 (address 10'1010000000). Merging ports 640, 658 (address 10'1010000000). Merging ports 640, 659 (address 10'1010000000). Merging ports 640, 660 (address 10'1010000000). Merging ports 640, 661 (address 10'1010000000). Merging ports 640, 662 (address 10'1010000000). Merging ports 640, 663 (address 10'1010000000). Merging ports 640, 664 (address 10'1010000000). Merging ports 640, 665 (address 10'1010000000). Merging ports 640, 666 (address 10'1010000000). Merging ports 640, 667 (address 10'1010000000). Merging ports 640, 668 (address 10'1010000000). Merging ports 640, 669 (address 10'1010000000). Merging ports 640, 670 (address 10'1010000000). Merging ports 640, 671 (address 10'1010000000). Merging ports 640, 672 (address 10'1010000000). Merging ports 640, 673 (address 10'1010000000). Merging ports 640, 674 (address 10'1010000000). Merging ports 640, 675 (address 10'1010000000). Merging ports 640, 676 (address 10'1010000000). Merging ports 640, 677 (address 10'1010000000). Merging ports 640, 678 (address 10'1010000000). Merging ports 640, 679 (address 10'1010000000). Merging ports 640, 680 (address 10'1010000000). Merging ports 640, 681 (address 10'1010000000). Merging ports 640, 682 (address 10'1010000000). Merging ports 640, 683 (address 10'1010000000). Merging ports 640, 684 (address 10'1010000000). Merging ports 640, 685 (address 10'1010000000). Merging ports 640, 686 (address 10'1010000000). Merging ports 640, 687 (address 10'1010000000). Merging ports 640, 688 (address 10'1010000000). Merging ports 640, 689 (address 10'1010000000). Merging ports 640, 690 (address 10'1010000000). Merging ports 640, 691 (address 10'1010000000). Merging ports 640, 692 (address 10'1010000000). Merging ports 640, 693 (address 10'1010000000). Merging ports 640, 694 (address 10'1010000000). Merging ports 640, 695 (address 10'1010000000). Merging ports 640, 696 (address 10'1010000000). Merging ports 640, 697 (address 10'1010000000). Merging ports 640, 698 (address 10'1010000000). Merging ports 640, 699 (address 10'1010000000). Merging ports 640, 700 (address 10'1010000000). Merging ports 640, 701 (address 10'1010000000). Merging ports 640, 702 (address 10'1010000000). Merging ports 640, 703 (address 10'1010000000). Merging ports 640, 704 (address 10'1010000000). Merging ports 640, 705 (address 10'1010000000). Merging ports 640, 706 (address 10'1010000000). Merging ports 640, 707 (address 10'1010000000). Merging ports 640, 708 (address 10'1010000000). Merging ports 640, 709 (address 10'1010000000). Merging ports 640, 710 (address 10'1010000000). Merging ports 640, 711 (address 10'1010000000). Merging ports 640, 712 (address 10'1010000000). Merging ports 640, 713 (address 10'1010000000). Merging ports 640, 714 (address 10'1010000000). Merging ports 640, 715 (address 10'1010000000). Merging ports 640, 716 (address 10'1010000000). Merging ports 640, 717 (address 10'1010000000). Merging ports 640, 718 (address 10'1010000000). Merging ports 640, 719 (address 10'1010000000). Merging ports 640, 720 (address 10'1010000000). Merging ports 640, 721 (address 10'1010000000). Merging ports 640, 722 (address 10'1010000000). Merging ports 640, 723 (address 10'1010000000). Merging ports 640, 724 (address 10'1010000000). Merging ports 640, 725 (address 10'1010000000). Merging ports 640, 726 (address 10'1010000000). Merging ports 640, 727 (address 10'1010000000). Merging ports 640, 728 (address 10'1010000000). Merging ports 640, 729 (address 10'1010000000). Merging ports 640, 730 (address 10'1010000000). Merging ports 640, 731 (address 10'1010000000). Merging ports 640, 732 (address 10'1010000000). Merging ports 640, 733 (address 10'1010000000). Merging ports 640, 734 (address 10'1010000000). Merging ports 640, 735 (address 10'1010000000). Merging ports 640, 736 (address 10'1010000000). Merging ports 640, 737 (address 10'1010000000). Merging ports 640, 738 (address 10'1010000000). Merging ports 640, 739 (address 10'1010000000). Merging ports 640, 740 (address 10'1010000000). Merging ports 640, 741 (address 10'1010000000). Merging ports 640, 742 (address 10'1010000000). Merging ports 640, 743 (address 10'1010000000). Merging ports 640, 744 (address 10'1010000000). Merging ports 640, 745 (address 10'1010000000). Merging ports 640, 746 (address 10'1010000000). Merging ports 640, 747 (address 10'1010000000). Merging ports 640, 748 (address 10'1010000000). Merging ports 640, 749 (address 10'1010000000). Merging ports 640, 750 (address 10'1010000000). Merging ports 640, 751 (address 10'1010000000). Merging ports 640, 752 (address 10'1010000000). Merging ports 640, 753 (address 10'1010000000). Merging ports 640, 754 (address 10'1010000000). Merging ports 640, 755 (address 10'1010000000). Merging ports 640, 756 (address 10'1010000000). Merging ports 640, 757 (address 10'1010000000). Merging ports 640, 758 (address 10'1010000000). Merging ports 640, 759 (address 10'1010000000). Merging ports 640, 760 (address 10'1010000000). Merging ports 640, 761 (address 10'1010000000). Merging ports 640, 762 (address 10'1010000000). Merging ports 640, 763 (address 10'1010000000). Merging ports 640, 764 (address 10'1010000000). Merging ports 640, 765 (address 10'1010000000). Merging ports 640, 766 (address 10'1010000000). Merging ports 640, 767 (address 10'1010000000). Merging ports 768, 769 (address 10'1100000000). Merging ports 768, 770 (address 10'1100000000). Merging ports 768, 771 (address 10'1100000000). Merging ports 768, 772 (address 10'1100000000). Merging ports 768, 773 (address 10'1100000000). Merging ports 768, 774 (address 10'1100000000). Merging ports 768, 775 (address 10'1100000000). Merging ports 768, 776 (address 10'1100000000). Merging ports 768, 777 (address 10'1100000000). Merging ports 768, 778 (address 10'1100000000). Merging ports 768, 779 (address 10'1100000000). Merging ports 768, 780 (address 10'1100000000). Merging ports 768, 781 (address 10'1100000000). Merging ports 768, 782 (address 10'1100000000). Merging ports 768, 783 (address 10'1100000000). Merging ports 768, 784 (address 10'1100000000). Merging ports 768, 785 (address 10'1100000000). Merging ports 768, 786 (address 10'1100000000). Merging ports 768, 787 (address 10'1100000000). Merging ports 768, 788 (address 10'1100000000). Merging ports 768, 789 (address 10'1100000000). Merging ports 768, 790 (address 10'1100000000). Merging ports 768, 791 (address 10'1100000000). Merging ports 768, 792 (address 10'1100000000). Merging ports 768, 793 (address 10'1100000000). Merging ports 768, 794 (address 10'1100000000). Merging ports 768, 795 (address 10'1100000000). Merging ports 768, 796 (address 10'1100000000). Merging ports 768, 797 (address 10'1100000000). Merging ports 768, 798 (address 10'1100000000). Merging ports 768, 799 (address 10'1100000000). Merging ports 768, 800 (address 10'1100000000). Merging ports 768, 801 (address 10'1100000000). Merging ports 768, 802 (address 10'1100000000). Merging ports 768, 803 (address 10'1100000000). Merging ports 768, 804 (address 10'1100000000). Merging ports 768, 805 (address 10'1100000000). Merging ports 768, 806 (address 10'1100000000). Merging ports 768, 807 (address 10'1100000000). Merging ports 768, 808 (address 10'1100000000). Merging ports 768, 809 (address 10'1100000000). Merging ports 768, 810 (address 10'1100000000). Merging ports 768, 811 (address 10'1100000000). Merging ports 768, 812 (address 10'1100000000). Merging ports 768, 813 (address 10'1100000000). Merging ports 768, 814 (address 10'1100000000). Merging ports 768, 815 (address 10'1100000000). Merging ports 768, 816 (address 10'1100000000). Merging ports 768, 817 (address 10'1100000000). Merging ports 768, 818 (address 10'1100000000). Merging ports 768, 819 (address 10'1100000000). Merging ports 768, 820 (address 10'1100000000). Merging ports 768, 821 (address 10'1100000000). Merging ports 768, 822 (address 10'1100000000). Merging ports 768, 823 (address 10'1100000000). Merging ports 768, 824 (address 10'1100000000). Merging ports 768, 825 (address 10'1100000000). Merging ports 768, 826 (address 10'1100000000). Merging ports 768, 827 (address 10'1100000000). Merging ports 768, 828 (address 10'1100000000). Merging ports 768, 829 (address 10'1100000000). Merging ports 768, 830 (address 10'1100000000). Merging ports 768, 831 (address 10'1100000000). Merging ports 768, 832 (address 10'1100000000). Merging ports 768, 833 (address 10'1100000000). Merging ports 768, 834 (address 10'1100000000). Merging ports 768, 835 (address 10'1100000000). Merging ports 768, 836 (address 10'1100000000). Merging ports 768, 837 (address 10'1100000000). Merging ports 768, 838 (address 10'1100000000). Merging ports 768, 839 (address 10'1100000000). Merging ports 768, 840 (address 10'1100000000). Merging ports 768, 841 (address 10'1100000000). Merging ports 768, 842 (address 10'1100000000). Merging ports 768, 843 (address 10'1100000000). Merging ports 768, 844 (address 10'1100000000). Merging ports 768, 845 (address 10'1100000000). Merging ports 768, 846 (address 10'1100000000). Merging ports 768, 847 (address 10'1100000000). Merging ports 768, 848 (address 10'1100000000). Merging ports 768, 849 (address 10'1100000000). Merging ports 768, 850 (address 10'1100000000). Merging ports 768, 851 (address 10'1100000000). Merging ports 768, 852 (address 10'1100000000). Merging ports 768, 853 (address 10'1100000000). Merging ports 768, 854 (address 10'1100000000). Merging ports 768, 855 (address 10'1100000000). Merging ports 768, 856 (address 10'1100000000). Merging ports 768, 857 (address 10'1100000000). Merging ports 768, 858 (address 10'1100000000). Merging ports 768, 859 (address 10'1100000000). Merging ports 768, 860 (address 10'1100000000). Merging ports 768, 861 (address 10'1100000000). Merging ports 768, 862 (address 10'1100000000). Merging ports 768, 863 (address 10'1100000000). Merging ports 768, 864 (address 10'1100000000). Merging ports 768, 865 (address 10'1100000000). Merging ports 768, 866 (address 10'1100000000). Merging ports 768, 867 (address 10'1100000000). Merging ports 768, 868 (address 10'1100000000). Merging ports 768, 869 (address 10'1100000000). Merging ports 768, 870 (address 10'1100000000). Merging ports 768, 871 (address 10'1100000000). Merging ports 768, 872 (address 10'1100000000). Merging ports 768, 873 (address 10'1100000000). Merging ports 768, 874 (address 10'1100000000). Merging ports 768, 875 (address 10'1100000000). Merging ports 768, 876 (address 10'1100000000). Merging ports 768, 877 (address 10'1100000000). Merging ports 768, 878 (address 10'1100000000). Merging ports 768, 879 (address 10'1100000000). Merging ports 768, 880 (address 10'1100000000). Merging ports 768, 881 (address 10'1100000000). Merging ports 768, 882 (address 10'1100000000). Merging ports 768, 883 (address 10'1100000000). Merging ports 768, 884 (address 10'1100000000). Merging ports 768, 885 (address 10'1100000000). Merging ports 768, 886 (address 10'1100000000). Merging ports 768, 887 (address 10'1100000000). Merging ports 768, 888 (address 10'1100000000). Merging ports 768, 889 (address 10'1100000000). Merging ports 768, 890 (address 10'1100000000). Merging ports 768, 891 (address 10'1100000000). Merging ports 768, 892 (address 10'1100000000). Merging ports 768, 893 (address 10'1100000000). Merging ports 768, 894 (address 10'1100000000). Merging ports 768, 895 (address 10'1100000000). Merging ports 768, 896 (address 10'1100000000). Merging ports 768, 897 (address 10'1100000000). Merging ports 768, 898 (address 10'1100000000). Merging ports 768, 899 (address 10'1100000000). Merging ports 768, 900 (address 10'1100000000). Merging ports 768, 901 (address 10'1100000000). Merging ports 768, 902 (address 10'1100000000). Merging ports 768, 903 (address 10'1100000000). Merging ports 768, 904 (address 10'1100000000). Merging ports 768, 905 (address 10'1100000000). Merging ports 768, 906 (address 10'1100000000). Merging ports 768, 907 (address 10'1100000000). Merging ports 768, 908 (address 10'1100000000). Merging ports 768, 909 (address 10'1100000000). Merging ports 768, 910 (address 10'1100000000). Merging ports 768, 911 (address 10'1100000000). Merging ports 768, 912 (address 10'1100000000). Merging ports 768, 913 (address 10'1100000000). Merging ports 768, 914 (address 10'1100000000). Merging ports 768, 915 (address 10'1100000000). Merging ports 768, 916 (address 10'1100000000). Merging ports 768, 917 (address 10'1100000000). Merging ports 768, 918 (address 10'1100000000). Merging ports 768, 919 (address 10'1100000000). Merging ports 768, 920 (address 10'1100000000). Merging ports 768, 921 (address 10'1100000000). Merging ports 768, 922 (address 10'1100000000). Merging ports 768, 923 (address 10'1100000000). Merging ports 768, 924 (address 10'1100000000). Merging ports 768, 925 (address 10'1100000000). Merging ports 768, 926 (address 10'1100000000). Merging ports 768, 927 (address 10'1100000000). Merging ports 768, 928 (address 10'1100000000). Merging ports 768, 929 (address 10'1100000000). Merging ports 768, 930 (address 10'1100000000). Merging ports 768, 931 (address 10'1100000000). Merging ports 768, 932 (address 10'1100000000). Merging ports 768, 933 (address 10'1100000000). Merging ports 768, 934 (address 10'1100000000). Merging ports 768, 935 (address 10'1100000000). Merging ports 768, 936 (address 10'1100000000). Merging ports 768, 937 (address 10'1100000000). Merging ports 768, 938 (address 10'1100000000). Merging ports 768, 939 (address 10'1100000000). Merging ports 768, 940 (address 10'1100000000). Merging ports 768, 941 (address 10'1100000000). Merging ports 768, 942 (address 10'1100000000). Merging ports 768, 943 (address 10'1100000000). Merging ports 768, 944 (address 10'1100000000). Merging ports 768, 945 (address 10'1100000000). Merging ports 768, 946 (address 10'1100000000). Merging ports 768, 947 (address 10'1100000000). Merging ports 768, 948 (address 10'1100000000). Merging ports 768, 949 (address 10'1100000000). Merging ports 768, 950 (address 10'1100000000). Merging ports 768, 951 (address 10'1100000000). Merging ports 768, 952 (address 10'1100000000). Merging ports 768, 953 (address 10'1100000000). Merging ports 768, 954 (address 10'1100000000). Merging ports 768, 955 (address 10'1100000000). Merging ports 768, 956 (address 10'1100000000). Merging ports 768, 957 (address 10'1100000000). Merging ports 768, 958 (address 10'1100000000). Merging ports 768, 959 (address 10'1100000000). Merging ports 768, 960 (address 10'1100000000). Merging ports 768, 961 (address 10'1100000000). Merging ports 768, 962 (address 10'1100000000). Merging ports 768, 963 (address 10'1100000000). Merging ports 768, 964 (address 10'1100000000). Merging ports 768, 965 (address 10'1100000000). Merging ports 768, 966 (address 10'1100000000). Merging ports 768, 967 (address 10'1100000000). Merging ports 768, 968 (address 10'1100000000). Merging ports 768, 969 (address 10'1100000000). Merging ports 768, 970 (address 10'1100000000). Merging ports 768, 971 (address 10'1100000000). Merging ports 768, 972 (address 10'1100000000). Merging ports 768, 973 (address 10'1100000000). Merging ports 768, 974 (address 10'1100000000). Merging ports 768, 975 (address 10'1100000000). Merging ports 768, 976 (address 10'1100000000). Merging ports 768, 977 (address 10'1100000000). Merging ports 768, 978 (address 10'1100000000). Merging ports 768, 979 (address 10'1100000000). Merging ports 768, 980 (address 10'1100000000). Merging ports 768, 981 (address 10'1100000000). Merging ports 768, 982 (address 10'1100000000). Merging ports 768, 983 (address 10'1100000000). Merging ports 768, 984 (address 10'1100000000). Merging ports 768, 985 (address 10'1100000000). Merging ports 768, 986 (address 10'1100000000). Merging ports 768, 987 (address 10'1100000000). Merging ports 768, 988 (address 10'1100000000). Merging ports 768, 989 (address 10'1100000000). Merging ports 768, 990 (address 10'1100000000). Merging ports 768, 991 (address 10'1100000000). Merging ports 768, 992 (address 10'1100000000). Merging ports 768, 993 (address 10'1100000000). Merging ports 768, 994 (address 10'1100000000). Merging ports 768, 995 (address 10'1100000000). Merging ports 768, 996 (address 10'1100000000). Merging ports 768, 997 (address 10'1100000000). Merging ports 768, 998 (address 10'1100000000). Merging ports 768, 999 (address 10'1100000000). Merging ports 768, 1000 (address 10'1100000000). Merging ports 768, 1001 (address 10'1100000000). Merging ports 768, 1002 (address 10'1100000000). Merging ports 768, 1003 (address 10'1100000000). Merging ports 768, 1004 (address 10'1100000000). Merging ports 768, 1005 (address 10'1100000000). Merging ports 768, 1006 (address 10'1100000000). Merging ports 768, 1007 (address 10'1100000000). Merging ports 768, 1008 (address 10'1100000000). Merging ports 768, 1009 (address 10'1100000000). Merging ports 768, 1010 (address 10'1100000000). Merging ports 768, 1011 (address 10'1100000000). Merging ports 768, 1012 (address 10'1100000000). Merging ports 768, 1013 (address 10'1100000000). Merging ports 768, 1014 (address 10'1100000000). Merging ports 768, 1015 (address 10'1100000000). Merging ports 768, 1016 (address 10'1100000000). Merging ports 768, 1017 (address 10'1100000000). Merging ports 768, 1018 (address 10'1100000000). Merging ports 768, 1019 (address 10'1100000000). Merging ports 768, 1020 (address 10'1100000000). Merging ports 768, 1021 (address 10'1100000000). Merging ports 768, 1022 (address 10'1100000000). Consolidating write ports of memory top.Core.Data_memory.ram by address: Merging ports 1, 2 (address 10'1000000001). Merging ports 1, 3 (address 10'1000000000). Merging ports 1, 4 (address 10'1000000000). Merging ports 1, 5 (address 10'1000000000). Merging ports 1, 6 (address 10'1000000000). Merging ports 1, 7 (address 10'1000000000). Merging ports 1, 8 (address 10'1000000000). Merging ports 1, 9 (address 10'1000000000). Consolidating write ports of memory top.Core.Data_memory.ram by address: Consolidating write ports of memory top.Core.Data_memory.ram using sat-based resource sharing: 12.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 12.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 12.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 12.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 12.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). using FF mapping for memory top.Core.Data_memory.ram using FF mapping for memory top.Core.Instruction_memory.memory <suppressed ~56 debug messages> 12.27. Executing TECHMAP pass (map to technology primitives). 12.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 12.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 12.27.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 12.28. Executing OPT pass (performing simple optimizations). 12.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~182 debug messages> 12.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~78 debug messages> Removed a total of 26 cells. 12.28.3. Executing OPT_DFF pass (perform DFF optimizations). Handling always-active ARST on $flatten\Core.\Control_unit.$auto$proc_dlatch.cc:433:proc_dlatch$10490 ($dlatch) from module top (changing to const driver). Handling never-active EN on $auto$ff.cc:266:slice$12968 ($sdffe) from module top (connecting SRST instead). Handling always-active ARST on $flatten\Core.\Control_unit.$auto$proc_dlatch.cc:433:proc_dlatch$10700 ($dlatch) from module top (changing to const driver). Handling always-active ARST on $flatten\Core.\Control_unit.$auto$proc_dlatch.cc:433:proc_dlatch$10595 ($dlatch) from module top (changing to const driver). Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$12968 ($dffe) from module top. 12.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 9 unused cells and 173 unused wires. <suppressed ~10 debug messages> 12.28.5. Rerunning OPT passes. (Removed registers in this run.) 12.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~13 debug messages> 12.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.28.8. Executing OPT_DFF pass (perform DFF optimizations). 12.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 13 unused cells and 32 unused wires. <suppressed ~25 debug messages> 12.28.10. Finished fast OPT passes. 12.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory \Core.Instruction_memory.memory in module \top: created 256 $dff cells and 0 static cells of width 14. read interface: 0 $dff and 255 $mux cells. write interface: 0 write mux blocks. 12.30. Executing OPT pass (performing simple optimizations). 12.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~246 debug messages> 12.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/7 on $pmux $flatten\Core.\Alu_Control.$procmux$10463. dead port 2/7 on $pmux $flatten\Core.\Alu_Control.$procmux$10463. dead port 3/7 on $pmux $flatten\Core.\Alu_Control.$procmux$10463. dead port 4/7 on $pmux $flatten\Core.\Alu_Control.$procmux$10463. dead port 5/7 on $pmux $flatten\Core.\Alu_Control.$procmux$10463. dead port 1/6 on $pmux $flatten\Core.\Immediate_generator.$procmux$7258. dead port 3/6 on $pmux $flatten\Core.\Immediate_generator.$procmux$7258. dead port 4/6 on $pmux $flatten\Core.\Immediate_generator.$procmux$7258. dead port 5/6 on $pmux $flatten\Core.\Immediate_generator.$procmux$7258. dead port 6/6 on $pmux $flatten\Core.\Immediate_generator.$procmux$7258. dead port 1/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 2/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 3/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 4/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 5/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 6/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 7/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 8/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 9/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 10/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 11/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 12/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 13/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 14/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 15/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 16/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 17/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 18/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 19/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 20/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 21/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 22/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 23/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 24/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 25/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 26/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 27/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 28/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 29/32 on $pmux $flatten\Core.\registers.$procmux$7216. dead port 31/32 on $pmux $flatten\Core.\registers.$procmux$7216. Removed 40 multiplexer ports. <suppressed ~5 debug messages> 12.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][7][1]$13534: Old ports: A=14'00000000000111, B=14'x, Y=$memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 New ports: A=2'01, B=2'x, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [0] } New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [13:4] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [0] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [0] } Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][7][0]$13531: Old ports: A=14'11111111100000, B=14'00000001111000, Y=$memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 New ports: A=2'10, B=2'01, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [7] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [3] } New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [13:8] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [6:4] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [2:0] } = { $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [7] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [7] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [7] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [7] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [7] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [7] 2'11 $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [3] 3'000 } Consolidated identical input bits for $mux cell $flatten\Core.\Alu_Control.$procmux$10463: Old ports: A=4'0010, B=4'1000, Y=\Core.Alu.operation New ports: A=2'01, B=2'10, Y={ \Core.Alu.operation [3] \Core.Alu.operation [1] } New connections: { \Core.Alu.operation [2] \Core.Alu.operation [0] } = 2'00 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$13339: Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340, B=$memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341, Y=$memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [7] 1'1 $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$a$13340 [3] 1'0 }, B={ $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [3] $memory\Core.Instruction_memory.memory$rdmux[0][6][0]$b$13341 [0] }, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [5] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [3] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [0] } New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [13:8] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [6] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [4] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [5] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [3] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [0] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$13243: Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244, B=14'x, Y=$memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [7] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [5] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [3] $memory\Core.Instruction_memory.memory$rdmux[0][5][0]$a$13244 [0] }, B=4'x, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [5] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [3] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [0] } New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [13:8] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [6] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [4] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [5] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [3] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [0] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$13195: Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196, B=14'x, Y=$memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [7] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [5] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [3] $memory\Core.Instruction_memory.memory$rdmux[0][4][0]$a$13196 [0] }, B=4'x, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [5] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [3] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [0] } New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [13:8] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [6] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [4] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [5] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [3] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [0] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$13171: Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172, B=14'x, Y=$memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [7] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [5] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [3] $memory\Core.Instruction_memory.memory$rdmux[0][3][0]$a$13172 [0] }, B=4'x, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [5] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [3] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [0] } New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [13:8] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [6] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [4] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [5] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [3] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [0] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$13159: Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160, B=14'x, Y=$memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [7] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [5] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [3] $memory\Core.Instruction_memory.memory$rdmux[0][2][0]$a$13160 [0] }, B=4'x, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [5] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [3] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [0] } New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [13:8] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [6] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [4] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [5] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [3] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [0] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$13153: Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154, B=14'x, Y=$memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [7] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [5] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [3] $memory\Core.Instruction_memory.memory$rdmux[0][1][0]$a$13154 [0] }, B=4'x, Y={ $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [5] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [3] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [0] } New connections: { $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [13:8] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [6] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [4] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [2:1] } = { $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [5] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [3] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [0] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$13150: Old ports: A=$memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151, B=14'x, Y={ \Core.Immediate_generator.instruction [30:24] \Core.Immediate_generator.instruction [22:21] \Core.Immediate_generator.instruction [16] \Core.Immediate_generator.instruction [12] \Core.Immediate_generator.instruction [10:9] \Core.Immediate_generator.instruction [7] } New ports: A={ $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [7] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [5] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [3] $memory\Core.Instruction_memory.memory$rdmux[0][0][0]$a$13151 [0] }, B=4'x, Y={ \Core.Immediate_generator.instruction [24] \Core.Immediate_generator.instruction [21] \Core.Immediate_generator.instruction [12] \Core.Immediate_generator.instruction [7] } New connections: { \Core.Immediate_generator.instruction [30:25] \Core.Immediate_generator.instruction [22] \Core.Immediate_generator.instruction [16] \Core.Immediate_generator.instruction [10:9] } = { \Core.Immediate_generator.instruction [24] \Core.Immediate_generator.instruction [24] \Core.Immediate_generator.instruction [24] \Core.Immediate_generator.instruction [24] \Core.Immediate_generator.instruction [24] \Core.Immediate_generator.instruction [24] \Core.Immediate_generator.instruction [21] \Core.Immediate_generator.instruction [12] \Core.Immediate_generator.instruction [7] \Core.Immediate_generator.instruction [7] } Optimizing cells in module \top. Performed a total of 10 changes. 12.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.30.6. Executing OPT_DFF pass (perform DFF optimizations). 12.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 12 unused cells and 514 unused wires. <suppressed ~19 debug messages> 12.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~39 debug messages> 12.30.9. Rerunning OPT passes. (Maybe there is more to do..) 12.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/12 on $pmux $flatten\Core.\Alu.$procmux$10478. dead port 2/12 on $pmux $flatten\Core.\Alu.$procmux$10478. dead port 4/12 on $pmux $flatten\Core.\Alu.$procmux$10478. dead port 6/12 on $pmux $flatten\Core.\Alu.$procmux$10478. dead port 7/12 on $pmux $flatten\Core.\Alu.$procmux$10478. dead port 8/12 on $pmux $flatten\Core.\Alu.$procmux$10478. dead port 10/12 on $pmux $flatten\Core.\Alu.$procmux$10478. dead port 1/2 on $mux $flatten\Core.\Alu.$ternary$Pequeno-Risco-5/src/alu.v:25$10. dead port 2/2 on $mux $flatten\Core.\Alu.$ternary$Pequeno-Risco-5/src/alu.v:25$10. Removed 9 multiplexer ports. <suppressed ~4 debug messages> 12.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 12.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.30.13. Executing OPT_DFF pass (perform DFF optimizations). 12.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 9 unused cells and 31 unused wires. <suppressed ~10 debug messages> 12.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.30.16. Rerunning OPT passes. (Maybe there is more to do..) 12.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~4 debug messages> 12.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 12.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.30.20. Executing OPT_DFF pass (perform DFF optimizations). 12.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 12.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.30.23. Finished OPT passes. (There is nothing left to do.) 12.31. Executing TECHMAP pass (map to technology primitives). 12.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 12.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 12.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $not. Using template $paramod$constmap:d3d6ae620e2c152bc23f08938fd5d94ec5742fe7$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using template $paramod$b098bc6f249c0ac91c4d6e19d54b23c285914115\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $logic_or. No more expansions possible. <suppressed ~797 debug messages> 12.32. Executing OPT pass (performing simple optimizations). 12.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~422 debug messages> 12.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~84 debug messages> Removed a total of 28 cells. 12.32.3. Executing OPT_DFF pass (perform DFF optimizations). 12.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 423 unused cells and 344 unused wires. <suppressed ~424 debug messages> 12.32.5. Finished fast OPT passes. 12.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 12.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 12.35. Executing TECHMAP pass (map to technology primitives). 12.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 12.35.2. Continuing TECHMAP pass. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. No more expansions possible. <suppressed ~95 debug messages> 12.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~79 debug messages> 12.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 12.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top. 12.39. Executing ATTRMVCP pass (move or copy attributes). 12.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 9 unused cells and 147 unused wires. <suppressed ~10 debug messages> 12.41. Executing TECHMAP pass (map to technology primitives). 12.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 12.41.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 12.42. Executing ABC9 pass. 12.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 12.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 12.42.3. Executing SCC pass (detecting logic loops). Found 0 SCCs in module top. Found 0 SCCs. 12.42.4. Executing ABC9_OPS pass (helper functions for ABC9). 12.42.5. Executing PROC pass (convert processes to netlists). 12.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 12.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 12.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 12.42.5.4. Executing PROC_INIT pass (extract init attributes). 12.42.5.5. Executing PROC_ARST pass (detect async resets in processes). 12.42.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 12.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 12.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). 12.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs). 12.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 12.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 12.42.5.12. Executing OPT_EXPR pass (perform const folding). 12.42.6. Executing TECHMAP pass (map to technology primitives). 12.42.6.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 12.42.6.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~160 debug messages> 12.42.7. Executing OPT pass (performing simple optimizations). 12.42.7.1. Executing OPT_EXPR pass (perform const folding). 12.42.7.2. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 12.42.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Removed 0 multiplexer ports. 12.42.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Performed a total of 0 changes. 12.42.7.5. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 12.42.7.6. Executing OPT_DFF pass (perform DFF optimizations). 12.42.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). 12.42.7.8. Executing OPT_EXPR pass (perform const folding). 12.42.7.9. Finished OPT passes. (There is nothing left to do.) 12.42.8. Executing TECHMAP pass (map to technology primitives). 12.42.8.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 12.42.8.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~2 debug messages> 12.42.9. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 12.42.10. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 12.42.11. Executing ABC9_OPS pass (helper functions for ABC9). 12.42.12. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 12.42.13. Executing TECHMAP pass (map to technology primitives). 12.42.13.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 12.42.13.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $xor. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~199 debug messages> 12.42.14. Executing OPT pass (performing simple optimizations). 12.42.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~18 debug messages> 12.42.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 12.42.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 12.42.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 12.42.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.42.14.6. Executing OPT_DFF pass (perform DFF optimizations). 12.42.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 12.42.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.42.14.9. Rerunning OPT passes. (Maybe there is more to do..) 12.42.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 12.42.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 12.42.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 12.42.14.13. Executing OPT_DFF pass (perform DFF optimizations). 12.42.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 12.42.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 12.42.14.16. Finished OPT passes. (There is nothing left to do.) 12.42.15. Executing AIGMAP pass (map logic to AIG). Module top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 12.42.16. Executing AIGMAP pass (map logic to AIG). Module top: replaced 10 cells with 70 new cells, skipped 53 cells. replaced 1 cell types: 10 $_MUX_ not replaced 5 cell types: 11 $scopeinfo 11 $_NOT_ 8 $_AND_ 18 TRELLIS_FF 5 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 12.42.16.1. Executing ABC9_OPS pass (helper functions for ABC9). 12.42.16.2. Executing ABC9_OPS pass (helper functions for ABC9). 12.42.16.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 38 AND gates and 148 wires from module `top' to a netlist network with 21 inputs and 20 outputs. 12.42.16.4. Executing ABC9_EXE pass (technology mapping using ABC9). 12.42.16.5. Executing ABC9. Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 21/ 20 and = 18 lev = 2 (0.55) mem = 0.00 MB box = 5 bb = 0 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 21/ 20 and = 2 lev = 1 (0.28) mem = 0.00 MB ch = 0 box = 1 bb = 0 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 60. Obj = 140. Set = 636. CutMin = no ABC: Node = 2. Ch = 0. Total mem = 0.01 MB. Peak cut mem = 0.00 MB. ABC: P: Del = 630.00. Ar = 2.0. Edge = 4. Cut = 2. T = 0.00 sec ABC: P: Del = 630.00. Ar = 2.0. Edge = 4. Cut = 2. T = 0.00 sec ABC: P: Del = 630.00. Ar = 2.0. Edge = 4. Cut = 2. T = 0.00 sec ABC: F: Del = 630.00. Ar = 2.0. Edge = 4. Cut = 2. T = 0.00 sec ABC: A: Del = 630.00. Ar = 2.0. Edge = 4. Cut = 2. T = 0.00 sec ABC: A: Del = 630.00. Ar = 2.0. Edge = 4. Cut = 2. T = 0.00 sec ABC: Total time = 0.00 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: The network is not changed by "&mfs". ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 21/ 20 and = 2 lev = 1 (0.28) mem = 0.00 MB box = 1 bb = 0 ABC: Mapping (K=2) : lut = 2 edge = 4 lev = 1 (0.28) levB = 1 mem = 0.00 MB ABC: LUT = 2 : 2=2 100.0 % Ave = 2.00 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 0.00 seconds, total: 0.00 seconds 12.42.16.6. Executing AIGER frontend. <suppressed ~98 debug messages> Removed 1 unused cells and 49 unused wires. 12.42.16.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 11 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 1 ABC RESULTS: input signals: 7 ABC RESULTS: output signals: 5 Removing temp directory. 12.42.17. Executing TECHMAP pass (map to technology primitives). 12.42.17.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 12.42.17.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. No more expansions possible. <suppressed ~7 debug messages> Removed 9 unused cells and 135 unused wires. 12.43. Executing TECHMAP pass (map to technology primitives). 12.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 12.43.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. No more expansions possible. <suppressed ~122 debug messages> 12.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top. Removed 0 unused cells and 22 unused wires. 12.45. Executing AUTONAME pass. Renamed 41 objects in module top (5 iterations). <suppressed ~25 debug messages> 12.46. Executing HIERARCHY pass (managing design hierarchy). 12.46.1. Analyzing design hierarchy.. Top module: \top 12.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 12.47. Printing statistics. === top === Number of wires: 104 Number of wire bits: 1784 Number of public wires: 104 Number of public wire bits: 1784 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 33 $scopeinfo 11 CCU2C 1 LUT4 11 TRELLIS_FF 10 12.48. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 12.49. Executing JSON backend. Warnings: 1 unique messages, 1 total End of script. Logfile hash: 7c322c176a, CPU: user 12.99s system 0.15s, MEM: 276.95 MB peak Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) Time spent: 26% 1x opt_mem_priority (3 sec), 16% 3x proc_mux (2 sec), ... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (NextPNR) [Pipeline] sh + /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Pequeno-Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained Info: constraining clock net 'clk' to 25.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 13/43848 0% Info: logic LUTs: 11/43848 0% Info: carry LUTs: 2/43848 0% Info: RAM LUTs: 0/ 5481 0% Info: RAMW LUTs: 0/10962 0% Info: Total DFFs: 10/43848 0% Info: Packing IOs.. Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'. Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'. Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'. Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'. Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 4 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0x16e40db1 Info: Device utilisation: Info: TRELLIS_IO: 12/ 245 4% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 10/43848 0% Info: TRELLIS_COMB: 19/43848 0% Info: TRELLIS_RAMW: 0/ 5481 0% Info: Placed 12 cells based on constraints. Info: Creating initial analytic placement for 19 cells, random placement wirelen = 1474. Info: at initial placer iter 0, wirelen = 557 Info: at initial placer iter 1, wirelen = 540 Info: at initial placer iter 2, wirelen = 529 Info: at initial placer iter 3, wirelen = 530 Info: Running main analytical placer, max placement attempts per cell = 10000. Info: at iteration #1, type ALL: wirelen solved = 524, spread = 535, legal = 538; time = 0.01s Info: HeAP Placer Time: 0.05s Info: of which solving equations: 0.00s Info: of which spreading cells: 0.00s Info: of which strict legalisation: 0.00s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 14, wirelen = 538 Info: at iteration #3: temp = 0.000000, timing cost = 17, wirelen = 514 Info: SA placement time 0.00s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 130.87 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.34 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 11.32 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 32359, 32704) |* Info: [ 32704, 33049) |* Info: [ 33049, 33394) |* Info: [ 33394, 33739) | Info: [ 33739, 34084) |* Info: [ 34084, 34429) | Info: [ 34429, 34774) | Info: [ 34774, 35119) | Info: [ 35119, 35464) | Info: [ 35464, 35809) |* Info: [ 35809, 36154) | Info: [ 36154, 36499) | Info: [ 36499, 36844) |* Info: [ 36844, 37189) |* Info: [ 37189, 37534) | Info: [ 37534, 37879) |*** Info: [ 37879, 38224) |* Info: [ 38224, 38569) |* Info: [ 38569, 38914) |***** Info: [ 38914, 39259) |* Info: Checksum: 0xdb3cbec2 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 58 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 58 | 0 55 | 0 55 | 0| 0.03 0.03| Info: Routing complete. Info: Router1 time 0.03s Info: Checksum: 0x2307dfec Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source Core.Immediate_generator.instruction_TRELLIS_FF_Q.Q Info: 0.7 1.3 Net Core.instruction[10] (3,43) -> (2,43) Info: Sink Core.Alu.ALU_Result_LUT4_Z_1.C Info: Defined in: Info: Pequeno-Risco-5/src/registers.v:7.22-7.35 Info: 0.2 1.5 Source Core.Alu.ALU_Result_LUT4_Z_1.F Info: 3.6 5.1 Net Core.data_address[1] (2,43) -> (69,43) Info: Sink Core.registers.register15_TRELLIS_FF_Q_5.M Info: Defined in: Info: Pequeno-Risco-5/src/registers.v:8.23-8.32 Info: 0.0 5.1 Setup Core.registers.register15_TRELLIS_FF_Q_5.M Info: 0.8 ns logic, 4.3 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source reset$tr_io.O Info: 4.4 4.4 Net reset$TRELLIS_IO_IN (0,29) -> (69,43) Info: Sink Core.registers.register15_TRELLIS_FF_Q_5.LSR Info: Defined in: Info: Pequeno-Risco-5/fpga/ecp5/main.v:3.16-3.21 Info: 0.4 4.8 Setup Core.registers.register15_TRELLIS_FF_Q_5.LSR Info: 0.4 ns logic, 4.4 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>': Info: curr total Info: 0.5 0.5 Source Core.registers.register15_TRELLIS_FF_Q_4.Q Info: 1.7 2.2 Net Core.registers.register15[3] (4,44) -> (9,33) Info: Sink led_LUT4_Z.D Info: Defined in: Info: Pequeno-Risco-5/src/registers.v:29.12-29.22 Info: 0.2 2.4 Source led_LUT4_Z.F Info: 4.6 7.1 Net led[3]$TRELLIS_IO_OUT (9,33) -> (90,29) Info: Sink led[3]$tr_io.I Info: Defined in: Info: Pequeno-Risco-5/fpga/ecp5/main.v:6.22-6.25 Info: 0.8 ns logic, 6.3 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 196.58 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.80 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.07 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 34913, 35118) |** Info: [ 35118, 35323) | Info: [ 35323, 35528) | Info: [ 35528, 35733) |* Info: [ 35733, 35938) |* Info: [ 35938, 36143) | Info: [ 36143, 36348) | Info: [ 36348, 36553) | Info: [ 36553, 36758) |* Info: [ 36758, 36963) | Info: [ 36963, 37168) |* Info: [ 37168, 37373) |* Info: [ 37373, 37578) |* Info: [ 37578, 37783) |* Info: [ 37783, 37988) |** Info: [ 37988, 38193) | Info: [ 38193, 38398) |** Info: [ 38398, 38603) | Info: [ 38603, 38808) |** Info: [ 38808, 39013) |*** Info: Program finished normally. [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (ECPPACK) [Pipeline] sh + /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (openFPGAloader) [Pipeline] sh + /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 DAPLink CMSIS-DAP Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE Loading: [========= ] 17.04% Loading: [================== ] 34.07% Loading: [========================== ] 51.11% Loading: [=================================== ] 68.14% Loading: [=========================================== ] 85.18% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline Finished: SUCCESS