Started by timer
<span class="pipeline-new-node" nodeId="2" startId="2">[Pipeline] Start of Pipeline
</span><span class="pipeline-new-node" nodeId="3" startId="3" enclosingId="2">[Pipeline] node
</span><span class="pipeline-node-3">Running on <a href='/jenkins/computer/(built-in)/' class='jenkins-table__link model-link model-link--float'>Jenkins</a> in /var/jenkins_home/workspace/I2SRV64-SS-v1
</span><span class="pipeline-new-node" nodeId="4" startId="4" enclosingId="3">[Pipeline] {
</span><span class="pipeline-new-node" nodeId="5" startId="5" enclosingId="4">[Pipeline] stage
</span><span class="pipeline-new-node" nodeId="6" startId="6" enclosingId="5" label="Git Clone">[Pipeline] { (Git Clone)
</span><span class="pipeline-new-node" nodeId="7" enclosingId="6">[Pipeline] sh
</span><span class="pipeline-node-7">+ rm -rf *.xml
</span><span class="pipeline-new-node" nodeId="8" enclosingId="6">[Pipeline] sh
</span><span class="pipeline-node-8">+ rm -rf I2SRV64-SS-v1
</span><span class="pipeline-new-node" nodeId="9" enclosingId="6">[Pipeline] sh
</span><span class="pipeline-node-9">+ git clone --recursive --depth=1 <a href='https://github.com/RClabiisc/I2SRV64-SS-v1'>https://github.com/RClabiisc/I2SRV64-SS-v1</a> I2SRV64-SS-v1
Cloning into 'I2SRV64-SS-v1'...
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</span><span class="pipeline-new-node" nodeId="10" startId="6">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="11" startId="5">[Pipeline] // stage
</span><span class="pipeline-new-node" nodeId="12" startId="12" enclosingId="4">[Pipeline] stage
</span><span class="pipeline-new-node" nodeId="13" startId="13" enclosingId="12" label="Simulation">[Pipeline] { (Simulation)
</span><span class="pipeline-new-node" nodeId="14" startId="14" enclosingId="13">[Pipeline] dir
</span><span class="pipeline-node-14">Running in /var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1
</span><span class="pipeline-new-node" nodeId="15" startId="15" enclosingId="14">[Pipeline] {
</span><span class="pipeline-new-node" nodeId="16" enclosingId="15">[Pipeline] echo
</span><span class="pipeline-node-16">simulation not supported for mixed VHDL and Verilog files
</span><span class="pipeline-new-node" nodeId="17" startId="15">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="18" startId="14">[Pipeline] // dir
</span><span class="pipeline-new-node" nodeId="19" startId="13">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="20" startId="12">[Pipeline] // stage
</span><span class="pipeline-new-node" nodeId="21" startId="21" enclosingId="4">[Pipeline] stage
</span><span class="pipeline-new-node" nodeId="22" startId="22" enclosingId="21" label="Utilities">[Pipeline] { (Utilities)
</span><span class="pipeline-new-node" nodeId="23" startId="23" enclosingId="22">[Pipeline] dir
</span><span class="pipeline-node-23">Running in /var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1
</span><span class="pipeline-new-node" nodeId="24" startId="24" enclosingId="23">[Pipeline] {
</span><span class="pipeline-new-node" nodeId="25" enclosingId="24">[Pipeline] sh
</span><span class="pipeline-node-25">+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1 -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
WARNING: Error reading file /var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/axi64_to_axi32/hdl/axi_protocol_converter_v2_1_vl_rfs.v with encoding utf-8: 'utf-8' codec can't decode byte 0x92 in position 186616: invalid start byte
WARNING: Error reading file /var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/axi32_to_axilite32/hdl/axi_protocol_converter_v2_1_vl_rfs.v with encoding utf-8: 'utf-8' codec can't decode byte 0x92 in position 186616: invalid start byte
WARNING: Error reading file /var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/axi64_dramctrl_vc707/axi64_dramctrl_vc707/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_upsizer.v with encoding utf-8: 'utf-8' codec can't decode byte 0x92 in position 5409: invalid start byte
WARNING: Error reading file /var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/axi64_dramctrl_vc707/axi64_dramctrl_vc707/user_design/rtl/axi/mig_7series_v4_2_ddr_a_upsizer.v with encoding utf-8: 'utf-8' codec can't decode byte 0x92 in position 4154: invalid start byte
Trying to read file: /var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/AXI4lite_PBUS_XBar/hdl/axi_crossbar_v2_1_vl_rfs.v
Cache-related signals in PLRU32_TLB.v
Cache-related signals in PLRU4.v
Cache-related signals in core.v
Cache-related signals in Store_Queue.v
Possible cache file: DCache_Arbiter.v
Cache-related signals in DCache_Arbiter.v
Possible cache file: axi_master_interface_dcache.v
Cache-related signals in axi_master_interface_dcache.v
Possible cache file: axi_lite_master_interface_dcache.v
Cache-related signals in axi_lite_master_interface_dcache.v
Possible cache file: DCache.v
Possible cache file: DCache_Module.v
Cache-related signals in DCache_Module.v
Cache-related signals in dTLB.v
Cache-related signals in DTLB_port0_FSM.v
Cache-related signals in DTLB_port1_FSM.v
Cache-related signals in DTLB_top.v
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Cache-related signals in Issue_Unit_top.v
Cache-related signals in EU.v
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Cache-related signals in FMUL.v
Cache-related signals in FU_Load.v
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Cache-related signals in FALU.v
Cache-related signals in serialdiv.v
Cache-related signals in IDIV.v
Cache-related signals in RS_Branch.v
Cache-related signals in Dispatch_Unit_top.v
Cache-related signals in RS_System.v
Cache-related signals in RS_Mem.v
Cache-related signals in RS_FP.v
Cache-related signals in RS_INT.v
Cache-related signals in Rename_Unit_top.v
Cache-related signals in Free_List.v
Cache-related signals in RV64GC_Decoder.v
Cache-related signals in Spectag_Unit.v
Cache-related signals in Decoder_top.v
Cache-related signals in Bundle_Generator.v
Cache-related signals in Instruction_Buffer.v
Cache-related signals in Branch_Checker.v
Cache-related signals in uBTB.v
Cache-related signals in IFU_top.v
Cache-related signals in iTLB.v
Cache-related signals in axi_master_interface_1.v
Possible cache file: ICache.v
Cache-related signals in ICache.v
Cache-related signals in SysCtl_top.v
Cache-related signals in AXI_PLIC_SLAVE.v
Cache-related signals in CoreCFG_v1_0.v
Cache-related signals in CLINT_v1_0.v
Cache-related signals in IB_bmem_4x186b_sim_netlist.v
Cache-related signals in axi64_to_axi32_sim_netlist.v
Cache-related signals in axi64_to_axi32.v
Cache-related signals in axi_data_fifo_v2_1_vl_rfs.v
Cache-related signals in axi_protocol_converter_v2_1_vl_rfs.v
Cache-related signals in axi_infrastructure_v1_1_vl_rfs.v
Cache-related signals in axi_clock_converter_v2_1_vl_rfs.v
Cache-related signals in axi_register_slice_v2_1_vl_rfs.v
Cache-related signals in generic_baseblocks_v2_1_vl_rfs.v
Cache-related signals in axi_dwidth_converter_v2_1_vlsyn_rfs.v
Cache-related signals in axi32_to_axilite32.v
Cache-related signals in axi_data_fifo_v2_1_vl_rfs.v
Cache-related signals in axi_protocol_converter_v2_1_vl_rfs.v
Cache-related signals in axi_infrastructure_v1_1_vl_rfs.v
Cache-related signals in axi_register_slice_v2_1_vl_rfs.v
Cache-related signals in generic_baseblocks_v2_1_vl_rfs.v
Cache-related signals in BTB_bmem_256x127b_sim_netlist.v
Cache-related signals in axi64_dramctrl_vc707_sim_netlist.v
Cache-related signals in axi64_dramctrl_vc707.v
Cache-related signals in axi64_dramctrl_vc707_mig.v
Cache-related signals in axi64_dramctrl_vc707_mig_sim.v
Cache-related signals in mig_7series_v4_2_ddr_axi_upsizer.v
Cache-related signals in mig_7series_v4_2_ddr_carry_or.v
Cache-related signals in mig_7series_v4_2_axi_mc_b_channel.v
Cache-related signals in mig_7series_v4_2_ddr_w_upsizer.v
Cache-related signals in mig_7series_v4_2_ddr_comparator_sel.v
Cache-related signals in mig_7series_v4_2_axi_mc_simple_fifo.v
Cache-related signals in mig_7series_v4_2_axi_mc_ar_channel.v
Cache-related signals in mig_7series_v4_2_axi_mc_wr_cmd_fsm.v
Cache-related signals in mig_7series_v4_2_axi_mc_r_channel.v
Cache-related signals in mig_7series_v4_2_ddr_carry_and.v
Cache-related signals in mig_7series_v4_2_axi_mc_wrap_cmd.v
Cache-related signals in mig_7series_v4_2_ddr_comparator_sel_static.v
Cache-related signals in mig_7series_v4_2_ddr_carry_latch_and.v
Cache-related signals in mig_7series_v4_2_ddr_axic_register_slice.v
Cache-related signals in mig_7series_v4_2_ddr_carry_latch_or.v
Cache-related signals in mig_7series_v4_2_axi_mc_incr_cmd.v
Cache-related signals in mig_7series_v4_2_axi_mc_w_channel.v
Cache-related signals in mig_7series_v4_2_axi_ctrl_reg.v
Cache-related signals in mig_7series_v4_2_ddr_a_upsizer.v
Cache-related signals in mig_7series_v4_2_axi_ctrl_reg_bank.v
Cache-related signals in mig_7series_v4_2_ddr_axi_register_slice.v
Cache-related signals in mig_7series_v4_2_axi_ctrl_read.v
Cache-related signals in mig_7series_v4_2_ddr_command_fifo.v
Cache-related signals in mig_7series_v4_2_axi_mc_cmd_translator.v
Cache-related signals in mig_7series_v4_2_ddr_comparator.v
Cache-related signals in mig_7series_v4_2_ddr_r_upsizer.v
Cache-related signals in mig_7series_v4_2_axi_ctrl_write.v
Cache-related signals in mig_7series_v4_2_axi_ctrl_top.v
Cache-related signals in mig_7series_v4_2_axi_mc_fifo.v
Cache-related signals in mig_7series_v4_2_axi_mc_cmd_arbiter.v
Cache-related signals in mig_7series_v4_2_axi_mc_cmd_fsm.v
Cache-related signals in mig_7series_v4_2_axi_ctrl_addr_decode.v
Cache-related signals in mig_7series_v4_2_axi_mc_aw_channel.v
Cache-related signals in mig_7series_v4_2_axi_mc.v
Cache-related signals in mig_7series_v4_2_iodelay_ctrl.v
Cache-related signals in mig_7series_v4_2_clk_ibuf.v
Cache-related signals in mig_7series_v4_2_tempmon.v
Cache-related signals in mig_7series_v4_2_infrastructure.v
Cache-related signals in mig_7series_v4_2_rank_common.v
Cache-related signals in mig_7series_v4_2_bank_common.v
Cache-related signals in mig_7series_v4_2_round_robin_arb.v
Cache-related signals in mig_7series_v4_2_col_mach.v
Cache-related signals in mig_7series_v4_2_arb_mux.v
Cache-related signals in mig_7series_v4_2_bank_cntrl.v
Cache-related signals in mig_7series_v4_2_bank_state.v
Cache-related signals in mig_7series_v4_2_arb_row_col.v
Cache-related signals in mig_7series_v4_2_bank_mach.v
Cache-related signals in mig_7series_v4_2_mc.v
Cache-related signals in mig_7series_v4_2_rank_mach.v
Cache-related signals in mig_7series_v4_2_bank_queue.v
Cache-related signals in mig_7series_v4_2_arb_select.v
Cache-related signals in mig_7series_v4_2_bank_compare.v
Cache-related signals in mig_7series_v4_2_rank_cntrl.v
Cache-related signals in mig_7series_v4_2_ui_cmd.v
Cache-related signals in mig_7series_v4_2_ui_top.v
Cache-related signals in mig_7series_v4_2_ui_wr_data.v
Cache-related signals in mig_7series_v4_2_ui_rd_data.v
Cache-related signals in mig_7series_v4_2_ecc_merge_enc.v
Cache-related signals in mig_7series_v4_2_fi_xor.v
Cache-related signals in mig_7series_v4_2_ecc_dec_fix.v
Cache-related signals in mig_7series_v4_2_ecc_gen.v
Cache-related signals in mig_7series_v4_2_ecc_buf.v
Cache-related signals in mig_7series_v4_2_ddr_phy_init.v
Cache-related signals in mig_7series_v4_2_ddr_phy_wrcal.v
Cache-related signals in mig_7series_v4_2_poc_top.v
Cache-related signals in mig_7series_v4_2_ddr_phy_wrlvl.v
Cache-related signals in mig_7series_v4_2_ddr_skip_calib_tap.v
Cache-related signals in mig_7series_v4_2_ddr_phy_ocd_lim.v
Cache-related signals in mig_7series_v4_2_ddr_of_pre_fifo.v
Cache-related signals in mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v
Cache-related signals in mig_7series_v4_2_ddr_phy_ocd_mux.v
Cache-related signals in mig_7series_v4_2_ddr_mc_phy.v
Cache-related signals in mig_7series_v4_2_ddr_phy_dqs_found_cal.v
Cache-related signals in mig_7series_v4_2_ddr_calib_top.v
Cache-related signals in mig_7series_v4_2_poc_pd.v
Cache-related signals in mig_7series_v4_2_poc_meta.v
Cache-related signals in mig_7series_v4_2_ddr_mc_phy_wrapper.v
Cache-related signals in mig_7series_v4_2_ddr_phy_ocd_samp.v
Cache-related signals in mig_7series_v4_2_ddr_phy_ocd_data.v
Cache-related signals in mig_7series_v4_2_poc_edge_store.v
Cache-related signals in mig_7series_v4_2_ddr_phy_4lanes.v
Cache-related signals in mig_7series_v4_2_poc_tap_base.v
Cache-related signals in mig_7series_v4_2_ddr_byte_lane.v
Cache-related signals in mig_7series_v4_2_ddr_phy_tempmon.v
Cache-related signals in mig_7series_v4_2_ddr_byte_group_io.v
Cache-related signals in mig_7series_v4_2_ddr_phy_ocd_cntlr.v
Cache-related signals in mig_7series_v4_2_ddr_phy_ocd_edge.v
Cache-related signals in mig_7series_v4_2_ddr_if_post_fifo.v
Cache-related signals in mig_7series_v4_2_ddr_phy_top.v
Cache-related signals in mig_7series_v4_2_ddr_phy_prbs_rdlvl.v
Cache-related signals in mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v
Cache-related signals in mig_7series_v4_2_ddr_phy_rdlvl.v
Cache-related signals in mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v
Cache-related signals in mig_7series_v4_2_poc_cc.v
Cache-related signals in mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
Cache-related signals in mig_7series_v4_2_ddr_phy_oclkdelay_cal.v
Cache-related signals in mig_7series_v4_2_ddr_prbs_gen.v
Cache-related signals in mig_7series_v4_2_mem_intfc.v
Cache-related signals in mig_7series_v4_2_memc_ui_top_axi.v
Cache-related signals in AXI4lite_PBUS_XBar.v
Cache-related signals in axi_data_fifo_v2_1_vl_rfs.v
Cache-related signals in axi_infrastructure_v1_1_vl_rfs.v
Cache-related signals in axi_crossbar_v2_1_vl_rfs.v
Cache-related signals in axi_register_slice_v2_1_vl_rfs.v
Cache-related signals in generic_baseblocks_v2_1_vl_rfs.v
Cache-related signals in JTAG_to_AXI4_sim_netlist.v
Cache-related signals in JTAG_to_AXI4.v
Cache-related signals in fifo_generator_vlog_beh.v
Cache-related signals in dist_mem_gen_v8_0.v
Cache-related signals in AXIlite32_L3_XBar.v
Cache-related signals in axi_data_fifo_v2_1_vl_rfs.v
Cache-related signals in axi_infrastructure_v1_1_vl_rfs.v
Cache-related signals in axi_crossbar_v2_1_vl_rfs.v
Cache-related signals in axi_register_slice_v2_1_vl_rfs.v
Cache-related signals in generic_baseblocks_v2_1_vl_rfs.v
Cache-related signals in axi64_clkcnv_async_sim_netlist.v
Cache-related signals in axi64_clkcnv_async.v
Cache-related signals in axi_infrastructure_v1_1_vl_rfs.v
Cache-related signals in axi_clock_converter_v2_1_vl_rfs.v
Cache-related signals in InternalSRAM_8192x64b_sim_netlist.v
Cache-related signals in BootROM_2048x64b_sim_netlist.v
Cache-related signals in BootROM_2048x64b.v
Cache-related signals in blk_mem_gen_v8_4.v
Cache-related signals in PHT_bmem_4096x16b_sim_netlist.v
Cache-related signals in sys_clk_ctrl.v
Cache-related signals in sys_clk_ctrl_clk_wiz.v
Cache-related signals in AXI64_L2_XBar.v
Cache-related signals in axi_data_fifo_v2_1_vl_rfs.v
Cache-related signals in axi_infrastructure_v1_1_vl_rfs.v
Cache-related signals in axi_crossbar_v2_1_vl_rfs.v
Cache-related signals in axi_register_slice_v2_1_vl_rfs.v
Cache-related signals in generic_baseblocks_v2_1_vl_rfs.v
Results saved to /jenkins/processor_ci_utils/labels/I2SRV64-SS-v1.json
</span><span class="pipeline-new-node" nodeId="26" startId="24">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="27" startId="23">[Pipeline] // dir
</span><span class="pipeline-new-node" nodeId="28" startId="22">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="29" startId="21">[Pipeline] // stage
</span><span class="pipeline-new-node" nodeId="30" startId="30" enclosingId="4">[Pipeline] stage
</span><span class="pipeline-new-node" nodeId="31" startId="31" enclosingId="30" label="FPGA Build Pipeline">[Pipeline] { (FPGA Build Pipeline)
</span><span class="pipeline-new-node" nodeId="32" startId="32" enclosingId="31">[Pipeline] parallel
</span><span class="pipeline-new-node" nodeId="33" startId="33" enclosingId="32" label="Branch: digilent_arty_a7_100t">[Pipeline] { (Branch: digilent_arty_a7_100t)
</span><span class="pipeline-new-node" nodeId="34" startId="34" enclosingId="33">[Pipeline] stage
</span><span class="pipeline-new-node" nodeId="35" startId="35" enclosingId="34" label="digilent_arty_a7_100t">[Pipeline] { (digilent_arty_a7_100t)
</span><span class="pipeline-new-node" nodeId="36" startId="36" enclosingId="35">[Pipeline] lock
</span><span class="pipeline-node-36">Trying to acquire lock on [Resource: digilent_arty_a7_100t]
Resource [digilent_arty_a7_100t] did not exist. Created.
Lock acquired on [Resource: digilent_arty_a7_100t]
</span><span class="pipeline-new-node" nodeId="37" startId="37" enclosingId="36">[Pipeline] {
</span><span class="pipeline-new-node" nodeId="38" startId="38" enclosingId="37">[Pipeline] stage
</span><span class="pipeline-new-node" nodeId="39" startId="39" enclosingId="38" label="Synthesis and PnR">[Pipeline] { (Synthesis and PnR)
</span><span class="pipeline-new-node" nodeId="40" startId="40" enclosingId="39">[Pipeline] dir
</span><span class="pipeline-node-40">Running in /var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1
</span><span class="pipeline-new-node" nodeId="41" startId="41" enclosingId="40">[Pipeline] {
</span><span class="pipeline-new-node" nodeId="42" enclosingId="41">[Pipeline] echo
</span><span class="pipeline-node-42">Starting synthesis for FPGA digilent_arty_a7_100t.
</span><span class="pipeline-new-node" nodeId="43" enclosingId="41">[Pipeline] sh
</span><span class="pipeline-node-43">+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p I2SRV64-SS-v1 -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:932]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_lib_fn.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:953]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:999]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_lib_fn.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1013]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1053]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1111]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1190]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1284]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1402]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_lib_fn.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1595]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_lib_fn.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1865]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:1905]
ERROR: [Synth 8-9263] cannot open include file 'ltlib_v1_0_0_ver.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:2005]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:2169]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/ltlib_v1_0_vl_rfs.v:2193]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/xsdbs_v1_0_vl_rfs.v:23]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/xsdbs_v1_0_vl_rfs.v:77]
ERROR: [Synth 8-9263] cannot open include file 'xsdbs_v1_0_2_i2x.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/xsdbs_v1_0_vl_rfs.v:262]
ERROR: [Synth 8-9263] cannot open include file 'xsdbs_v1_0_2_i2x.vh' [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/JTAG_to_AXI4/hdl/xsdbs_v1_0_vl_rfs.v:382]
ERROR: [Synth 8-5832] source file was generated for simulation and is not permitted as input to synthesis [/var/jenkins_home/workspace/I2SRV64-SS-v1/I2SRV64-SS-v1/Hardware_Source_Files/IP/AXI64_L2_XBar/AXI64_L2_XBar_sim_netlist.v:16]
ERROR: [Synth 8-439] module 'uart_rx' not found [/eda/processor-ci-controller/modules/uart.sv:260]
ERROR: [Synth 8-6156] failed synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/I2SRV64-SS-v1.sv:5]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in &lt;module&gt;
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 296, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
</span><span class="pipeline-new-node" nodeId="44" startId="41">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="45" startId="40">[Pipeline] // dir
</span><span class="pipeline-new-node" nodeId="46" startId="39">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="47" startId="38">[Pipeline] // stage
</span><span class="pipeline-new-node" nodeId="48" startId="48" enclosingId="37">[Pipeline] stage
</span><span class="pipeline-new-node" nodeId="49" startId="49" enclosingId="48" label="Flash digilent_arty_a7_100t">[Pipeline] { (Flash digilent_arty_a7_100t)
</span>Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s)
<span class="pipeline-new-node" nodeId="50" enclosingId="49">[Pipeline] getContext
</span><span class="pipeline-new-node" nodeId="51" startId="49">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="52" startId="48">[Pipeline] // stage
</span><span class="pipeline-new-node" nodeId="53" startId="53" enclosingId="37">[Pipeline] stage
</span><span class="pipeline-new-node" nodeId="54" startId="54" enclosingId="53" label="Test digilent_arty_a7_100t">[Pipeline] { (Test digilent_arty_a7_100t)
</span>Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s)
<span class="pipeline-new-node" nodeId="55" enclosingId="54">[Pipeline] getContext
</span><span class="pipeline-new-node" nodeId="56" startId="54">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="57" startId="53">[Pipeline] // stage
</span><span class="pipeline-new-node" nodeId="58" startId="37">[Pipeline] }
</span><span class="pipeline-node-58">Lock released on resource [Resource: digilent_arty_a7_100t]
</span><span class="pipeline-new-node" nodeId="59" startId="36">[Pipeline] // lock
</span><span class="pipeline-new-node" nodeId="60" startId="35">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="61" startId="34">[Pipeline] // stage
</span><span class="pipeline-new-node" nodeId="62" startId="33">[Pipeline] }
</span><span class="pipeline-node-62">Failed in branch digilent_arty_a7_100t
</span><span class="pipeline-new-node" nodeId="63" startId="32">[Pipeline] // parallel
</span><span class="pipeline-new-node" nodeId="64" startId="31">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="65" startId="30">[Pipeline] // stage
</span><span class="pipeline-new-node" nodeId="66" startId="66" enclosingId="4">[Pipeline] stage
</span><span class="pipeline-new-node" nodeId="67" startId="67" enclosingId="66" label="Declarative: Post Actions">[Pipeline] { (Declarative: Post Actions)
</span><span class="pipeline-new-node" nodeId="68" enclosingId="67">[Pipeline] junit
</span><span class="pipeline-node-68">Recording test results
[Checks API] No suitable checks publisher found.
</span><span class="pipeline-new-node" nodeId="69" startId="67">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="70" startId="66">[Pipeline] // stage
</span><span class="pipeline-new-node" nodeId="71" startId="4">[Pipeline] }
</span><span class="pipeline-new-node" nodeId="72" startId="3">[Pipeline] // node
</span><span class="pipeline-new-node" nodeId="73" startId="2">[Pipeline] End of Pipeline
</span>ERROR: script returned exit code 1
Finished: FAILURE