Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Sun May 11 21:23:12 2025
| Host         : 89852011558b running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : processorci_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |   128 |
|    Minimum number of control sets                        |   128 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   127 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |   128 |
| >= 0 to < 4        |     3 |
| >= 4 to < 6        |     8 |
| >= 6 to < 8        |     2 |
| >= 8 to < 10       |    12 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     1 |
| >= 16              |    95 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              95 |           40 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |             528 |          188 |
| Yes          | No                    | No                     |            1788 |          942 |
| Yes          | No                    | Yes                    |              32 |            8 |
| Yes          | Yes                   | No                     |            1070 |          377 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+-------------------------+---------------------------------------------------------------------------+---------------------------------------------------------+------------------+----------------+--------------+
|       Clock Signal      |                               Enable Signal                               |                     Set/Reset Signal                    | Slice Load Count | Bel Load Count | Bels / Slice |
+-------------------------+---------------------------------------------------------------------------+---------------------------------------------------------+------------------+----------------+--------------+
|  clk_IBUF_BUFG          |                                                                           |                                                         |                1 |              1 |         1.00 |
|  clk_o_BUFG             | u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                               | u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/First_Stage/IFID_IR_o[31]_i_2_n_0                            |                                                         |                2 |              2 |         1.00 |
|  clk_o_BUFG             | u_Controller/Uart/i_uart_rx/next_bit                                      | u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1__0_n_0   |                1 |              4 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/FSM_sequential_unaligned_access_state[3]_i_1_n_0 | u_Controller/Interpreter/rst_core                       |                2 |              4 |         2.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/core_reset_reg_0[0]                              |                                                         |                1 |              4 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/First_Stage/IFID_IR_o[31]_i_2_n_0                            | Processor/N1/First_Stage/IFID_IR_o[5]_i_1_n_0           |                2 |              4 |         2.00 |
|  clk_o_BUFG             | u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0                     | u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  clk_o_BUFG             | ResetBootSystem/counter                                                   |                                                         |                2 |              4 |         2.00 |
|  clk_o_BUFG             | u_Controller/Uart/i_uart_tx/E[0]                                          |                                                         |                1 |              4 |         4.00 |
|  clk_o_BUFG             | u_Controller/Interpreter/return_state                                     | ResetBootSystem/rst_o_reg_0                             |                3 |              5 |         1.67 |
|  clk_o_BUFG             |                                                                           |                                                         |                3 |              6 |         2.00 |
|  clk_o_BUFG             | u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0                       | ResetBootSystem/rst_o_reg_0                             |                2 |              7 |         3.50 |
|  clk_o_BUFG             | u_Controller/Uart/i_uart_rx/E[0]                                          | ResetBootSystem/rst_o_reg_0                             |                1 |              8 |         8.00 |
|  clk_o_BUFG             | u_Controller/Uart/uart_tx_en                                              | ResetBootSystem/rst_o_reg_0                             |                1 |              8 |         8.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/Merged_Word_o[7]_i_1_n_0                         |                                                         |                3 |              8 |         2.67 |
|  clk_o_BUFG             | u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0]            | ResetBootSystem/rst_o_reg_0                             |                1 |              8 |         8.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/Merged_Word_o[15]_i_1_n_0                        |                                                         |                6 |              8 |         1.33 |
|  ClkDivider/clk_o_pulse |                                                                           | u_Controller/Interpreter/SR[0]                          |                3 |              8 |         2.67 |
|  clk_o_BUFG             | u_Controller/Interpreter/accumulator[7]_i_1_n_0                           | ResetBootSystem/rst_o_reg_0                             |                2 |              8 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/EXMEM_mem_data_value[15]_i_1_n_0                 |                                                         |                7 |              8 |         1.14 |
|  clk_o_BUFG             | u_Controller/Interpreter/counter                                          | ResetBootSystem/rst_o_reg_0                             |                3 |              8 |         2.67 |
|  clk_o_BUFG             | u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0                       | ResetBootSystem/rst_o_reg_0                             |                1 |              8 |         8.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/EXMEM_mem_data_value[7]_i_1_n_0                  |                                                         |                3 |              8 |         2.67 |
|  clk_o_BUFG             | u_Controller/Uart/i_uart_rx/recieved_data0                                | u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                2 |              8 |         4.00 |
|  clk_o_BUFG             | u_Controller/Uart/i_uart_rx/cycle_counter0                                | u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0 |                3 |             10 |         3.33 |
|  clk_o_BUFG             | u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                               | ResetBootSystem/SR[0]                                   |                3 |             10 |         3.33 |
|  clk_o_BUFG             | u_Controller/Uart/rx_fifo/read_ptr0                                       | ResetBootSystem/rst_o_reg_0                             |                3 |             11 |         3.67 |
|  clk_o_BUFG             | u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                             | ResetBootSystem/rst_o_reg_0                             |                3 |             11 |         3.67 |
|  clk_o_BUFG             | u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0                   |                                                         |                2 |             12 |         6.00 |
|  clk_o_BUFG             | u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0                      |                                                         |                2 |             12 |         6.00 |
|  clk_o_BUFG             | u_Controller/Interpreter/address[31]_i_1_n_0                              |                                                         |                5 |             12 |         2.40 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/Mdu/FSM_onehot_state_mul[1]_i_1_n_0             | u_Controller/Interpreter/rst_core                       |                6 |             15 |         2.50 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/EXMEM_mem_data_value[31]_i_1_n_0                 |                                                         |               10 |             16 |         1.60 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/Merged_Word_o[31]_i_1_n_0                        |                                                         |                8 |             16 |         2.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/EXMEMIR_o[14]_i_2_n_0                            | Processor/N1/Third_Stage/EXMEMIR_o[14]_i_1_n_0          |                8 |             23 |         2.88 |
|  clk_o_BUFG             | u_Controller/Interpreter/num_of_pages                                     | ResetBootSystem/rst_o_reg_0                             |                5 |             24 |         4.80 |
|  clk_o_BUFG             | u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0               |                                                         |                9 |             24 |         2.67 |
|  clk_o_BUFG             | u_Controller/Interpreter/timeout                                          | ResetBootSystem/rst_o_reg_0                             |                8 |             24 |         3.00 |
|  clk_o_BUFG             | u_Controller/Interpreter/memory_page_number[23]_i_2_n_0                   | u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                7 |             24 |         3.43 |
|  clk_o_BUFG             | u_Controller/Interpreter/accumulator0                                     | ResetBootSystem/rst_o_reg_0                             |                4 |             24 |         6.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/First_Stage/IFID_IR_o[31]_i_2_n_0                            | Processor/N1/First_Stage/IFID_IR_o[31]_i_1_n_0          |               18 |             26 |         1.44 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_11[0]                           |                                                         |               19 |             32 |         1.68 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_14[0]                           |                                                         |               22 |             32 |         1.45 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_12[0]                           |                                                         |               20 |             32 |         1.60 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_10[0]                           |                                                         |               18 |             32 |         1.78 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/IDEXIR_o_reg[23]_0[0]                           | u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_16[0]                           |                                                         |               17 |             32 |         1.88 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_27[0]                           |                                                         |               19 |             32 |         1.68 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_24[0]                           |                                                         |               22 |             32 |         1.45 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/Mdu/mul_ready_o                                 | u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_18[0]                           |                                                         |               15 |             32 |         2.13 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_19[0]                           |                                                         |               21 |             32 |         1.52 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_9[0]                            |                                                         |               16 |             32 |         2.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/Mdu/DIV_RD[31]_i_1_n_0                          |                                                         |               12 |             32 |         2.67 |
|  ClkDivider/clk_o_pulse | Processor/N1/First_Stage/IFID_PC_o[31]_i_2_n_0                            | Processor/N1/First_Stage/IFID_PC_o[31]_i_1_n_0          |                9 |             32 |         3.56 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_17[0]                           |                                                         |               22 |             32 |         1.45 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_1[0]                            |                                                         |               21 |             32 |         1.52 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/EXMEMALUOut_o[31]_i_1_n_0                        |                                                         |               16 |             32 |         2.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_2[0]                            |                                                         |               23 |             32 |         1.39 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_7[0]                            |                                                         |               17 |             32 |         1.88 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_5[0]                            |                                                         |               25 |             32 |         1.28 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_20[0]                           |                                                         |               21 |             32 |         1.52 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_3[0]                            |                                                         |               23 |             32 |         1.39 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_21[0]                           |                                                         |               24 |             32 |         1.33 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_23[0]                           |                                                         |               23 |             32 |         1.39 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_22[0]                           |                                                         |               20 |             32 |         1.60 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_4[0]                            |                                                         |               19 |             32 |         1.68 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_13[0]                           |                                                         |               19 |             32 |         1.68 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_6[0]                            |                                                         |               17 |             32 |         1.88 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_0[0]                            |                                                         |               23 |             32 |         1.39 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/E[0]                                            |                                                         |               19 |             32 |         1.68 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/Data_Address[0]_i_1_n_0                          |                                                         |                8 |             32 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_25[0]                           |                                                         |               20 |             32 |         1.60 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_29[0]                           |                                                         |               23 |             32 |         1.39 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_8[0]                            |                                                         |               18 |             32 |         1.78 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_26[0]                           |                                                         |               20 |             32 |         1.60 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_28[0]                           |                                                         |               25 |             32 |         1.28 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/Mdu/dividendo[31]_i_1_n_0                       |                                                         |               12 |             32 |         2.67 |
|  clk_o_BUFG             | u_Controller/Interpreter/read_buffer                                      | ResetBootSystem/rst_o_reg_0                             |               14 |             32 |         2.29 |
|  clk_o_BUFG             | u_Controller/Uart/rx_fifo/E[0]                                            | ResetBootSystem/rst_o_reg_0                             |                7 |             32 |         4.57 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/reg_wr_en_o_reg_15[0]                           |                                                         |               17 |             32 |         1.88 |
|  clk_o_BUFG             | u_Controller/Interpreter/write_data[31]_i_1_n_0                           |                                                         |               13 |             32 |         2.46 |
|  clk_o_BUFG             | u_Controller/Interpreter/timeout_counter                                  | ResetBootSystem/rst_o_reg_0                             |                9 |             32 |         3.56 |
|  clk_o_BUFG             | u_Controller/Interpreter/communication_write_data[31]_i_1_n_0             |                                                         |                8 |             32 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/M1/write_data[31]_i_1__0_n_0                                    |                                                         |               15 |             32 |         2.13 |
|  ClkDivider/clk_o_pulse | Processor/M1/i_cache_read_data[31]_i_1_n_0                                |                                                         |               13 |             32 |         2.46 |
|  ClkDivider/clk_o_pulse | Processor/M1/d_cache_read_data[31]_i_1_n_0                                |                                                         |               12 |             32 |         2.67 |
|  clk_o_BUFG             | u_Controller/Uart/tx_fifo/E[0]                                            | ResetBootSystem/rst_o_reg_0                             |                4 |             32 |         8.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/IDEXIR_o_reg[22]_0[0]                           | u_Controller/Interpreter/rst_core                       |               16 |             32 |         2.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/Mdu/quociente[31]_i_1_n_0                       | u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/First_Word[31]_i_1_n_0                           |                                                         |               12 |             32 |         2.67 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/IDEXIR_o_reg[20]_1[0]                           | u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/IDEXIR_o_reg[21]_0[0]                           | u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/IDEXIR_o_reg[26]_0[0]                           | u_Controller/Interpreter/rst_core                       |               18 |             32 |         1.78 |
|  clk_o_BUFG             | u_Controller/Interpreter/communication_buffer[31]_i_1_n_0                 | ResetBootSystem/rst_o_reg_0                             |                8 |             32 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/IDEXIR_o_reg[26]_1[0]                           | u_Controller/Interpreter/rst_core                       |               18 |             32 |         1.78 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/IDEXIR_o_reg[23]_1[0]                           | u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/Second_Word[31]_i_1_n_0                          |                                                         |               10 |             32 |         3.20 |
|  clk_o_BUFG             | u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0                          | ResetBootSystem/rst_o_reg_0                             |                8 |             32 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/Mdu/core_reset_reg[0]                           |                                                         |               18 |             32 |         1.78 |
|  clk_o_BUFG             | u_Controller/Interpreter/end_position[31]_i_1_n_0                         | ResetBootSystem/rst_o_reg_0                             |                5 |             32 |         6.40 |
|  ClkDivider/clk_o_pulse | Processor/M1/requested_memory_addr                                        | u_Controller/Interpreter/rst_core                       |               11 |             33 |         3.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/Mdu/quociente_msk[31]_i_1_n_0                   |                                                         |               10 |             33 |         3.30 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/Mdu/acumulador0_i_1_n_0                         |                                                         |                9 |             34 |         3.78 |
|  ClkDivider/clk_o_pulse | Processor/N1/First_Stage/PC                                               | u_Controller/Interpreter/rst_core                       |               27 |             36 |         1.33 |
|  ClkDivider/clk_o_pulse | Processor/N1/First_Stage/temp_instruction                                 |                                                         |               22 |             48 |         2.18 |
|  clk_o_BUFG             | u_Controller/Interpreter/num_of_positions[23]_i_1_n_0                     |                                                         |               11 |             55 |         5.00 |
|  clk_o_BUFG             |                                                                           | ResetBootSystem/rst_o_reg_0                             |               26 |             55 |         2.12 |
|  ClkDivider/clk_o_pulse | Processor/ICache/cache_tag_reg_0_63_0_0_i_1_n_0                           |                                                         |               14 |             56 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/memory_write_reg_2                               |                                                         |               14 |             56 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/Mdu/quociente_msk[31]_i_1_n_0                   | Processor/N1/Second_Stage/Mdu/quociente_msk[30]_i_1_n_0 |               19 |             62 |         3.26 |
|  ClkDivider/clk_o_pulse | u_Controller/Interpreter/E[0]                                             |                                                         |               20 |             64 |         3.20 |
|  ClkDivider/clk_o_pulse | Processor/N1/Fourth_Stage/instruction_finished                            | u_Controller/Interpreter/rst_core                       |               16 |             64 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/Mdu/E[0]                                        |                                                         |               36 |             64 |         1.78 |
|  ClkDivider/clk_o_pulse | Processor/N1/Third_Stage/mdu_start1                                       | Processor/N1/Second_Stage/Mdu/SS[0]                     |               34 |             76 |         2.24 |
|  ClkDivider/clk_o_pulse |                                                                           |                                                         |               36 |             88 |         2.44 |
|  clk_o_BUFG             | Processor/N1/Third_Stage/Data_Address_reg[10]_3                           |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG             | Processor/N1/Third_Stage/memory_mux_selector_reg_1                        |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG             | Processor/N1/Third_Stage/Data_Address_reg[12]_2                           |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG             | Processor/N1/Third_Stage/memory_mux_selector_reg_2                        |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG             | Processor/N1/Third_Stage/memory_mux_selector_reg_0                        |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG             | Processor/N1/Third_Stage/memory_mux_selector_reg                          |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG             | Processor/N1/Third_Stage/Data_Address_reg[11]_2                           |                                                         |               32 |            128 |         4.00 |
|  clk_o_BUFG             | Processor/N1/Third_Stage/Data_Address_reg[10]_2                           |                                                         |               32 |            128 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/core_reset_reg_0                                |                                                         |               33 |            132 |         4.00 |
|  ClkDivider/clk_o_pulse | Processor/N1/Second_Stage/EXMEMPC_o_reg[7]                                |                                                         |               33 |            132 |         4.00 |
|  ClkDivider/clk_o_pulse |                                                                           | u_Controller/Interpreter/rst_core                       |              159 |            465 |         2.92 |
+-------------------------+---------------------------------------------------------------------------+---------------------------------------------------------+------------------+----------------+--------------+


